diff options
Diffstat (limited to 'arch/powerpc/boot/dts/virtex440-ml507.dts')
-rw-r--r-- | arch/powerpc/boot/dts/virtex440-ml507.dts | 124 |
1 files changed, 113 insertions, 11 deletions
diff --git a/arch/powerpc/boot/dts/virtex440-ml507.dts b/arch/powerpc/boot/dts/virtex440-ml507.dts index dc8e78e2dceb..52d8c1ad26a1 100644 --- a/arch/powerpc/boot/dts/virtex440-ml507.dts +++ b/arch/powerpc/boot/dts/virtex440-ml507.dts | |||
@@ -7,6 +7,15 @@ | |||
7 | * This file is licensed under the terms of the GNU General Public License | 7 | * This file is licensed under the terms of the GNU General Public License |
8 | * version 2. This program is licensed "as is" without any warranty of any | 8 | * version 2. This program is licensed "as is" without any warranty of any |
9 | * kind, whether express or implied. | 9 | * kind, whether express or implied. |
10 | * | ||
11 | * --- | ||
12 | * | ||
13 | * Device Tree Generator version: 1.1 | ||
14 | * | ||
15 | * CAUTION: This file is automatically generated by libgen. | ||
16 | * Version: Xilinx EDK 10.1.03 EDK_K_SP3.6 | ||
17 | * | ||
18 | * XPS project directory: ml507_ppc440_emb_ref | ||
10 | */ | 19 | */ |
11 | 20 | ||
12 | /dts-v1/; | 21 | /dts-v1/; |
@@ -22,8 +31,8 @@ | |||
22 | reg = < 0 0x10000000 >; | 31 | reg = < 0 0x10000000 >; |
23 | } ; | 32 | } ; |
24 | chosen { | 33 | chosen { |
25 | bootargs = "console=ttyS0 ip=on root=/dev/ram"; | 34 | bootargs = "console=ttyS0 root=/dev/ram"; |
26 | linux,stdout-path = "/plb@0/serial@83e00000"; | 35 | linux,stdout-path = &RS232_Uart_1; |
27 | } ; | 36 | } ; |
28 | cpus { | 37 | cpus { |
29 | #address-cells = <1>; | 38 | #address-cells = <1>; |
@@ -136,19 +145,19 @@ | |||
136 | compatible = "xlnx,ll-dma-1.00.a"; | 145 | compatible = "xlnx,ll-dma-1.00.a"; |
137 | dcr-reg = < 0x80 0x11 >; | 146 | dcr-reg = < 0x80 0x11 >; |
138 | interrupt-parent = <&xps_intc_0>; | 147 | interrupt-parent = <&xps_intc_0>; |
139 | interrupts = < 9 2 0xa 2 >; | 148 | interrupts = < 10 2 11 2 >; |
140 | } ; | 149 | } ; |
141 | } ; | 150 | } ; |
142 | } ; | 151 | } ; |
143 | plb_v46_0: plb@0 { | 152 | plb_v46_0: plb@0 { |
144 | #address-cells = <1>; | 153 | #address-cells = <1>; |
145 | #size-cells = <1>; | 154 | #size-cells = <1>; |
146 | compatible = "xlnx,plb-v46-1.02.a", "simple-bus"; | 155 | compatible = "xlnx,plb-v46-1.03.a", "simple-bus"; |
147 | ranges ; | 156 | ranges ; |
148 | DIP_Switches_8Bit: gpio@81460000 { | 157 | DIP_Switches_8Bit: gpio@81460000 { |
149 | compatible = "xlnx,xps-gpio-1.00.a"; | 158 | compatible = "xlnx,xps-gpio-1.00.a"; |
150 | interrupt-parent = <&xps_intc_0>; | 159 | interrupt-parent = <&xps_intc_0>; |
151 | interrupts = < 6 2 >; | 160 | interrupts = < 7 2 >; |
152 | reg = < 0x81460000 0x10000 >; | 161 | reg = < 0x81460000 0x10000 >; |
153 | xlnx,all-inputs = <1>; | 162 | xlnx,all-inputs = <1>; |
154 | xlnx,all-inputs-2 = <0>; | 163 | xlnx,all-inputs-2 = <0>; |
@@ -163,6 +172,86 @@ | |||
163 | xlnx,tri-default = <0xffffffff>; | 172 | xlnx,tri-default = <0xffffffff>; |
164 | xlnx,tri-default-2 = <0xffffffff>; | 173 | xlnx,tri-default-2 = <0xffffffff>; |
165 | } ; | 174 | } ; |
175 | FLASH: flash@fc000000 { | ||
176 | bank-width = <2>; | ||
177 | compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash"; | ||
178 | reg = < 0xfc000000 0x2000000 >; | ||
179 | xlnx,family = "virtex5"; | ||
180 | xlnx,include-datawidth-matching-0 = <0x1>; | ||
181 | xlnx,include-datawidth-matching-1 = <0x0>; | ||
182 | xlnx,include-datawidth-matching-2 = <0x0>; | ||
183 | xlnx,include-datawidth-matching-3 = <0x0>; | ||
184 | xlnx,include-negedge-ioregs = <0x0>; | ||
185 | xlnx,include-plb-ipif = <0x1>; | ||
186 | xlnx,include-wrbuf = <0x1>; | ||
187 | xlnx,max-mem-width = <0x10>; | ||
188 | xlnx,mch-native-dwidth = <0x20>; | ||
189 | xlnx,mch-plb-clk-period-ps = <0x2710>; | ||
190 | xlnx,mch-splb-awidth = <0x20>; | ||
191 | xlnx,mch0-accessbuf-depth = <0x10>; | ||
192 | xlnx,mch0-protocol = <0x0>; | ||
193 | xlnx,mch0-rddatabuf-depth = <0x10>; | ||
194 | xlnx,mch1-accessbuf-depth = <0x10>; | ||
195 | xlnx,mch1-protocol = <0x0>; | ||
196 | xlnx,mch1-rddatabuf-depth = <0x10>; | ||
197 | xlnx,mch2-accessbuf-depth = <0x10>; | ||
198 | xlnx,mch2-protocol = <0x0>; | ||
199 | xlnx,mch2-rddatabuf-depth = <0x10>; | ||
200 | xlnx,mch3-accessbuf-depth = <0x10>; | ||
201 | xlnx,mch3-protocol = <0x0>; | ||
202 | xlnx,mch3-rddatabuf-depth = <0x10>; | ||
203 | xlnx,mem0-width = <0x10>; | ||
204 | xlnx,mem1-width = <0x20>; | ||
205 | xlnx,mem2-width = <0x20>; | ||
206 | xlnx,mem3-width = <0x20>; | ||
207 | xlnx,num-banks-mem = <0x1>; | ||
208 | xlnx,num-channels = <0x2>; | ||
209 | xlnx,priority-mode = <0x0>; | ||
210 | xlnx,synch-mem-0 = <0x0>; | ||
211 | xlnx,synch-mem-1 = <0x0>; | ||
212 | xlnx,synch-mem-2 = <0x0>; | ||
213 | xlnx,synch-mem-3 = <0x0>; | ||
214 | xlnx,synch-pipedelay-0 = <0x2>; | ||
215 | xlnx,synch-pipedelay-1 = <0x2>; | ||
216 | xlnx,synch-pipedelay-2 = <0x2>; | ||
217 | xlnx,synch-pipedelay-3 = <0x2>; | ||
218 | xlnx,tavdv-ps-mem-0 = <0x1adb0>; | ||
219 | xlnx,tavdv-ps-mem-1 = <0x3a98>; | ||
220 | xlnx,tavdv-ps-mem-2 = <0x3a98>; | ||
221 | xlnx,tavdv-ps-mem-3 = <0x3a98>; | ||
222 | xlnx,tcedv-ps-mem-0 = <0x1adb0>; | ||
223 | xlnx,tcedv-ps-mem-1 = <0x3a98>; | ||
224 | xlnx,tcedv-ps-mem-2 = <0x3a98>; | ||
225 | xlnx,tcedv-ps-mem-3 = <0x3a98>; | ||
226 | xlnx,thzce-ps-mem-0 = <0x88b8>; | ||
227 | xlnx,thzce-ps-mem-1 = <0x1b58>; | ||
228 | xlnx,thzce-ps-mem-2 = <0x1b58>; | ||
229 | xlnx,thzce-ps-mem-3 = <0x1b58>; | ||
230 | xlnx,thzoe-ps-mem-0 = <0x1b58>; | ||
231 | xlnx,thzoe-ps-mem-1 = <0x1b58>; | ||
232 | xlnx,thzoe-ps-mem-2 = <0x1b58>; | ||
233 | xlnx,thzoe-ps-mem-3 = <0x1b58>; | ||
234 | xlnx,tlzwe-ps-mem-0 = <0x88b8>; | ||
235 | xlnx,tlzwe-ps-mem-1 = <0x0>; | ||
236 | xlnx,tlzwe-ps-mem-2 = <0x0>; | ||
237 | xlnx,tlzwe-ps-mem-3 = <0x0>; | ||
238 | xlnx,twc-ps-mem-0 = <0x2af8>; | ||
239 | xlnx,twc-ps-mem-1 = <0x3a98>; | ||
240 | xlnx,twc-ps-mem-2 = <0x3a98>; | ||
241 | xlnx,twc-ps-mem-3 = <0x3a98>; | ||
242 | xlnx,twp-ps-mem-0 = <0x11170>; | ||
243 | xlnx,twp-ps-mem-1 = <0x2ee0>; | ||
244 | xlnx,twp-ps-mem-2 = <0x2ee0>; | ||
245 | xlnx,twp-ps-mem-3 = <0x2ee0>; | ||
246 | xlnx,xcl0-linesize = <0x4>; | ||
247 | xlnx,xcl0-writexfer = <0x1>; | ||
248 | xlnx,xcl1-linesize = <0x4>; | ||
249 | xlnx,xcl1-writexfer = <0x1>; | ||
250 | xlnx,xcl2-linesize = <0x4>; | ||
251 | xlnx,xcl2-writexfer = <0x1>; | ||
252 | xlnx,xcl3-linesize = <0x4>; | ||
253 | xlnx,xcl3-writexfer = <0x1>; | ||
254 | } ; | ||
166 | Hard_Ethernet_MAC: xps-ll-temac@81c00000 { | 255 | Hard_Ethernet_MAC: xps-ll-temac@81c00000 { |
167 | #address-cells = <1>; | 256 | #address-cells = <1>; |
168 | #size-cells = <1>; | 257 | #size-cells = <1>; |
@@ -185,6 +274,19 @@ | |||
185 | xlnx,txfifo = <0x1000>; | 274 | xlnx,txfifo = <0x1000>; |
186 | } ; | 275 | } ; |
187 | } ; | 276 | } ; |
277 | IIC_EEPROM: i2c@81600000 { | ||
278 | compatible = "xlnx,xps-iic-2.00.a"; | ||
279 | interrupt-parent = <&xps_intc_0>; | ||
280 | interrupts = < 6 2 >; | ||
281 | reg = < 0x81600000 0x10000 >; | ||
282 | xlnx,clk-freq = <0x5f5e100>; | ||
283 | xlnx,family = "virtex5"; | ||
284 | xlnx,gpo-width = <0x1>; | ||
285 | xlnx,iic-freq = <0x186a0>; | ||
286 | xlnx,scl-inertial-delay = <0x0>; | ||
287 | xlnx,sda-inertial-delay = <0x0>; | ||
288 | xlnx,ten-bit-adr = <0x0>; | ||
289 | } ; | ||
188 | LEDs_8Bit: gpio@81400000 { | 290 | LEDs_8Bit: gpio@81400000 { |
189 | compatible = "xlnx,xps-gpio-1.00.a"; | 291 | compatible = "xlnx,xps-gpio-1.00.a"; |
190 | reg = < 0x81400000 0x10000 >; | 292 | reg = < 0x81400000 0x10000 >; |
@@ -220,7 +322,7 @@ | |||
220 | Push_Buttons_5Bit: gpio@81440000 { | 322 | Push_Buttons_5Bit: gpio@81440000 { |
221 | compatible = "xlnx,xps-gpio-1.00.a"; | 323 | compatible = "xlnx,xps-gpio-1.00.a"; |
222 | interrupt-parent = <&xps_intc_0>; | 324 | interrupt-parent = <&xps_intc_0>; |
223 | interrupts = < 7 2 >; | 325 | interrupts = < 8 2 >; |
224 | reg = < 0x81440000 0x10000 >; | 326 | reg = < 0x81440000 0x10000 >; |
225 | xlnx,all-inputs = <1>; | 327 | xlnx,all-inputs = <1>; |
226 | xlnx,all-inputs-2 = <0>; | 328 | xlnx,all-inputs-2 = <0>; |
@@ -237,13 +339,13 @@ | |||
237 | } ; | 339 | } ; |
238 | RS232_Uart_1: serial@83e00000 { | 340 | RS232_Uart_1: serial@83e00000 { |
239 | clock-frequency = <100000000>; | 341 | clock-frequency = <100000000>; |
240 | compatible = "xlnx,xps-uart16550-2.00.a", "ns16550"; | 342 | compatible = "xlnx,xps-uart16550-2.00.b", "ns16550"; |
241 | current-speed = <0x2580>; | 343 | current-speed = <9600>; |
242 | device_type = "serial"; | 344 | device_type = "serial"; |
243 | interrupt-parent = <&xps_intc_0>; | 345 | interrupt-parent = <&xps_intc_0>; |
244 | interrupts = < 8 2 >; | 346 | interrupts = < 9 2 >; |
245 | reg = < 0x83e00000 0x10000 >; | 347 | reg = < 0x83e00000 0x10000 >; |
246 | reg-offset = <3>; | 348 | reg-offset = <0x1003>; |
247 | reg-shift = <2>; | 349 | reg-shift = <2>; |
248 | xlnx,family = "virtex5"; | 350 | xlnx,family = "virtex5"; |
249 | xlnx,has-external-rclk = <0>; | 351 | xlnx,has-external-rclk = <0>; |
@@ -268,7 +370,7 @@ | |||
268 | compatible = "xlnx,xps-intc-1.00.a"; | 370 | compatible = "xlnx,xps-intc-1.00.a"; |
269 | interrupt-controller ; | 371 | interrupt-controller ; |
270 | reg = < 0x81800000 0x10000 >; | 372 | reg = < 0x81800000 0x10000 >; |
271 | xlnx,num-intr-inputs = <0xb>; | 373 | xlnx,num-intr-inputs = <0xc>; |
272 | } ; | 374 | } ; |
273 | xps_timebase_wdt_1: xps-timebase-wdt@83a00000 { | 375 | xps_timebase_wdt_1: xps-timebase-wdt@83a00000 { |
274 | compatible = "xlnx,xps-timebase-wdt-1.00.b"; | 376 | compatible = "xlnx,xps-timebase-wdt-1.00.b"; |