1 files changed, 177 insertions, 0 deletions

diff --git a/arch/powerpc/boot/dts/tqm5200.dts b/arch/powerpc/boot/dts/tqm5200.dts
new file mode 100644
index 000000000000..c86464f007da
--- /dev/null
+++ b/arch/powerpc/boot/dts/tqm5200.dts
@@ -0,0 +1,177 @@
+/*
+ * TQM5200 board Device Tree Source
+ *
+ * Copyright (C) 2007 Semihalf
+ * Marian Balakowicz <m8@semihalf.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/ {
+        model = "tqc,tqm5200";
+        compatible = "tqc,tqm5200";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                PowerPC,5200@0 {
+                        device_type = "cpu";
+                        reg = <0>;
+                        d-cache-line-size = <20>;
+                        i-cache-line-size = <20>;
+                        d-cache-size = <4000>;          // L1, 16K
+                        i-cache-size = <4000>;          // L1, 16K
+                        timebase-frequency = <0>;       // from bootloader
+                        bus-frequency = <0>;            // from bootloader
+                        clock-frequency = <0>;          // from bootloader
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <00000000 04000000>;      // 64MB
+        };
+
+        soc5200@f0000000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "fsl,mpc5200-immr";
+                ranges = <0 f0000000 0000c000>;
+                reg = <f0000000 00000100>;
+                bus-frequency = <0>;            // from bootloader
+                system-frequency = <0>;         // from bootloader
+
+                cdm@200 {
+                        compatible = "fsl,mpc5200-cdm";
+                        reg = <200 38>;
+                };
+
+                mpc5200_pic: interrupt-controller@500 {
+                        // 5200 interrupts are encoded into two levels;
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                        compatible = "fsl,mpc5200-pic";
+                        reg = <500 80>;
+                };
+
+                timer@600 {     // General Purpose Timer
+                        compatible = "fsl,mpc5200-gpt";
+                        reg = <600 10>;
+                        interrupts = <1 9 0>;
+                        interrupt-parent = <&mpc5200_pic>;
+                        fsl,has-wdt;
+                };
+
+                gpio@b00 {
+                        compatible = "fsl,mpc5200-gpio";
+                        reg = <b00 40>;
+                        interrupts = <1 7 0>;
+                        interrupt-parent = <&mpc5200_pic>;
+                };
+
+                usb@1000 {
+                        compatible = "fsl,mpc5200-ohci","ohci-be";
+                        reg = <1000 ff>;
+                        interrupts = <2 6 0>;
+                        interrupt-parent = <&mpc5200_pic>;
+                };
+
+                dma-controller@1200 {
+                        compatible = "fsl,mpc5200-bestcomm";
+                        reg = <1200 80>;
+                        interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
+                                      3 4 0  3 5 0  3 6 0  3 7 0
+                                      3 8 0  3 9 0  3 a 0  3 b 0
+                                      3 c 0  3 d 0  3 e 0  3 f 0>;
+                        interrupt-parent = <&mpc5200_pic>;
+                };
+
+                xlb@1f00 {
+                        compatible = "fsl,mpc5200-xlb";
+                        reg = <1f00 100>;
+                };
+
+                serial@2000 {           // PSC1
+                        device_type = "serial";
+                        compatible = "fsl,mpc5200-psc-uart";
+                        port-number = <0>;  // Logical port assignment
+                        reg = <2000 100>;
+                        interrupts = <2 1 0>;
+                        interrupt-parent = <&mpc5200_pic>;
+                };
+
+                serial@2200 {           // PSC2
+                        device_type = "serial";
+                        compatible = "fsl,mpc5200-psc-uart";
+                        port-number = <1>;  // Logical port assignment
+                        reg = <2200 100>;
+                        interrupts = <2 2 0>;
+                        interrupt-parent = <&mpc5200_pic>;
+                };
+
+                serial@2400 {           // PSC3
+                        device_type = "serial";
+                        compatible = "fsl,mpc5200-psc-uart";
+                        port-number = <2>;  // Logical port assignment
+                        reg = <2400 100>;
+                        interrupts = <2 3 0>;
+                        interrupt-parent = <&mpc5200_pic>;
+                };
+
+                ethernet@3000 {
+                        device_type = "network";
+                        compatible = "fsl,mpc5200-fec";
+                        reg = <3000 800>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <2 5 0>;
+                        interrupt-parent = <&mpc5200_pic>;
+                };
+
+                ata@3a00 {
+                        compatible = "fsl,mpc5200-ata";
+                        reg = <3a00 100>;
+                        interrupts = <2 7 0>;
+                        interrupt-parent = <&mpc5200_pic>;
+                };
+
+                i2c@3d40 {
+                        compatible = "fsl,mpc5200-i2c","fsl-i2c";
+                        reg = <3d40 40>;
+                        interrupts = <2 10 0>;
+                        interrupt-parent = <&mpc5200_pic>;
+                        fsl5200-clocking;
+                };
+
+                sram@8000 {
+                        compatible = "fsl,mpc5200-sram";
+                        reg = <8000 4000>;
+                };
+        };
+
+        pci@f0000d00 {
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                compatible = "fsl,mpc5200-pci";
+                reg = <f0000d00 100>;
+                interrupt-map-mask = <f800 0 0 7>;
+                interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3
+                                 c000 0 0 2 &mpc5200_pic 0 0 3
+                                 c000 0 0 3 &mpc5200_pic 0 0 3
+                                 c000 0 0 4 &mpc5200_pic 0 0 3>;
+                clock-frequency = <0>; // From boot loader
+                interrupts = <2 8 0 2 9 0 2 a 0>;
+                interrupt-parent = <&mpc5200_pic>;
+                bus-range = <0 0>;
+                ranges = <42000000 0 80000000 80000000 0 10000000
+                          02000000 0 90000000 90000000 0 10000000
+                          01000000 0 00000000 a0000000 0 01000000>;
+        };
+};