1 files changed, 156 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/t104xrdb.dtsi b/arch/powerpc/boot/dts/t104xrdb.dtsi
new file mode 100644
index 000000000000..1cf0f3c5f7e5
--- /dev/null
+++ b/arch/powerpc/boot/dts/t104xrdb.dtsi
@@ -0,0 +1,156 @@
+/*
+ * T1040RDB/T1042RDB Device Tree Source
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/ {
+        ifc: localbus@ffe124000 {
+                reg = <0xf 0xfe124000 0 0x2000>;
+                ranges = <0 0 0xf 0xe8000000 0x08000000
+                          2 0 0xf 0xff800000 0x00010000
+                          3 0 0xf 0xffdf0000 0x00008000>;
+                nor@0,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "cfi-flash";
+                        reg = <0x0 0x0 0x8000000>;
+                        bank-width = <2>;
+                        device-width = <1>;
+                };
+                nand@2,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,ifc-nand";
+                        reg = <0x2 0x0 0x10000>;
+                };
+                cpld@3,0 {
+                        reg = <3 0 0x300>;
+                };
+        };
+        memory {
+                device_type = "memory";
+        };
+        dcsr: dcsr@f00000000 {
+                ranges = <0x00000000 0xf 0x00000000 0x01072000>;
+        };
+        soc: soc@ffe000000 {
+                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+                reg = <0xf 0xfe000000 0 0x00001000>;
+                spi@110000 {
+                        flash@0 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "micron,n25q512a";
+                                reg = <0>;
+                                spi-max-frequency = <10000000>; /* input clock */
+                        };
+                };
+                i2c@118100 {
+                        pca9546@77 {
+                                compatible = "nxp,pca9546";
+                                reg = <0x77>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+                };
+        };
+        pci0: pcie@ffe240000 {
+                reg = <0xf 0xfe240000 0 0x10000>;
+                ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x10000000
+                          0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
+                pcie@0 {
+                        ranges = <0x02000000 0 0xe0000000
+                                  0x02000000 0 0xe0000000
+                                  0 0x10000000
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00010000>;
+                };
+        };
+        pci1: pcie@ffe250000 {
+                reg = <0xf 0xfe250000 0 0x10000>;
+                ranges = <0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000
+                          0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
+                pcie@0 {
+                        ranges = <0x02000000 0 0xe0000000
+                                  0x02000000 0 0xe0000000
+                                  0 0x10000000
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00010000>;
+                };
+        };
+        pci2: pcie@ffe260000 {
+                reg = <0xf 0xfe260000 0 0x10000>;
+                ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000
+                          0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
+                pcie@0 {
+                        ranges = <0x02000000 0 0xe0000000
+                                  0x02000000 0 0xe0000000
+                                  0 0x10000000
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00010000>;
+                };
+        };
+        pci3: pcie@ffe270000 {
+                reg = <0xf 0xfe270000 0 0x10000>;
+                ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
+                          0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
+                pcie@0 {
+                        ranges = <0x02000000 0 0xe0000000
+                                  0x02000000 0 0xe0000000
+                                  0 0x10000000
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00010000>;
+                };
+        };
+};

diff --git a/arch/powerpc/boot/dts/t104xrdb.dtsi b/arch/powerpc/boot/dts/t104xrdb.dtsi new file mode 100644 index 000000000000..1cf0f3c5f7e5 --- /dev/null +++ b/arch/powerpc/boot/dts/t104xrdb.dtsi
@@ -0,0 +1,156 @@
	1	/*
	2	* T1040RDB/T1042RDB Device Tree Source
	3	*
	4	* Copyright 2014 Freescale Semiconductor Inc.
	5	*
	6	* Redistribution and use in source and binary forms, with or without
	7	* modification, are permitted provided that the following conditions are met:
	8	* * Redistributions of source code must retain the above copyright
	9	* notice, this list of conditions and the following disclaimer.
	10	* * Redistributions in binary form must reproduce the above copyright
	11	* notice, this list of conditions and the following disclaimer in the
	12	* documentation and/or other materials provided with the distribution.
	13	* * Neither the name of Freescale Semiconductor nor the
	14	* names of its contributors may be used to endorse or promote products
	15	* derived from this software without specific prior written permission.
	16	*
	17	*
	18	* ALTERNATIVELY, this software may be distributed under the terms of the
	19	* GNU General Public License ("GPL") as published by the Free Software
	20	* Foundation, either version 2 of that License or (at your option) any
	21	* later version.
	22	*
	23	* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
	24	* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	25	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	26	* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
	27	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	28	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	29	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	30	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	31	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	32	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	33	*/
	34
	35	/ {
	36
	37	ifc: localbus@ffe124000 {
	38	reg = <0xf 0xfe124000 0 0x2000>;
	39	ranges = <0 0 0xf 0xe8000000 0x08000000
	40	2 0 0xf 0xff800000 0x00010000
	41	3 0 0xf 0xffdf0000 0x00008000>;
	42
	43	nor@0,0 {
	44	#address-cells = <1>;
	45	#size-cells = <1>;
	46	compatible = "cfi-flash";
	47	reg = <0x0 0x0 0x8000000>;
	48	bank-width = <2>;
	49	device-width = <1>;
	50	};
	51
	52	nand@2,0 {
	53	#address-cells = <1>;
	54	#size-cells = <1>;
	55	compatible = "fsl,ifc-nand";
	56	reg = <0x2 0x0 0x10000>;
	57	};
	58
	59	cpld@3,0 {
	60	reg = <3 0 0x300>;
	61	};
	62	};
	63
	64	memory {
	65	device_type = "memory";
	66	};
	67
	68	dcsr: dcsr@f00000000 {
	69	ranges = <0x00000000 0xf 0x00000000 0x01072000>;
	70	};
	71
	72	soc: soc@ffe000000 {
	73	ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
	74	reg = <0xf 0xfe000000 0 0x00001000>;
	75
	76	spi@110000 {
	77	flash@0 {
	78	#address-cells = <1>;
	79	#size-cells = <1>;
	80	compatible = "micron,n25q512a";
	81	reg = <0>;
	82	spi-max-frequency = <10000000>; /* input clock */
	83	};
	84	};
	85
	86	i2c@118100 {
	87	pca9546@77 {
	88	compatible = "nxp,pca9546";
	89	reg = <0x77>;
	90	#address-cells = <1>;
	91	#size-cells = <0>;
	92	};
	93	};
	94
	95	};
	96
	97	pci0: pcie@ffe240000 {
	98	reg = <0xf 0xfe240000 0 0x10000>;
	99	ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x10000000
	100	0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
	101	pcie@0 {
	102	ranges = <0x02000000 0 0xe0000000
	103	0x02000000 0 0xe0000000
	104	0 0x10000000
	105
	106	0x01000000 0 0x00000000
	107	0x01000000 0 0x00000000
	108	0 0x00010000>;
	109	};
	110	};
	111
	112	pci1: pcie@ffe250000 {
	113	reg = <0xf 0xfe250000 0 0x10000>;
	114	ranges = <0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000
	115	0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
	116	pcie@0 {
	117	ranges = <0x02000000 0 0xe0000000
	118	0x02000000 0 0xe0000000
	119	0 0x10000000
	120
	121	0x01000000 0 0x00000000
	122	0x01000000 0 0x00000000
	123	0 0x00010000>;
	124	};
	125	};
	126
	127	pci2: pcie@ffe260000 {
	128	reg = <0xf 0xfe260000 0 0x10000>;
	129	ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000
	130	0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
	131	pcie@0 {
	132	ranges = <0x02000000 0 0xe0000000
	133	0x02000000 0 0xe0000000
	134	0 0x10000000
	135
	136	0x01000000 0 0x00000000
	137	0x01000000 0 0x00000000
	138	0 0x00010000>;
	139	};
	140	};
	141
	142	pci3: pcie@ffe270000 {
	143	reg = <0xf 0xfe270000 0 0x10000>;
	144	ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
	145	0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
	146	pcie@0 {
	147	ranges = <0x02000000 0 0xe0000000
	148	0x02000000 0 0xe0000000
	149	0 0x10000000
	150
	151	0x01000000 0 0x00000000
	152	0x01000000 0 0x00000000
	153	0 0x00010000>;
	154	};
	155	};
	156	};