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-rw-r--r--arch/powerpc/boot/dts/prpmc2800.dts336
1 files changed, 161 insertions, 175 deletions
diff --git a/arch/powerpc/boot/dts/prpmc2800.dts b/arch/powerpc/boot/dts/prpmc2800.dts
index 297dfa53fe9e..1ee6ff43dd57 100644
--- a/arch/powerpc/boot/dts/prpmc2800.dts
+++ b/arch/powerpc/boot/dts/prpmc2800.dts
@@ -11,6 +11,8 @@
11 * if it can determine the exact PrPMC type. 11 * if it can determine the exact PrPMC type.
12 */ 12 */
13 13
14/dts-v1/;
15
14/ { 16/ {
15 #address-cells = <1>; 17 #address-cells = <1>;
16 #size-cells = <1>; 18 #size-cells = <1>;
@@ -25,46 +27,46 @@
25 PowerPC,7447 { 27 PowerPC,7447 {
26 device_type = "cpu"; 28 device_type = "cpu";
27 reg = <0>; 29 reg = <0>;
28 clock-frequency = <2bb0b140>; /* Default (733 MHz) */ 30 clock-frequency = <733333333>; /* Default */
29 bus-frequency = <7f28155>; /* 133.333333 MHz */ 31 bus-frequency = <133333333>;
30 timebase-frequency = <1fca055>; /* 33.333333 MHz */ 32 timebase-frequency = <33333333>;
31 i-cache-line-size = <20>; 33 i-cache-line-size = <32>;
32 d-cache-line-size = <20>; 34 d-cache-line-size = <32>;
33 i-cache-size = <8000>; 35 i-cache-size = <32768>;
34 d-cache-size = <8000>; 36 d-cache-size = <32768>;
35 }; 37 };
36 }; 38 };
37 39
38 memory { 40 memory {
39 device_type = "memory"; 41 device_type = "memory";
40 reg = <00000000 20000000>; /* Default (512MB) */ 42 reg = <0x0 0x20000000>; /* Default (512MB) */
41 }; 43 };
42 44
43 mv64x60@f1000000 { /* Marvell Discovery */ 45 system-controller@f1000000 { /* Marvell Discovery mv64360 */
44 #address-cells = <1>; 46 #address-cells = <1>;
45 #size-cells = <1>; 47 #size-cells = <1>;
46 model = "mv64360"; /* Default */ 48 model = "mv64360"; /* Default */
47 compatible = "marvell,mv64x60"; 49 compatible = "marvell,mv64360";
48 clock-frequency = <7f28155>; /* 133.333333 MHz */ 50 clock-frequency = <133333333>;
49 reg = <f1000000 00010000>; 51 reg = <0xf1000000 0x10000>;
50 virtual-reg = <f1000000>; 52 virtual-reg = <0xf1000000>;
51 ranges = <88000000 88000000 01000000 /* PCI 0 I/O Space */ 53 ranges = <0x88000000 0x88000000 0x1000000 /* PCI 0 I/O Space */
52 80000000 80000000 08000000 /* PCI 0 MEM Space */ 54 0x80000000 0x80000000 0x8000000 /* PCI 0 MEM Space */
53 a0000000 a0000000 04000000 /* User FLASH */ 55 0xa0000000 0xa0000000 0x4000000 /* User FLASH */
54 00000000 f1000000 00010000 /* Bridge's regs */ 56 0x00000000 0xf1000000 0x0010000 /* Bridge's regs */
55 f2000000 f2000000 00040000>; /* Integrated SRAM */ 57 0xf2000000 0xf2000000 0x0040000>;/* Integrated SRAM */
56 58
57 flash@a0000000 { 59 flash@a0000000 {
58 device_type = "rom"; 60 device_type = "rom";
59 compatible = "direct-mapped"; 61 compatible = "direct-mapped";
60 reg = <a0000000 4000000>; /* Default (64MB) */ 62 reg = <0xa0000000 0x4000000>; /* Default (64MB) */
61 probe-type = "CFI"; 63 probe-type = "CFI";
62 bank-width = <4>; 64 bank-width = <4>;
63 partitions = <00000000 00100000 /* RO */ 65 partitions = <0x00000000 0x00100000 /* RO */
64 00100000 00040001 /* RW */ 66 0x00100000 0x00040001 /* RW */
65 00140000 00400000 /* RO */ 67 0x00140000 0x00400000 /* RO */
66 00540000 039c0000 /* RO */ 68 0x00540000 0x039c0000 /* RO */
67 03f00000 00100000>; /* RO */ 69 0x03f00000 0x00100000>; /* RO */
68 partition-names = "FW Image A", "FW Config Data", "Kernel Image", "Filesystem", "FW Image B"; 70 partition-names = "FW Image A", "FW Config Data", "Kernel Image", "Filesystem", "FW Image B";
69 }; 71 };
70 72
@@ -72,171 +74,153 @@
72 #address-cells = <1>; 74 #address-cells = <1>;
73 #size-cells = <0>; 75 #size-cells = <0>;
74 device_type = "mdio"; 76 device_type = "mdio";
75 compatible = "marvell,mv64x60-mdio"; 77 compatible = "marvell,mv64360-mdio";
76 ethernet-phy@1 { 78 PHY0: ethernet-phy@1 {
77 device_type = "ethernet-phy"; 79 device_type = "ethernet-phy";
78 compatible = "broadcom,bcm5421"; 80 compatible = "broadcom,bcm5421";
79 interrupts = <4c>; /* GPP 12 */ 81 interrupts = <76>; /* GPP 12 */
80 interrupt-parent = <&/mv64x60/pic>; 82 interrupt-parent = <&PIC>;
81 reg = <1>; 83 reg = <1>;
82 }; 84 };
83 ethernet-phy@3 { 85 PHY1: ethernet-phy@3 {
84 device_type = "ethernet-phy"; 86 device_type = "ethernet-phy";
85 compatible = "broadcom,bcm5421"; 87 compatible = "broadcom,bcm5421";
86 interrupts = <4c>; /* GPP 12 */ 88 interrupts = <76>; /* GPP 12 */
87 interrupt-parent = <&/mv64x60/pic>; 89 interrupt-parent = <&PIC>;
88 reg = <3>; 90 reg = <3>;
89 }; 91 };
90 }; 92 };
91 93
92 ethernet@2000 { 94 ethernet-group@2000 {
93 reg = <2000 2000>; 95 #address-cells = <1>;
94 eth0 { 96 #size-cells = <0>;
97 compatible = "marvell,mv64360-eth-group";
98 reg = <0x2000 0x2000>;
99 ethernet@0 {
95 device_type = "network"; 100 device_type = "network";
96 compatible = "marvell,mv64x60-eth"; 101 compatible = "marvell,mv64360-eth";
97 block-index = <0>; 102 reg = <0>;
98 interrupts = <20>; 103 interrupts = <32>;
99 interrupt-parent = <&/mv64x60/pic>; 104 interrupt-parent = <&PIC>;
100 phy = <&/mv64x60/mdio/ethernet-phy@1>; 105 phy = <&PHY0>;
101 local-mac-address = [ 00 00 00 00 00 00 ]; 106 local-mac-address = [ 00 00 00 00 00 00 ];
102 }; 107 };
103 eth1 { 108 ethernet@1 {
104 device_type = "network"; 109 device_type = "network";
105 compatible = "marvell,mv64x60-eth"; 110 compatible = "marvell,mv64360-eth";
106 block-index = <1>; 111 reg = <1>;
107 interrupts = <21>; 112 interrupts = <33>;
108 interrupt-parent = <&/mv64x60/pic>; 113 interrupt-parent = <&PIC>;
109 phy = <&/mv64x60/mdio/ethernet-phy@3>; 114 phy = <&PHY1>;
110 local-mac-address = [ 00 00 00 00 00 00 ]; 115 local-mac-address = [ 00 00 00 00 00 00 ];
111 }; 116 };
112 }; 117 };
113 118
114 sdma@4000 { 119 SDMA0: sdma@4000 {
115 device_type = "dma"; 120 compatible = "marvell,mv64360-sdma";
116 compatible = "marvell,mv64x60-sdma"; 121 reg = <0x4000 0xc18>;
117 reg = <4000 c18>; 122 virtual-reg = <0xf1004000>;
118 virtual-reg = <f1004000>; 123 interrupts = <36>;
119 interrupt-base = <0>; 124 interrupt-parent = <&PIC>;
120 interrupts = <24>;
121 interrupt-parent = <&/mv64x60/pic>;
122 }; 125 };
123 126
124 sdma@6000 { 127 SDMA1: sdma@6000 {
125 device_type = "dma"; 128 compatible = "marvell,mv64360-sdma";
126 compatible = "marvell,mv64x60-sdma"; 129 reg = <0x6000 0xc18>;
127 reg = <6000 c18>; 130 virtual-reg = <0xf1006000>;
128 virtual-reg = <f1006000>; 131 interrupts = <38>;
129 interrupt-base = <0>; 132 interrupt-parent = <&PIC>;
130 interrupts = <26>;
131 interrupt-parent = <&/mv64x60/pic>;
132 }; 133 };
133 134
134 brg@b200 { 135 BRG0: brg@b200 {
135 compatible = "marvell,mv64x60-brg"; 136 compatible = "marvell,mv64360-brg";
136 reg = <b200 8>; 137 reg = <0xb200 0x8>;
137 clock-src = <8>; 138 clock-src = <8>;
138 clock-frequency = <7ed6b40>; 139 clock-frequency = <133333333>;
139 current-speed = <2580>; 140 current-speed = <9600>;
140 bcr = <0>;
141 }; 141 };
142 142
143 brg@b208 { 143 BRG1: brg@b208 {
144 compatible = "marvell,mv64x60-brg"; 144 compatible = "marvell,mv64360-brg";
145 reg = <b208 8>; 145 reg = <0xb208 0x8>;
146 clock-src = <8>; 146 clock-src = <8>;
147 clock-frequency = <7ed6b40>; 147 clock-frequency = <133333333>;
148 current-speed = <2580>; 148 current-speed = <9600>;
149 bcr = <0>;
150 }; 149 };
151 150
152 cunit@f200 { 151 CUNIT: cunit@f200 {
153 reg = <f200 200>; 152 reg = <0xf200 0x200>;
154 }; 153 };
155 154
156 mpscrouting@b400 { 155 MPSCROUTING: mpscrouting@b400 {
157 reg = <b400 c>; 156 reg = <0xb400 0xc>;
158 }; 157 };
159 158
160 mpscintr@b800 { 159 MPSCINTR: mpscintr@b800 {
161 reg = <b800 100>; 160 reg = <0xb800 0x100>;
162 virtual-reg = <f100b800>; 161 virtual-reg = <0xf100b800>;
163 }; 162 };
164 163
165 mpsc@8000 { 164 MPSC0: mpsc@8000 {
166 device_type = "serial"; 165 device_type = "serial";
167 compatible = "marvell,mpsc"; 166 compatible = "marvell,mv64360-mpsc";
168 reg = <8000 38>; 167 reg = <0x8000 0x38>;
169 virtual-reg = <f1008000>; 168 virtual-reg = <0xf1008000>;
170 sdma = <&/mv64x60/sdma@4000>; 169 sdma = <&SDMA0>;
171 brg = <&/mv64x60/brg@b200>; 170 brg = <&BRG0>;
172 cunit = <&/mv64x60/cunit@f200>; 171 cunit = <&CUNIT>;
173 mpscrouting = <&/mv64x60/mpscrouting@b400>; 172 mpscrouting = <&MPSCROUTING>;
174 mpscintr = <&/mv64x60/mpscintr@b800>; 173 mpscintr = <&MPSCINTR>;
175 block-index = <0>; 174 cell-index = <0>;
176 max_idle = <28>; 175 interrupts = <40>;
177 chr_1 = <0>; 176 interrupt-parent = <&PIC>;
178 chr_2 = <0>;
179 chr_10 = <3>;
180 mpcr = <0>;
181 interrupts = <28>;
182 interrupt-parent = <&/mv64x60/pic>;
183 }; 177 };
184 178
185 mpsc@9000 { 179 MPSC1: mpsc@9000 {
186 device_type = "serial"; 180 device_type = "serial";
187 compatible = "marvell,mpsc"; 181 compatible = "marvell,mv64360-mpsc";
188 reg = <9000 38>; 182 reg = <0x9000 0x38>;
189 virtual-reg = <f1009000>; 183 virtual-reg = <0xf1009000>;
190 sdma = <&/mv64x60/sdma@6000>; 184 sdma = <&SDMA1>;
191 brg = <&/mv64x60/brg@b208>; 185 brg = <&BRG1>;
192 cunit = <&/mv64x60/cunit@f200>; 186 cunit = <&CUNIT>;
193 mpscrouting = <&/mv64x60/mpscrouting@b400>; 187 mpscrouting = <&MPSCROUTING>;
194 mpscintr = <&/mv64x60/mpscintr@b800>; 188 mpscintr = <&MPSCINTR>;
195 block-index = <1>; 189 cell-index = <1>;
196 max_idle = <28>; 190 interrupts = <42>;
197 chr_1 = <0>; 191 interrupt-parent = <&PIC>;
198 chr_2 = <0>;
199 chr_10 = <3>;
200 mpcr = <0>;
201 interrupts = <2a>;
202 interrupt-parent = <&/mv64x60/pic>;
203 }; 192 };
204 193
205 wdt@b410 { /* watchdog timer */ 194 wdt@b410 { /* watchdog timer */
206 compatible = "marvell,mv64x60-wdt"; 195 compatible = "marvell,mv64360-wdt";
207 reg = <b410 8>; 196 reg = <0xb410 0x8>;
208 timeout = <a>; /* wdt timeout in seconds */
209 }; 197 };
210 198
211 i2c@c000 { 199 i2c@c000 {
212 device_type = "i2c"; 200 device_type = "i2c";
213 compatible = "marvell,mv64x60-i2c"; 201 compatible = "marvell,mv64360-i2c";
214 reg = <c000 20>; 202 reg = <0xc000 0x20>;
215 virtual-reg = <f100c000>; 203 virtual-reg = <0xf100c000>;
216 freq_m = <8>; 204 interrupts = <37>;
217 freq_n = <3>; 205 interrupt-parent = <&PIC>;
218 timeout = <3e8>; /* 1000 = 1 second */
219 retries = <1>;
220 interrupts = <25>;
221 interrupt-parent = <&/mv64x60/pic>;
222 }; 206 };
223 207
224 pic { 208 PIC: pic {
225 #interrupt-cells = <1>; 209 #interrupt-cells = <1>;
226 #address-cells = <0>; 210 #address-cells = <0>;
227 compatible = "marvell,mv64x60-pic"; 211 compatible = "marvell,mv64360-pic";
228 reg = <0000 88>; 212 reg = <0x0 0x88>;
229 interrupt-controller; 213 interrupt-controller;
230 }; 214 };
231 215
232 mpp@f000 { 216 mpp@f000 {
233 compatible = "marvell,mv64x60-mpp"; 217 compatible = "marvell,mv64360-mpp";
234 reg = <f000 10>; 218 reg = <0xf000 0x10>;
235 }; 219 };
236 220
237 gpp@f100 { 221 gpp@f100 {
238 compatible = "marvell,mv64x60-gpp"; 222 compatible = "marvell,mv64360-gpp";
239 reg = <f100 20>; 223 reg = <0xf100 0x20>;
240 }; 224 };
241 225
242 pci@80000000 { 226 pci@80000000 {
@@ -244,73 +228,75 @@
244 #size-cells = <2>; 228 #size-cells = <2>;
245 #interrupt-cells = <1>; 229 #interrupt-cells = <1>;
246 device_type = "pci"; 230 device_type = "pci";
247 compatible = "marvell,mv64x60-pci"; 231 compatible = "marvell,mv64360-pci";
248 reg = <0cf8 8>; 232 reg = <0xcf8 0x8>;
249 ranges = <01000000 0 0 88000000 0 01000000 233 ranges = <0x01000000 0x0 0x0
250 02000000 0 80000000 80000000 0 08000000>; 234 0x88000000 0x0 0x01000000
251 bus-range = <0 ff>; 235 0x02000000 0x0 0x80000000
252 clock-frequency = <3EF1480>; 236 0x80000000 0x0 0x08000000>;
253 interrupt-pci-iack = <0c34>; 237 bus-range = <0 255>;
254 interrupt-parent = <&/mv64x60/pic>; 238 clock-frequency = <66000000>;
255 interrupt-map-mask = <f800 0 0 7>; 239 interrupt-pci-iack = <0xc34>;
240 interrupt-parent = <&PIC>;
241 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
256 interrupt-map = < 242 interrupt-map = <
257 /* IDSEL 0x0a */ 243 /* IDSEL 0x0a */
258 5000 0 0 1 &/mv64x60/pic 50 244 0x5000 0 0 1 &PIC 80
259 5000 0 0 2 &/mv64x60/pic 51 245 0x5000 0 0 2 &PIC 81
260 5000 0 0 3 &/mv64x60/pic 5b 246 0x5000 0 0 3 &PIC 91
261 5000 0 0 4 &/mv64x60/pic 5d 247 0x5000 0 0 4 &PIC 93
262 248
263 /* IDSEL 0x0b */ 249 /* IDSEL 0x0b */
264 5800 0 0 1 &/mv64x60/pic 5b 250 0x5800 0 0 1 &PIC 91
265 5800 0 0 2 &/mv64x60/pic 5d 251 0x5800 0 0 2 &PIC 93
266 5800 0 0 3 &/mv64x60/pic 50 252 0x5800 0 0 3 &PIC 80
267 5800 0 0 4 &/mv64x60/pic 51 253 0x5800 0 0 4 &PIC 81
268 254
269 /* IDSEL 0x0c */ 255 /* IDSEL 0x0c */
270 6000 0 0 1 &/mv64x60/pic 5b 256 0x6000 0 0 1 &PIC 91
271 6000 0 0 2 &/mv64x60/pic 5d 257 0x6000 0 0 2 &PIC 93
272 6000 0 0 3 &/mv64x60/pic 50 258 0x6000 0 0 3 &PIC 80
273 6000 0 0 4 &/mv64x60/pic 51 259 0x6000 0 0 4 &PIC 81
274 260
275 /* IDSEL 0x0d */ 261 /* IDSEL 0x0d */
276 6800 0 0 1 &/mv64x60/pic 5d 262 0x6800 0 0 1 &PIC 93
277 6800 0 0 2 &/mv64x60/pic 50 263 0x6800 0 0 2 &PIC 80
278 6800 0 0 3 &/mv64x60/pic 51 264 0x6800 0 0 3 &PIC 81
279 6800 0 0 4 &/mv64x60/pic 5b 265 0x6800 0 0 4 &PIC 91
280 >; 266 >;
281 }; 267 };
282 268
283 cpu-error@0070 { 269 cpu-error@0070 {
284 compatible = "marvell,mv64x60-cpu-error"; 270 compatible = "marvell,mv64360-cpu-error";
285 reg = <0070 10 0128 28>; 271 reg = <0x70 0x10 0x128 0x28>;
286 interrupts = <03>; 272 interrupts = <3>;
287 interrupt-parent = <&/mv64x60/pic>; 273 interrupt-parent = <&PIC>;
288 }; 274 };
289 275
290 sram-ctrl@0380 { 276 sram-ctrl@0380 {
291 compatible = "marvell,mv64x60-sram-ctrl"; 277 compatible = "marvell,mv64360-sram-ctrl";
292 reg = <0380 80>; 278 reg = <0x380 0x80>;
293 interrupts = <0d>; 279 interrupts = <13>;
294 interrupt-parent = <&/mv64x60/pic>; 280 interrupt-parent = <&PIC>;
295 }; 281 };
296 282
297 pci-error@1d40 { 283 pci-error@1d40 {
298 compatible = "marvell,mv64x60-pci-error"; 284 compatible = "marvell,mv64360-pci-error";
299 reg = <1d40 40 0c28 4>; 285 reg = <0x1d40 0x40 0xc28 0x4>;
300 interrupts = <0c>; 286 interrupts = <12>;
301 interrupt-parent = <&/mv64x60/pic>; 287 interrupt-parent = <&PIC>;
302 }; 288 };
303 289
304 mem-ctrl@1400 { 290 mem-ctrl@1400 {
305 compatible = "marvell,mv64x60-mem-ctrl"; 291 compatible = "marvell,mv64360-mem-ctrl";
306 reg = <1400 60>; 292 reg = <0x1400 0x60>;
307 interrupts = <11>; 293 interrupts = <17>;
308 interrupt-parent = <&/mv64x60/pic>; 294 interrupt-parent = <&PIC>;
309 }; 295 };
310 }; 296 };
311 297
312 chosen { 298 chosen {
313 bootargs = "ip=on"; 299 bootargs = "ip=on";
314 linux,stdout-path = "/mv64x60@f1000000/mpsc@8000"; 300 linux,stdout-path = &MPSC0;
315 }; 301 };
316}; 302};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 16:34:58 -0500