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-rw-r--r--arch/powerpc/boot/dts/mucmc52.dts332
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diff --git a/arch/powerpc/boot/dts/mucmc52.dts b/arch/powerpc/boot/dts/mucmc52.dts
new file mode 100644
index 000000000000..b72a7581d798
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+++ b/arch/powerpc/boot/dts/mucmc52.dts
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1/*
2 * Manroland mucmc52 board Device Tree Source
3 *
4 * Copyright (C) 2009 DENX Software Engineering GmbH
5 * Heiko Schocher <hs@denx.de>
6 * Copyright 2006-2007 Secret Lab Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14/dts-v1/;
15
16/ {
17 model = "manroland,mucmc52";
18 compatible = "manroland,mucmc52";
19 #address-cells = <1>;
20 #size-cells = <1>;
21 interrupt-parent = <&mpc5200_pic>;
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 PowerPC,5200@0 {
28 device_type = "cpu";
29 reg = <0>;
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <0x4000>; // L1, 16K
33 i-cache-size = <0x4000>; // L1, 16K
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
37 };
38 };
39
40 memory {
41 device_type = "memory";
42 reg = <0x00000000 0x04000000>; // 64MB
43 };
44
45 soc5200@f0000000 {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "fsl,mpc5200b-immr";
49 ranges = <0 0xf0000000 0x0000c000>;
50 reg = <0xf0000000 0x00000100>;
51 bus-frequency = <0>; // from bootloader
52 system-frequency = <0>; // from bootloader
53
54 cdm@200 {
55 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
56 reg = <0x200 0x38>;
57 };
58
59 mpc5200_pic: interrupt-controller@500 {
60 // 5200 interrupts are encoded into two levels;
61 interrupt-controller;
62 #interrupt-cells = <3>;
63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
64 reg = <0x500 0x80>;
65 };
66
67 gpt0: timer@600 { // GPT 0 in GPIO mode
68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
69 reg = <0x600 0x10>;
70 interrupts = <1 9 0>;
71 gpio-controller;
72 #gpio-cells = <2>;
73 };
74
75 gpt1: timer@610 { // General Purpose Timer in GPIO mode
76 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
77 reg = <0x610 0x10>;
78 interrupts = <1 10 0>;
79 gpio-controller;
80 #gpio-cells = <2>;
81 };
82
83 gpt2: timer@620 { // General Purpose Timer in GPIO mode
84 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
85 reg = <0x620 0x10>;
86 interrupts = <1 11 0>;
87 gpio-controller;
88 #gpio-cells = <2>;
89 };
90
91 gpt3: timer@630 { // General Purpose Timer in GPIO mode
92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
93 reg = <0x630 0x10>;
94 interrupts = <1 12 0>;
95 gpio-controller;
96 #gpio-cells = <2>;
97 };
98
99 gpio_simple: gpio@b00 {
100 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
101 reg = <0xb00 0x40>;
102 interrupts = <1 7 0>;
103 gpio-controller;
104 #gpio-cells = <2>;
105 };
106
107 gpio_wkup: gpio@c00 {
108 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
109 reg = <0xc00 0x40>;
110 interrupts = <1 8 0 0 3 0>;
111 gpio-controller;
112 #gpio-cells = <2>;
113 };
114
115 dma-controller@1200 {
116 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
117 reg = <0x1200 0x80>;
118 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
119 3 4 0 3 5 0 3 6 0 3 7 0
120 3 8 0 3 9 0 3 10 0 3 11 0
121 3 12 0 3 13 0 3 14 0 3 15 0>;
122 };
123
124 xlb@1f00 {
125 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
126 reg = <0x1f00 0x100>;
127 };
128
129 serial@2000 { /* PSC1 in UART mode */
130 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
131 reg = <0x2000 0x100>;
132 interrupts = <2 1 0>;
133 };
134
135 serial@2200 { /* PSC2 in UART mode */
136 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
137 reg = <0x2200 0x100>;
138 interrupts = <2 2 0>;
139 };
140
141 serial@2c00 { /* PSC6 in UART mode */
142 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
143 reg = <0x2c00 0x100>;
144 interrupts = <2 4 0>;
145 };
146
147 ethernet@3000 {
148 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
149 reg = <0x3000 0x400>;
150 local-mac-address = [ 00 00 00 00 00 00 ];
151 interrupts = <2 5 0>;
152 phy-handle = <&phy0>;
153 };
154
155 mdio@3000 {
156 #address-cells = <1>;
157 #size-cells = <0>;
158 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
159 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
160 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
161
162 phy0: ethernet-phy@0 {
163 compatible = "intel,lxt971";
164 reg = <0>;
165 };
166 };
167
168 ata@3a00 {
169 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
170 reg = <0x3a00 0x100>;
171 interrupts = <2 7 0>;
172 };
173
174 i2c@3d40 {
175 #address-cells = <1>;
176 #size-cells = <0>;
177 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
178 reg = <0x3d40 0x40>;
179 interrupts = <2 16 0>;
180 hwmon@2c {
181 compatible = "ad,adm9240";
182 reg = <0x2c>;
183 };
184 rtc@51 {
185 compatible = "nxp,pcf8563";
186 reg = <0x51>;
187 };
188 };
189
190 sram@8000 {
191 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
192 reg = <0x8000 0x4000>;
193 };
194 };
195
196 pci@f0000d00 {
197 #interrupt-cells = <1>;
198 #size-cells = <2>;
199 #address-cells = <3>;
200 device_type = "pci";
201 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
202 reg = <0xf0000d00 0x100>;
203 interrupt-map-mask = <0xf800 0 0 7>;
204 interrupt-map = <
205 /* IDSEL 0x10 */
206 0x8000 0 0 1 &mpc5200_pic 0 3 3
207 0x8000 0 0 2 &mpc5200_pic 0 3 3
208 0x8000 0 0 3 &mpc5200_pic 0 2 3
209 0x8000 0 0 4 &mpc5200_pic 0 1 3
210 >;
211 clock-frequency = <0>; // From boot loader
212 interrupts = <2 8 0 2 9 0 2 10 0>;
213 bus-range = <0 0>;
214 ranges = <0x42000000 0 0x60000000 0x60000000 0 0x10000000
215 0x02000000 0 0x90000000 0x90000000 0 0x10000000
216 0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
217 };
218
219 localbus {
220 compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
221
222 #address-cells = <2>;
223 #size-cells = <1>;
224
225 ranges = <0 0 0xff800000 0x00800000
226 1 0 0x80000000 0x00800000
227 3 0 0x80000000 0x00800000>;
228
229 flash@0,0 {
230 compatible = "cfi-flash";
231 reg = <0 0 0x00800000>;
232 bank-width = <4>;
233 device-width = <2>;
234 #size-cells = <1>;
235 #address-cells = <1>;
236 partition@0 {
237 label = "DTS";
238 reg = <0x0 0x00100000>;
239 };
240 partition@100000 {
241 label = "Kernel";
242 reg = <0x100000 0x00200000>;
243 };
244 partition@300000 {
245 label = "RootFS";
246 reg = <0x00300000 0x00200000>;
247 };
248 partition@500000 {
249 label = "user";
250 reg = <0x00500000 0x00200000>;
251 };
252 partition@700000 {
253 label = "U-Boot";
254 reg = <0x00700000 0x00040000>;
255 };
256 partition@740000 {
257 label = "Env";
258 reg = <0x00740000 0x00020000>;
259 };
260 partition@760000 {
261 label = "red. Env";
262 reg = <0x00760000 0x00020000>;
263 };
264 partition@780000 {
265 label = "reserve";
266 reg = <0x00780000 0x00080000>;
267 };
268 };
269
270 simple100: gpio-controller-100@3,600100 {
271 compatible = "manroland,mucmc52-aux-gpio";
272 reg = <3 0x00600100 0x1>;
273 gpio-controller;
274 #gpio-cells = <2>;
275 };
276 simple104: gpio-controller-104@3,600104 {
277 compatible = "manroland,mucmc52-aux-gpio";
278 reg = <3 0x00600104 0x1>;
279 gpio-controller;
280 #gpio-cells = <2>;
281 };
282 simple200: gpio-controller-200@3,600200 {
283 compatible = "manroland,mucmc52-aux-gpio";
284 reg = <3 0x00600200 0x1>;
285 gpio-controller;
286 #gpio-cells = <2>;
287 };
288 simple201: gpio-controller-201@3,600201 {
289 compatible = "manroland,mucmc52-aux-gpio";
290 reg = <3 0x00600201 0x1>;
291 gpio-controller;
292 #gpio-cells = <2>;
293 };
294 simple202: gpio-controller-202@3,600202 {
295 compatible = "manroland,mucmc52-aux-gpio";
296 reg = <3 0x00600202 0x1>;
297 gpio-controller;
298 #gpio-cells = <2>;
299 };
300 simple203: gpio-controller-203@3,600203 {
301 compatible = "manroland,mucmc52-aux-gpio";
302 reg = <3 0x00600203 0x1>;
303 gpio-controller;
304 #gpio-cells = <2>;
305 };
306 simple204: gpio-controller-204@3,600204 {
307 compatible = "manroland,mucmc52-aux-gpio";
308 reg = <3 0x00600204 0x1>;
309 gpio-controller;
310 #gpio-cells = <2>;
311 };
312 simple206: gpio-controller-206@3,600206 {
313 compatible = "manroland,mucmc52-aux-gpio";
314 reg = <3 0x00600206 0x1>;
315 gpio-controller;
316 #gpio-cells = <2>;
317 };
318 simple207: gpio-controller-207@3,600207 {
319 compatible = "manroland,mucmc52-aux-gpio";
320 reg = <3 0x00600207 0x1>;
321 gpio-controller;
322 #gpio-cells = <2>;
323 };
324 simple20f: gpio-controller-20f@3,60020f {
325 compatible = "manroland,mucmc52-aux-gpio";
326 reg = <3 0x0060020f 0x1>;
327 gpio-controller;
328 #gpio-cells = <2>;
329 };
330
331 };
332};
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-20 01:47:09 -0400