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Diffstat (limited to 'arch/powerpc/boot/dts/mucmc52.dts')
-rw-r--r--arch/powerpc/boot/dts/mucmc52.dts174
1 files changed, 46 insertions, 128 deletions
diff --git a/arch/powerpc/boot/dts/mucmc52.dts b/arch/powerpc/boot/dts/mucmc52.dts
index 8dc212d9238b..21d34720fcc9 100644
--- a/arch/powerpc/boot/dts/mucmc52.dts
+++ b/arch/powerpc/boot/dts/mucmc52.dts
@@ -11,172 +11,109 @@
11 * option) any later version. 11 * option) any later version.
12 */ 12 */
13 13
14/dts-v1/; 14/include/ "mpc5200b.dtsi"
15 15
16/ { 16/ {
17 model = "manroland,mucmc52"; 17 model = "manroland,mucmc52";
18 compatible = "manroland,mucmc52"; 18 compatible = "manroland,mucmc52";
19 #address-cells = <1>;
20 #size-cells = <1>;
21 interrupt-parent = <&mpc5200_pic>;
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 PowerPC,5200@0 {
28 device_type = "cpu";
29 reg = <0>;
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <0x4000>; // L1, 16K
33 i-cache-size = <0x4000>; // L1, 16K
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
37 };
38 };
39
40 memory {
41 device_type = "memory";
42 reg = <0x00000000 0x04000000>; // 64MB
43 };
44 19
45 soc5200@f0000000 { 20 soc5200@f0000000 {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "fsl,mpc5200b-immr";
49 ranges = <0 0xf0000000 0x0000c000>;
50 reg = <0xf0000000 0x00000100>;
51 bus-frequency = <0>; // from bootloader
52 system-frequency = <0>; // from bootloader
53
54 cdm@200 {
55 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
56 reg = <0x200 0x38>;
57 };
58
59 mpc5200_pic: interrupt-controller@500 {
60 // 5200 interrupts are encoded into two levels;
61 interrupt-controller;
62 #interrupt-cells = <3>;
63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
64 reg = <0x500 0x80>;
65 };
66
67 gpt0: timer@600 { // GPT 0 in GPIO mode 21 gpt0: timer@600 { // GPT 0 in GPIO mode
68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
69 reg = <0x600 0x10>;
70 interrupts = <1 9 0>;
71 gpio-controller; 22 gpio-controller;
72 #gpio-cells = <2>; 23 #gpio-cells = <2>;
73 }; 24 };
74 25
75 gpt1: timer@610 { // General Purpose Timer in GPIO mode 26 gpt1: timer@610 { // General Purpose Timer in GPIO mode
76 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
77 reg = <0x610 0x10>;
78 interrupts = <1 10 0>;
79 gpio-controller; 27 gpio-controller;
80 #gpio-cells = <2>; 28 #gpio-cells = <2>;
81 }; 29 };
82 30
83 gpt2: timer@620 { // General Purpose Timer in GPIO mode 31 gpt2: timer@620 { // General Purpose Timer in GPIO mode
84 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
85 reg = <0x620 0x10>;
86 interrupts = <1 11 0>;
87 gpio-controller; 32 gpio-controller;
88 #gpio-cells = <2>; 33 #gpio-cells = <2>;
89 }; 34 };
90 35
91 gpt3: timer@630 { // General Purpose Timer in GPIO mode 36 gpt3: timer@630 { // General Purpose Timer in GPIO mode
92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
93 reg = <0x630 0x10>;
94 interrupts = <1 12 0>;
95 gpio-controller; 37 gpio-controller;
96 #gpio-cells = <2>; 38 #gpio-cells = <2>;
97 }; 39 };
98 40
99 gpio_simple: gpio@b00 { 41 timer@640 {
100 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 42 status = "disabled";
101 reg = <0xb00 0x40>;
102 interrupts = <1 7 0>;
103 gpio-controller;
104 #gpio-cells = <2>;
105 }; 43 };
106 44
107 gpio_wkup: gpio@c00 { 45 timer@650 {
108 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 46 status = "disabled";
109 reg = <0xc00 0x40>; 47 };
110 interrupts = <1 8 0 0 3 0>; 48
111 gpio-controller; 49 timer@660 {
112 #gpio-cells = <2>; 50 status = "disabled";
51 };
52
53 timer@670 {
54 status = "disabled";
113 }; 55 };
114 56
115 dma-controller@1200 { 57 rtc@800 {
116 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; 58 status = "disabled";
117 reg = <0x1200 0x80>;
118 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
119 3 4 0 3 5 0 3 6 0 3 7 0
120 3 8 0 3 9 0 3 10 0 3 11 0
121 3 12 0 3 13 0 3 14 0 3 15 0>;
122 }; 59 };
123 60
124 xlb@1f00 { 61 can@900 {
125 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; 62 status = "disabled";
126 reg = <0x1f00 0x100>;
127 }; 63 };
128 64
129 psc@2000 { /* PSC1 in UART mode */ 65 can@980 {
66 status = "disabled";
67 };
68
69 spi@f00 {
70 status = "disabled";
71 };
72
73 usb@1000 {
74 status = "disabled";
75 };
76
77 psc@2000 { // PSC1
130 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 78 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
131 reg = <0x2000 0x100>;
132 interrupts = <2 1 0>;
133 }; 79 };
134 80
135 psc@2200 { /* PSC2 in UART mode */ 81 psc@2200 { // PSC2
136 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 82 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
137 reg = <0x2200 0x100>;
138 interrupts = <2 2 0>;
139 }; 83 };
140 84
141 psc@2c00 { /* PSC6 in UART mode */ 85 psc@2400 { // PSC3
86 status = "disabled";
87 };
88
89 psc@2600 { // PSC4
90 status = "disabled";
91 };
92
93 psc@2800 { // PSC5
94 status = "disabled";
95 };
96
97 psc@2c00 { // PSC6
142 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 98 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
143 reg = <0x2c00 0x100>;
144 interrupts = <2 4 0>;
145 }; 99 };
146 100
147 ethernet@3000 { 101 ethernet@3000 {
148 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
149 reg = <0x3000 0x400>;
150 local-mac-address = [ 00 00 00 00 00 00 ];
151 interrupts = <2 5 0>;
152 phy-handle = <&phy0>; 102 phy-handle = <&phy0>;
153 }; 103 };
154 104
155 mdio@3000 { 105 mdio@3000 {
156 #address-cells = <1>;
157 #size-cells = <0>;
158 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
159 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
160 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
161
162 phy0: ethernet-phy@0 { 106 phy0: ethernet-phy@0 {
163 compatible = "intel,lxt971"; 107 compatible = "intel,lxt971";
164 reg = <0>; 108 reg = <0>;
165 }; 109 };
166 }; 110 };
167 111
168 ata@3a00 { 112 i2c@3d00 {
169 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; 113 status = "disabled";
170 reg = <0x3a00 0x100>;
171 interrupts = <2 7 0>;
172 }; 114 };
173 115
174 i2c@3d40 { 116 i2c@3d40 {
175 #address-cells = <1>;
176 #size-cells = <0>;
177 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
178 reg = <0x3d40 0x40>;
179 interrupts = <2 16 0>;
180 hwmon@2c { 117 hwmon@2c {
181 compatible = "ad,adm9240"; 118 compatible = "ad,adm9240";
182 reg = <0x2c>; 119 reg = <0x2c>;
@@ -186,20 +123,9 @@
186 reg = <0x51>; 123 reg = <0x51>;
187 }; 124 };
188 }; 125 };
189
190 sram@8000 {
191 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
192 reg = <0x8000 0x4000>;
193 };
194 }; 126 };
195 127
196 pci@f0000d00 { 128 pci@f0000d00 {
197 #interrupt-cells = <1>;
198 #size-cells = <2>;
199 #address-cells = <3>;
200 device_type = "pci";
201 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
202 reg = <0xf0000d00 0x100>;
203 interrupt-map-mask = <0xf800 0 0 7>; 129 interrupt-map-mask = <0xf800 0 0 7>;
204 interrupt-map = < 130 interrupt-map = <
205 /* IDSEL 0x10 */ 131 /* IDSEL 0x10 */
@@ -208,20 +134,12 @@
208 0x8000 0 0 3 &mpc5200_pic 0 2 3 134 0x8000 0 0 3 &mpc5200_pic 0 2 3
209 0x8000 0 0 4 &mpc5200_pic 0 1 3 135 0x8000 0 0 4 &mpc5200_pic 0 1 3
210 >; 136 >;
211 clock-frequency = <0>; // From boot loader
212 interrupts = <2 8 0 2 9 0 2 10 0>;
213 bus-range = <0 0>;
214 ranges = <0x42000000 0 0x60000000 0x60000000 0 0x10000000 137 ranges = <0x42000000 0 0x60000000 0x60000000 0 0x10000000
215 0x02000000 0 0x90000000 0x90000000 0 0x10000000 138 0x02000000 0 0x90000000 0x90000000 0 0x10000000
216 0x01000000 0 0x00000000 0xa0000000 0 0x01000000>; 139 0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
217 }; 140 };
218 141
219 localbus { 142 localbus {
220 compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
221
222 #address-cells = <2>;
223 #size-cells = <1>;
224
225 ranges = <0 0 0xff800000 0x00800000 143 ranges = <0 0 0xff800000 0x00800000
226 1 0 0x80000000 0x00800000 144 1 0 0x80000000 0x00800000
227 3 0 0x80000000 0x00800000>; 145 3 0 0x80000000 0x00800000>;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-16 05:26:28 -0500