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Diffstat (limited to 'arch/powerpc/boot/dts/mpc8641_hpcn.dts')
-rw-r--r--arch/powerpc/boot/dts/mpc8641_hpcn.dts269
1 files changed, 139 insertions, 130 deletions
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
index 4d53d9bc3a9d..f797662212ba 100644
--- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts
+++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
@@ -53,11 +53,7 @@
53 #address-cells = <1>; 53 #address-cells = <1>;
54 #size-cells = <1>; 54 #size-cells = <1>;
55 device_type = "soc"; 55 device_type = "soc";
56 ranges = <00001000 f8001000 000ff000 56 ranges = <00000000 f8000000 00100000>;
57 80000000 80000000 20000000
58 e2000000 e2000000 00100000
59 a0000000 a0000000 20000000
60 e3000000 e3000000 00100000>;
61 reg = <f8000000 00001000>; // CCSRBAR 57 reg = <f8000000 00001000>; // CCSRBAR
62 bus-frequency = <0>; 58 bus-frequency = <0>;
63 59
@@ -208,50 +204,75 @@
208 interrupt-parent = <&mpic>; 204 interrupt-parent = <&mpic>;
209 }; 205 };
210 206
211 pcie@8000 { 207 mpic: pic@40000 {
212 compatible = "fsl,mpc8641-pcie"; 208 clock-frequency = <0>;
213 device_type = "pci"; 209 interrupt-controller;
214 #interrupt-cells = <1>; 210 #address-cells = <0>;
215 #size-cells = <2>; 211 #interrupt-cells = <2>;
216 #address-cells = <3>; 212 reg = <40000 40000>;
217 reg = <8000 1000>; 213 compatible = "chrp,open-pic";
218 bus-range = <0 ff>; 214 device_type = "open-pic";
219 ranges = <02000000 0 80000000 80000000 0 20000000 215 big-endian;
220 01000000 0 00000000 e2000000 0 00100000>; 216 };
221 clock-frequency = <1fca055>; 217 };
222 interrupt-parent = <&mpic>;
223 interrupts = <18 2>;
224 interrupt-map-mask = <fb00 0 0 0>;
225 interrupt-map = <
226 /* IDSEL 0x11 */
227 8800 0 0 1 &i8259 9 2
228 8800 0 0 2 &i8259 a 2
229 8800 0 0 3 &i8259 b 2
230 8800 0 0 4 &i8259 c 2
231 218
232 /* IDSEL 0x12 */ 219 pcie@f8008000 {
233 9000 0 0 1 &i8259 a 2 220 compatible = "fsl,mpc8641-pcie";
234 9000 0 0 2 &i8259 b 2 221 device_type = "pci";
235 9000 0 0 3 &i8259 c 2 222 #interrupt-cells = <1>;
236 9000 0 0 4 &i8259 9 2 223 #size-cells = <2>;
224 #address-cells = <3>;
225 reg = <f8008000 1000>;
226 bus-range = <0 ff>;
227 ranges = <02000000 0 80000000 80000000 0 20000000
228 01000000 0 00000000 e2000000 0 00100000>;
229 clock-frequency = <1fca055>;
230 interrupt-parent = <&mpic>;
231 interrupts = <18 2>;
232 interrupt-map-mask = <fb00 0 0 0>;
233 interrupt-map = <
234 /* IDSEL 0x11 */
235 8800 0 0 1 &i8259 9 2
236 8800 0 0 2 &i8259 a 2
237 8800 0 0 3 &i8259 b 2
238 8800 0 0 4 &i8259 c 2
237 239
238 // IDSEL 0x1c USB 240 /* IDSEL 0x12 */
239 e000 0 0 0 &i8259 c 2 241 9000 0 0 1 &i8259 a 2
240 e100 0 0 0 &i8259 9 2 242 9000 0 0 2 &i8259 b 2
241 e200 0 0 0 &i8259 a 2 243 9000 0 0 3 &i8259 c 2
242 e300 0 0 0 &i8259 b 2 244 9000 0 0 4 &i8259 9 2
243 245
244 // IDSEL 0x1d Audio 246 // IDSEL 0x1c USB
245 e800 0 0 0 &i8259 6 2 247 e000 0 0 0 &i8259 c 2
248 e100 0 0 0 &i8259 9 2
249 e200 0 0 0 &i8259 a 2
250 e300 0 0 0 &i8259 b 2
246 251
247 // IDSEL 0x1e Legacy 252 // IDSEL 0x1d Audio
248 f000 0 0 0 &i8259 7 2 253 e800 0 0 0 &i8259 6 2
249 f100 0 0 0 &i8259 7 2
250 254
251 // IDSEL 0x1f IDE/SATA 255 // IDSEL 0x1e Legacy
252 f800 0 0 0 &i8259 e 2 256 f000 0 0 0 &i8259 7 2
253 f900 0 0 0 &i8259 5 2 257 f100 0 0 0 &i8259 7 2
254 >; 258
259 // IDSEL 0x1f IDE/SATA
260 f800 0 0 0 &i8259 e 2
261 f900 0 0 0 &i8259 5 2
262 >;
263
264 pcie@0 {
265 reg = <0 0 0 0 0>;
266 #size-cells = <2>;
267 #address-cells = <3>;
268 device_type = "pci";
269 ranges = <02000000 0 80000000
270 02000000 0 80000000
271 0 20000000
272
273 01000000 0 00000000
274 01000000 0 00000000
275 0 00100000>;
255 uli1575@0 { 276 uli1575@0 {
256 reg = <0 0 0 0 0>; 277 reg = <0 0 0 0 0>;
257 #size-cells = <2>; 278 #size-cells = <2>;
@@ -262,108 +283,96 @@
262 01000000 0 00000000 283 01000000 0 00000000
263 01000000 0 00000000 284 01000000 0 00000000
264 0 00100000>; 285 0 00100000>;
286 isa@1e {
287 device_type = "isa";
288 #interrupt-cells = <2>;
289 #size-cells = <1>;
290 #address-cells = <2>;
291 reg = <f000 0 0 0 0>;
292 ranges = <1 0 01000000 0 0
293 00001000>;
294 interrupt-parent = <&i8259>;
265 295
266 pci_bridge@0 { 296 i8259: interrupt-controller@20 {
267 reg = <0 0 0 0 0>; 297 reg = <1 20 2
268 #size-cells = <2>; 298 1 a0 2
269 #address-cells = <3>; 299 1 4d0 2>;
270 ranges = <02000000 0 80000000 300 interrupt-controller;
271 02000000 0 80000000 301 device_type = "interrupt-controller";
272 0 20000000 302 #address-cells = <0>;
273 01000000 0 00000000
274 01000000 0 00000000
275 0 00100000>;
276
277 isa@1e {
278 device_type = "isa";
279 #interrupt-cells = <2>; 303 #interrupt-cells = <2>;
280 #size-cells = <1>; 304 compatible = "chrp,iic";
281 #address-cells = <2>; 305 interrupts = <9 2>;
282 reg = <f000 0 0 0 0>; 306 interrupt-parent = <&mpic>;
283 ranges = <1 0 01000000 0 0 307 };
284 00001000>;
285 interrupt-parent = <&i8259>;
286
287 i8259: interrupt-controller@20 {
288 reg = <1 20 2
289 1 a0 2
290 1 4d0 2>;
291 interrupt-controller;
292 device_type = "interrupt-controller";
293 #address-cells = <0>;
294 #interrupt-cells = <2>;
295 compatible = "chrp,iic";
296 interrupts = <9 2>;
297 interrupt-parent =
298 <&mpic>;
299 };
300
301 i8042@60 {
302 #size-cells = <0>;
303 #address-cells = <1>;
304 reg = <1 60 1 1 64 1>;
305 interrupts = <1 3 c 3>;
306 interrupt-parent =
307 <&i8259>;
308 308
309 keyboard@0 { 309 i8042@60 {
310 reg = <0>; 310 #size-cells = <0>;
311 compatible = "pnpPNP,303"; 311 #address-cells = <1>;
312 }; 312 reg = <1 60 1 1 64 1>;
313 interrupts = <1 3 c 3>;
314 interrupt-parent =
315 <&i8259>;
313 316
314 mouse@1 { 317 keyboard@0 {
315 reg = <1>; 318 reg = <0>;
316 compatible = "pnpPNP,f03"; 319 compatible = "pnpPNP,303";
317 };
318 }; 320 };
319 321
320 rtc@70 { 322 mouse@1 {
321 compatible = 323 reg = <1>;
322 "pnpPNP,b00"; 324 compatible = "pnpPNP,f03";
323 reg = <1 70 2>;
324 }; 325 };
326 };
325 327
326 gpio@400 { 328 rtc@70 {
327 reg = <1 400 80>; 329 compatible =
328 }; 330 "pnpPNP,b00";
331 reg = <1 70 2>;
332 };
333
334 gpio@400 {
335 reg = <1 400 80>;
329 }; 336 };
330 }; 337 };
331 }; 338 };
332
333 }; 339 };
334 340
335 pcie@9000 { 341 };
336 compatible = "fsl,mpc8641-pcie"; 342
337 device_type = "pci"; 343 pcie@f8009000 {
338 #interrupt-cells = <1>; 344 compatible = "fsl,mpc8641-pcie";
345 device_type = "pci";
346 #interrupt-cells = <1>;
347 #size-cells = <2>;
348 #address-cells = <3>;
349 reg = <f8009000 1000>;
350 bus-range = <0 ff>;
351 ranges = <02000000 0 a0000000 a0000000 0 20000000
352 01000000 0 00000000 e3000000 0 00100000>;
353 clock-frequency = <1fca055>;
354 interrupt-parent = <&mpic>;
355 interrupts = <19 2>;
356 interrupt-map-mask = <f800 0 0 7>;
357 interrupt-map = <
358 /* IDSEL 0x0 */
359 0000 0 0 1 &mpic 4 1
360 0000 0 0 2 &mpic 5 1
361 0000 0 0 3 &mpic 6 1
362 0000 0 0 4 &mpic 7 1
363 >;
364 pcie@0 {
365 reg = <0 0 0 0 0>;
339 #size-cells = <2>; 366 #size-cells = <2>;
340 #address-cells = <3>; 367 #address-cells = <3>;
341 reg = <9000 1000>; 368 device_type = "pci";
342 bus-range = <0 ff>; 369 ranges = <02000000 0 a0000000
343 ranges = <02000000 0 a0000000 a0000000 0 20000000 370 02000000 0 a0000000
344 01000000 0 00000000 e3000000 0 00100000>; 371 0 20000000
345 clock-frequency = <1fca055>;
346 interrupt-parent = <&mpic>;
347 interrupts = <19 2>;
348 interrupt-map-mask = <f800 0 0 7>;
349 interrupt-map = <
350 /* IDSEL 0x0 */
351 0000 0 0 1 &mpic 4 1
352 0000 0 0 2 &mpic 5 1
353 0000 0 0 3 &mpic 6 1
354 0000 0 0 4 &mpic 7 1
355 >;
356 };
357 372
358 mpic: pic@40000 { 373 01000000 0 00000000
359 clock-frequency = <0>; 374 01000000 0 00000000
360 interrupt-controller; 375 0 00100000>;
361 #address-cells = <0>;
362 #interrupt-cells = <2>;
363 reg = <40000 40000>;
364 compatible = "chrp,open-pic";
365 device_type = "open-pic";
366 big-endian;
367 }; 376 };
368 }; 377 };
369}; 378};
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-11 03:14:31 -0400