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Diffstat (limited to 'arch/powerpc/boot/dts/mpc8641_hpcn.dts')
-rw-r--r--arch/powerpc/boot/dts/mpc8641_hpcn.dts289
1 files changed, 149 insertions, 140 deletions
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
index b0166e5c177e..367765937a06 100644
--- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts
+++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
@@ -30,7 +30,6 @@
30 timebase-frequency = <0>; // 33 MHz, from uboot 30 timebase-frequency = <0>; // 33 MHz, from uboot
31 bus-frequency = <0>; // From uboot 31 bus-frequency = <0>; // From uboot
32 clock-frequency = <0>; // From uboot 32 clock-frequency = <0>; // From uboot
33 32-bit;
34 }; 33 };
35 PowerPC,8641@1 { 34 PowerPC,8641@1 {
36 device_type = "cpu"; 35 device_type = "cpu";
@@ -42,7 +41,6 @@
42 timebase-frequency = <0>; // 33 MHz, from uboot 41 timebase-frequency = <0>; // 33 MHz, from uboot
43 bus-frequency = <0>; // From uboot 42 bus-frequency = <0>; // From uboot
44 clock-frequency = <0>; // From uboot 43 clock-frequency = <0>; // From uboot
45 32-bit;
46 }; 44 };
47 }; 45 };
48 46
@@ -54,13 +52,8 @@
54 soc8641@f8000000 { 52 soc8641@f8000000 {
55 #address-cells = <1>; 53 #address-cells = <1>;
56 #size-cells = <1>; 54 #size-cells = <1>;
57 #interrupt-cells = <2>;
58 device_type = "soc"; 55 device_type = "soc";
59 ranges = <00001000 f8001000 000ff000 56 ranges = <00000000 f8000000 00100000>;
60 80000000 80000000 20000000
61 e2000000 e2000000 00100000
62 a0000000 a0000000 20000000
63 e3000000 e3000000 00100000>;
64 reg = <f8000000 00001000>; // CCSRBAR 57 reg = <f8000000 00001000>; // CCSRBAR
65 bus-frequency = <0>; 58 bus-frequency = <0>;
66 59
@@ -211,50 +204,81 @@
211 interrupt-parent = <&mpic>; 204 interrupt-parent = <&mpic>;
212 }; 205 };
213 206
214 pcie@8000 { 207 mpic: pic@40000 {
215 compatible = "fsl,mpc8641-pcie"; 208 clock-frequency = <0>;
216 device_type = "pci"; 209 interrupt-controller;
217 #interrupt-cells = <1>; 210 #address-cells = <0>;
211 #interrupt-cells = <2>;
212 reg = <40000 40000>;
213 compatible = "chrp,open-pic";
214 device_type = "open-pic";
215 big-endian;
216 };
217
218 global-utilities@e0000 {
219 compatible = "fsl,mpc8641-guts";
220 reg = <e0000 1000>;
221 fsl,has-rstcr;
222 };
223 };
224
225 pcie@f8008000 {
226 compatible = "fsl,mpc8641-pcie";
227 device_type = "pci";
228 #interrupt-cells = <1>;
229 #size-cells = <2>;
230 #address-cells = <3>;
231 reg = <f8008000 1000>;
232 bus-range = <0 ff>;
233 ranges = <02000000 0 80000000 80000000 0 20000000
234 01000000 0 00000000 e2000000 0 00100000>;
235 clock-frequency = <1fca055>;
236 interrupt-parent = <&mpic>;
237 interrupts = <18 2>;
238 interrupt-map-mask = <fb00 0 0 0>;
239 interrupt-map = <
240 /* IDSEL 0x11 */
241 8800 0 0 1 &i8259 9 2
242 8800 0 0 2 &i8259 a 2
243 8800 0 0 3 &i8259 b 2
244 8800 0 0 4 &i8259 c 2
245
246 /* IDSEL 0x12 */
247 9000 0 0 1 &i8259 a 2
248 9000 0 0 2 &i8259 b 2
249 9000 0 0 3 &i8259 c 2
250 9000 0 0 4 &i8259 9 2
251
252 // IDSEL 0x1c USB
253 e000 0 0 0 &i8259 c 2
254 e100 0 0 0 &i8259 9 2
255 e200 0 0 0 &i8259 a 2
256 e300 0 0 0 &i8259 b 2
257
258 // IDSEL 0x1d Audio
259 e800 0 0 0 &i8259 6 2
260
261 // IDSEL 0x1e Legacy
262 f000 0 0 0 &i8259 7 2
263 f100 0 0 0 &i8259 7 2
264
265 // IDSEL 0x1f IDE/SATA
266 f800 0 0 0 &i8259 e 2
267 f900 0 0 0 &i8259 5 2
268 >;
269
270 pcie@0 {
271 reg = <0 0 0 0 0>;
218 #size-cells = <2>; 272 #size-cells = <2>;
219 #address-cells = <3>; 273 #address-cells = <3>;
220 reg = <8000 1000>; 274 device_type = "pci";
221 bus-range = <0 ff>; 275 ranges = <02000000 0 80000000
222 ranges = <02000000 0 80000000 80000000 0 20000000 276 02000000 0 80000000
223 01000000 0 00000000 e2000000 0 00100000>; 277 0 20000000
224 clock-frequency = <1fca055>; 278
225 interrupt-parent = <&mpic>; 279 01000000 0 00000000
226 interrupts = <18 2>; 280 01000000 0 00000000
227 interrupt-map-mask = <fb00 0 0 0>; 281 0 00100000>;
228 interrupt-map = <
229 /* IDSEL 0x11 */
230 8800 0 0 1 &i8259 9 2
231 8800 0 0 2 &i8259 a 2
232 8800 0 0 3 &i8259 b 2
233 8800 0 0 4 &i8259 c 2
234
235 /* IDSEL 0x12 */
236 9000 0 0 1 &i8259 a 2
237 9000 0 0 2 &i8259 b 2
238 9000 0 0 3 &i8259 c 2
239 9000 0 0 4 &i8259 9 2
240
241 // IDSEL 0x1c USB
242 e000 0 0 0 &i8259 c 2
243 e100 0 0 0 &i8259 9 2
244 e200 0 0 0 &i8259 a 2
245 e300 0 0 0 &i8259 b 2
246
247 // IDSEL 0x1d Audio
248 e800 0 0 0 &i8259 6 2
249
250 // IDSEL 0x1e Legacy
251 f000 0 0 0 &i8259 7 2
252 f100 0 0 0 &i8259 7 2
253
254 // IDSEL 0x1f IDE/SATA
255 f800 0 0 0 &i8259 e 2
256 f900 0 0 0 &i8259 5 2
257 >;
258 uli1575@0 { 282 uli1575@0 {
259 reg = <0 0 0 0 0>; 283 reg = <0 0 0 0 0>;
260 #size-cells = <2>; 284 #size-cells = <2>;
@@ -265,111 +289,96 @@
265 01000000 0 00000000 289 01000000 0 00000000
266 01000000 0 00000000 290 01000000 0 00000000
267 0 00100000>; 291 0 00100000>;
292 isa@1e {
293 device_type = "isa";
294 #interrupt-cells = <2>;
295 #size-cells = <1>;
296 #address-cells = <2>;
297 reg = <f000 0 0 0 0>;
298 ranges = <1 0 01000000 0 0
299 00001000>;
300 interrupt-parent = <&i8259>;
268 301
269 pci_bridge@0 { 302 i8259: interrupt-controller@20 {
270 reg = <0 0 0 0 0>; 303 reg = <1 20 2
271 #size-cells = <2>; 304 1 a0 2
272 #address-cells = <3>; 305 1 4d0 2>;
273 ranges = <02000000 0 80000000 306 interrupt-controller;
274 02000000 0 80000000 307 device_type = "interrupt-controller";
275 0 20000000 308 #address-cells = <0>;
276 01000000 0 00000000
277 01000000 0 00000000
278 0 00100000>;
279
280 isa@1e {
281 device_type = "isa";
282 #interrupt-cells = <2>; 309 #interrupt-cells = <2>;
283 #size-cells = <1>; 310 compatible = "chrp,iic";
284 #address-cells = <2>; 311 interrupts = <9 2>;
285 reg = <f000 0 0 0 0>; 312 interrupt-parent = <&mpic>;
286 ranges = <1 0 01000000 0 0 313 };
287 00001000>;
288 interrupt-parent = <&i8259>;
289
290 i8259: interrupt-controller@20 {
291 reg = <1 20 2
292 1 a0 2
293 1 4d0 2>;
294 clock-frequency = <0>;
295 interrupt-controller;
296 device_type = "interrupt-controller";
297 #address-cells = <0>;
298 #interrupt-cells = <2>;
299 built-in;
300 compatible = "chrp,iic";
301 interrupts = <9 2>;
302 interrupt-parent =
303 <&mpic>;
304 };
305 314
306 i8042@60 { 315 i8042@60 {
307 #size-cells = <0>; 316 #size-cells = <0>;
308 #address-cells = <1>; 317 #address-cells = <1>;
309 reg = <1 60 1 1 64 1>; 318 reg = <1 60 1 1 64 1>;
310 interrupts = <1 3 c 3>; 319 interrupts = <1 3 c 3>;
311 interrupt-parent = 320 interrupt-parent =
312 <&i8259>; 321 <&i8259>;
313
314 keyboard@0 {
315 reg = <0>;
316 compatible = "pnpPNP,303";
317 };
318
319 mouse@1 {
320 reg = <1>;
321 compatible = "pnpPNP,f03";
322 };
323 };
324 322
325 rtc@70 { 323 keyboard@0 {
326 compatible = 324 reg = <0>;
327 "pnpPNP,b00"; 325 compatible = "pnpPNP,303";
328 reg = <1 70 2>;
329 }; 326 };
330 327
331 gpio@400 { 328 mouse@1 {
332 reg = <1 400 80>; 329 reg = <1>;
330 compatible = "pnpPNP,f03";
333 }; 331 };
334 }; 332 };
333
334 rtc@70 {
335 compatible =
336 "pnpPNP,b00";
337 reg = <1 70 2>;
338 };
339
340 gpio@400 {
341 reg = <1 400 80>;
342 };
335 }; 343 };
336 }; 344 };
337
338 }; 345 };
339 346
340 pcie@9000 { 347 };
341 compatible = "fsl,mpc8641-pcie"; 348
342 device_type = "pci"; 349 pcie@f8009000 {
343 #interrupt-cells = <1>; 350 compatible = "fsl,mpc8641-pcie";
351 device_type = "pci";
352 #interrupt-cells = <1>;
353 #size-cells = <2>;
354 #address-cells = <3>;
355 reg = <f8009000 1000>;
356 bus-range = <0 ff>;
357 ranges = <02000000 0 a0000000 a0000000 0 20000000
358 01000000 0 00000000 e3000000 0 00100000>;
359 clock-frequency = <1fca055>;
360 interrupt-parent = <&mpic>;
361 interrupts = <19 2>;
362 interrupt-map-mask = <f800 0 0 7>;
363 interrupt-map = <
364 /* IDSEL 0x0 */
365 0000 0 0 1 &mpic 4 1
366 0000 0 0 2 &mpic 5 1
367 0000 0 0 3 &mpic 6 1
368 0000 0 0 4 &mpic 7 1
369 >;
370 pcie@0 {
371 reg = <0 0 0 0 0>;
344 #size-cells = <2>; 372 #size-cells = <2>;
345 #address-cells = <3>; 373 #address-cells = <3>;
346 reg = <9000 1000>; 374 device_type = "pci";
347 bus-range = <0 ff>; 375 ranges = <02000000 0 a0000000
348 ranges = <02000000 0 a0000000 a0000000 0 20000000 376 02000000 0 a0000000
349 01000000 0 00000000 e3000000 0 00100000>; 377 0 20000000
350 clock-frequency = <1fca055>;
351 interrupt-parent = <&mpic>;
352 interrupts = <19 2>;
353 interrupt-map-mask = <f800 0 0 7>;
354 interrupt-map = <
355 /* IDSEL 0x0 */
356 0000 0 0 1 &mpic 4 1
357 0000 0 0 2 &mpic 5 1
358 0000 0 0 3 &mpic 6 1
359 0000 0 0 4 &mpic 7 1
360 >;
361 };
362 378
363 mpic: pic@40000 { 379 01000000 0 00000000
364 clock-frequency = <0>; 380 01000000 0 00000000
365 interrupt-controller; 381 0 00100000>;
366 #address-cells = <0>;
367 #interrupt-cells = <2>;
368 reg = <40000 40000>;
369 built-in;
370 compatible = "chrp,open-pic";
371 device_type = "open-pic";
372 big-endian;
373 }; 382 };
374 }; 383 };
375}; 384};
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-04 16:15:41 -0500