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-rw-r--r--arch/powerpc/boot/dts/mpc8572ds.dts383
1 files changed, 192 insertions, 191 deletions
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts
index db37214aee37..66f27ab613a2 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8572 DS Device Tree Source 2 * MPC8572 DS Device Tree Source
3 * 3 *
4 * Copyright 2007 Freescale Semiconductor Inc. 4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,6 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
12/ { 13/ {
13 model = "fsl,MPC8572DS"; 14 model = "fsl,MPC8572DS";
14 compatible = "fsl,MPC8572DS"; 15 compatible = "fsl,MPC8572DS";
@@ -33,11 +34,11 @@
33 34
34 PowerPC,8572@0 { 35 PowerPC,8572@0 {
35 device_type = "cpu"; 36 device_type = "cpu";
36 reg = <0>; 37 reg = <0x0>;
37 d-cache-line-size = <20>; // 32 bytes 38 d-cache-line-size = <32>; // 32 bytes
38 i-cache-line-size = <20>; // 32 bytes 39 i-cache-line-size = <32>; // 32 bytes
39 d-cache-size = <8000>; // L1, 32K 40 d-cache-size = <0x8000>; // L1, 32K
40 i-cache-size = <8000>; // L1, 32K 41 i-cache-size = <0x8000>; // L1, 32K
41 timebase-frequency = <0>; 42 timebase-frequency = <0>;
42 bus-frequency = <0>; 43 bus-frequency = <0>;
43 clock-frequency = <0>; 44 clock-frequency = <0>;
@@ -45,11 +46,11 @@
45 46
46 PowerPC,8572@1 { 47 PowerPC,8572@1 {
47 device_type = "cpu"; 48 device_type = "cpu";
48 reg = <1>; 49 reg = <0x1>;
49 d-cache-line-size = <20>; // 32 bytes 50 d-cache-line-size = <32>; // 32 bytes
50 i-cache-line-size = <20>; // 32 bytes 51 i-cache-line-size = <32>; // 32 bytes
51 d-cache-size = <8000>; // L1, 32K 52 d-cache-size = <0x8000>; // L1, 32K
52 i-cache-size = <8000>; // L1, 32K 53 i-cache-size = <0x8000>; // L1, 32K
53 timebase-frequency = <0>; 54 timebase-frequency = <0>;
54 bus-frequency = <0>; 55 bus-frequency = <0>;
55 clock-frequency = <0>; 56 clock-frequency = <0>;
@@ -58,38 +59,38 @@
58 59
59 memory { 60 memory {
60 device_type = "memory"; 61 device_type = "memory";
61 reg = <00000000 00000000>; // Filled by U-Boot 62 reg = <0x0 0x0>; // Filled by U-Boot
62 }; 63 };
63 64
64 soc8572@ffe00000 { 65 soc8572@ffe00000 {
65 #address-cells = <1>; 66 #address-cells = <1>;
66 #size-cells = <1>; 67 #size-cells = <1>;
67 device_type = "soc"; 68 device_type = "soc";
68 ranges = <00000000 ffe00000 00100000>; 69 ranges = <0x0 0xffe00000 0x100000>;
69 reg = <ffe00000 00001000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed 70 reg = <0xffe00000 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
70 bus-frequency = <0>; // Filled out by uboot. 71 bus-frequency = <0>; // Filled out by uboot.
71 72
72 memory-controller@2000 { 73 memory-controller@2000 {
73 compatible = "fsl,mpc8572-memory-controller"; 74 compatible = "fsl,mpc8572-memory-controller";
74 reg = <2000 1000>; 75 reg = <0x2000 0x1000>;
75 interrupt-parent = <&mpic>; 76 interrupt-parent = <&mpic>;
76 interrupts = <12 2>; 77 interrupts = <18 2>;
77 }; 78 };
78 79
79 memory-controller@6000 { 80 memory-controller@6000 {
80 compatible = "fsl,mpc8572-memory-controller"; 81 compatible = "fsl,mpc8572-memory-controller";
81 reg = <6000 1000>; 82 reg = <0x6000 0x1000>;
82 interrupt-parent = <&mpic>; 83 interrupt-parent = <&mpic>;
83 interrupts = <12 2>; 84 interrupts = <18 2>;
84 }; 85 };
85 86
86 l2-cache-controller@20000 { 87 l2-cache-controller@20000 {
87 compatible = "fsl,mpc8572-l2-cache-controller"; 88 compatible = "fsl,mpc8572-l2-cache-controller";
88 reg = <20000 1000>; 89 reg = <0x20000 0x1000>;
89 cache-line-size = <20>; // 32 bytes 90 cache-line-size = <32>; // 32 bytes
90 cache-size = <80000>; // L2, 512K 91 cache-size = <0x80000>; // L2, 512K
91 interrupt-parent = <&mpic>; 92 interrupt-parent = <&mpic>;
92 interrupts = <10 2>; 93 interrupts = <16 2>;
93 }; 94 };
94 95
95 i2c@3000 { 96 i2c@3000 {
@@ -97,8 +98,8 @@
97 #size-cells = <0>; 98 #size-cells = <0>;
98 cell-index = <0>; 99 cell-index = <0>;
99 compatible = "fsl-i2c"; 100 compatible = "fsl-i2c";
100 reg = <3000 100>; 101 reg = <0x3000 0x100>;
101 interrupts = <2b 2>; 102 interrupts = <43 2>;
102 interrupt-parent = <&mpic>; 103 interrupt-parent = <&mpic>;
103 dfsrr; 104 dfsrr;
104 }; 105 };
@@ -108,8 +109,8 @@
108 #size-cells = <0>; 109 #size-cells = <0>;
109 cell-index = <1>; 110 cell-index = <1>;
110 compatible = "fsl-i2c"; 111 compatible = "fsl-i2c";
111 reg = <3100 100>; 112 reg = <0x3100 0x100>;
112 interrupts = <2b 2>; 113 interrupts = <43 2>;
113 interrupt-parent = <&mpic>; 114 interrupt-parent = <&mpic>;
114 dfsrr; 115 dfsrr;
115 }; 116 };
@@ -118,27 +119,27 @@
118 #address-cells = <1>; 119 #address-cells = <1>;
119 #size-cells = <0>; 120 #size-cells = <0>;
120 compatible = "fsl,gianfar-mdio"; 121 compatible = "fsl,gianfar-mdio";
121 reg = <24520 20>; 122 reg = <0x24520 0x20>;
122 123
123 phy0: ethernet-phy@0 { 124 phy0: ethernet-phy@0 {
124 interrupt-parent = <&mpic>; 125 interrupt-parent = <&mpic>;
125 interrupts = <a 1>; 126 interrupts = <10 1>;
126 reg = <0>; 127 reg = <0x0>;
127 }; 128 };
128 phy1: ethernet-phy@1 { 129 phy1: ethernet-phy@1 {
129 interrupt-parent = <&mpic>; 130 interrupt-parent = <&mpic>;
130 interrupts = <a 1>; 131 interrupts = <10 1>;
131 reg = <1>; 132 reg = <0x1>;
132 }; 133 };
133 phy2: ethernet-phy@2 { 134 phy2: ethernet-phy@2 {
134 interrupt-parent = <&mpic>; 135 interrupt-parent = <&mpic>;
135 interrupts = <a 1>; 136 interrupts = <10 1>;
136 reg = <2>; 137 reg = <0x2>;
137 }; 138 };
138 phy3: ethernet-phy@3 { 139 phy3: ethernet-phy@3 {
139 interrupt-parent = <&mpic>; 140 interrupt-parent = <&mpic>;
140 interrupts = <a 1>; 141 interrupts = <10 1>;
141 reg = <3>; 142 reg = <0x3>;
142 }; 143 };
143 }; 144 };
144 145
@@ -147,9 +148,9 @@
147 device_type = "network"; 148 device_type = "network";
148 model = "eTSEC"; 149 model = "eTSEC";
149 compatible = "gianfar"; 150 compatible = "gianfar";
150 reg = <24000 1000>; 151 reg = <0x24000 0x1000>;
151 local-mac-address = [ 00 00 00 00 00 00 ]; 152 local-mac-address = [ 00 00 00 00 00 00 ];
152 interrupts = <1d 2 1e 2 22 2>; 153 interrupts = <29 2 30 2 34 2>;
153 interrupt-parent = <&mpic>; 154 interrupt-parent = <&mpic>;
154 phy-handle = <&phy0>; 155 phy-handle = <&phy0>;
155 phy-connection-type = "rgmii-id"; 156 phy-connection-type = "rgmii-id";
@@ -160,9 +161,9 @@
160 device_type = "network"; 161 device_type = "network";
161 model = "eTSEC"; 162 model = "eTSEC";
162 compatible = "gianfar"; 163 compatible = "gianfar";
163 reg = <25000 1000>; 164 reg = <0x25000 0x1000>;
164 local-mac-address = [ 00 00 00 00 00 00 ]; 165 local-mac-address = [ 00 00 00 00 00 00 ];
165 interrupts = <23 2 24 2 28 2>; 166 interrupts = <35 2 36 2 40 2>;
166 interrupt-parent = <&mpic>; 167 interrupt-parent = <&mpic>;
167 phy-handle = <&phy1>; 168 phy-handle = <&phy1>;
168 phy-connection-type = "rgmii-id"; 169 phy-connection-type = "rgmii-id";
@@ -173,9 +174,9 @@
173 device_type = "network"; 174 device_type = "network";
174 model = "eTSEC"; 175 model = "eTSEC";
175 compatible = "gianfar"; 176 compatible = "gianfar";
176 reg = <26000 1000>; 177 reg = <0x26000 0x1000>;
177 local-mac-address = [ 00 00 00 00 00 00 ]; 178 local-mac-address = [ 00 00 00 00 00 00 ];
178 interrupts = <1f 2 20 2 21 2>; 179 interrupts = <31 2 32 2 33 2>;
179 interrupt-parent = <&mpic>; 180 interrupt-parent = <&mpic>;
180 phy-handle = <&phy2>; 181 phy-handle = <&phy2>;
181 phy-connection-type = "rgmii-id"; 182 phy-connection-type = "rgmii-id";
@@ -186,9 +187,9 @@
186 device_type = "network"; 187 device_type = "network";
187 model = "eTSEC"; 188 model = "eTSEC";
188 compatible = "gianfar"; 189 compatible = "gianfar";
189 reg = <27000 1000>; 190 reg = <0x27000 0x1000>;
190 local-mac-address = [ 00 00 00 00 00 00 ]; 191 local-mac-address = [ 00 00 00 00 00 00 ];
191 interrupts = <25 2 26 2 27 2>; 192 interrupts = <37 2 38 2 39 2>;
192 interrupt-parent = <&mpic>; 193 interrupt-parent = <&mpic>;
193 phy-handle = <&phy3>; 194 phy-handle = <&phy3>;
194 phy-connection-type = "rgmii-id"; 195 phy-connection-type = "rgmii-id";
@@ -198,9 +199,9 @@
198 cell-index = <0>; 199 cell-index = <0>;
199 device_type = "serial"; 200 device_type = "serial";
200 compatible = "ns16550"; 201 compatible = "ns16550";
201 reg = <4500 100>; 202 reg = <0x4500 0x100>;
202 clock-frequency = <0>; 203 clock-frequency = <0>;
203 interrupts = <2a 2>; 204 interrupts = <42 2>;
204 interrupt-parent = <&mpic>; 205 interrupt-parent = <&mpic>;
205 }; 206 };
206 207
@@ -208,15 +209,15 @@
208 cell-index = <1>; 209 cell-index = <1>;
209 device_type = "serial"; 210 device_type = "serial";
210 compatible = "ns16550"; 211 compatible = "ns16550";
211 reg = <4600 100>; 212 reg = <0x4600 0x100>;
212 clock-frequency = <0>; 213 clock-frequency = <0>;
213 interrupts = <2a 2>; 214 interrupts = <42 2>;
214 interrupt-parent = <&mpic>; 215 interrupt-parent = <&mpic>;
215 }; 216 };
216 217
217 global-utilities@e0000 { //global utilities block 218 global-utilities@e0000 { //global utilities block
218 compatible = "fsl,mpc8572-guts"; 219 compatible = "fsl,mpc8572-guts";
219 reg = <e0000 1000>; 220 reg = <0xe0000 0x1000>;
220 fsl,has-rstcr; 221 fsl,has-rstcr;
221 }; 222 };
222 223
@@ -225,7 +226,7 @@
225 interrupt-controller; 226 interrupt-controller;
226 #address-cells = <0>; 227 #address-cells = <0>;
227 #interrupt-cells = <2>; 228 #interrupt-cells = <2>;
228 reg = <40000 40000>; 229 reg = <0x40000 0x40000>;
229 compatible = "chrp,open-pic"; 230 compatible = "chrp,open-pic";
230 device_type = "open-pic"; 231 device_type = "open-pic";
231 big-endian; 232 big-endian;
@@ -239,167 +240,167 @@
239 #interrupt-cells = <1>; 240 #interrupt-cells = <1>;
240 #size-cells = <2>; 241 #size-cells = <2>;
241 #address-cells = <3>; 242 #address-cells = <3>;
242 reg = <ffe08000 1000>; 243 reg = <0xffe08000 0x1000>;
243 bus-range = <0 ff>; 244 bus-range = <0 255>;
244 ranges = <02000000 0 80000000 80000000 0 20000000 245 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
245 01000000 0 00000000 ffc00000 0 00010000>; 246 0x1000000 0x0 0x0 0xffc00000 0x0 0x10000>;
246 clock-frequency = <1fca055>; 247 clock-frequency = <33333333>;
247 interrupt-parent = <&mpic>; 248 interrupt-parent = <&mpic>;
248 interrupts = <18 2>; 249 interrupts = <24 2>;
249 interrupt-map-mask = <ff00 0 0 7>; 250 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
250 interrupt-map = < 251 interrupt-map = <
251 /* IDSEL 0x11 func 0 - PCI slot 1 */ 252 /* IDSEL 0x11 func 0 - PCI slot 1 */
252 8800 0 0 1 &mpic 2 1 253 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
253 8800 0 0 2 &mpic 3 1 254 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
254 8800 0 0 3 &mpic 4 1 255 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
255 8800 0 0 4 &mpic 1 1 256 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
256 257
257 /* IDSEL 0x11 func 1 - PCI slot 1 */ 258 /* IDSEL 0x11 func 1 - PCI slot 1 */
258 8900 0 0 1 &mpic 2 1 259 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
259 8900 0 0 2 &mpic 3 1 260 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
260 8900 0 0 3 &mpic 4 1 261 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
261 8900 0 0 4 &mpic 1 1 262 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
262 263
263 /* IDSEL 0x11 func 2 - PCI slot 1 */ 264 /* IDSEL 0x11 func 2 - PCI slot 1 */
264 8a00 0 0 1 &mpic 2 1 265 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
265 8a00 0 0 2 &mpic 3 1 266 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
266 8a00 0 0 3 &mpic 4 1 267 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
267 8a00 0 0 4 &mpic 1 1 268 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
268 269
269 /* IDSEL 0x11 func 3 - PCI slot 1 */ 270 /* IDSEL 0x11 func 3 - PCI slot 1 */
270 8b00 0 0 1 &mpic 2 1 271 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
271 8b00 0 0 2 &mpic 3 1 272 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
272 8b00 0 0 3 &mpic 4 1 273 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
273 8b00 0 0 4 &mpic 1 1 274 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
274 275
275 /* IDSEL 0x11 func 4 - PCI slot 1 */ 276 /* IDSEL 0x11 func 4 - PCI slot 1 */
276 8c00 0 0 1 &mpic 2 1 277 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
277 8c00 0 0 2 &mpic 3 1 278 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
278 8c00 0 0 3 &mpic 4 1 279 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
279 8c00 0 0 4 &mpic 1 1 280 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
280 281
281 /* IDSEL 0x11 func 5 - PCI slot 1 */ 282 /* IDSEL 0x11 func 5 - PCI slot 1 */
282 8d00 0 0 1 &mpic 2 1 283 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
283 8d00 0 0 2 &mpic 3 1 284 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
284 8d00 0 0 3 &mpic 4 1 285 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
285 8d00 0 0 4 &mpic 1 1 286 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
286 287
287 /* IDSEL 0x11 func 6 - PCI slot 1 */ 288 /* IDSEL 0x11 func 6 - PCI slot 1 */
288 8e00 0 0 1 &mpic 2 1 289 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
289 8e00 0 0 2 &mpic 3 1 290 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
290 8e00 0 0 3 &mpic 4 1 291 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
291 8e00 0 0 4 &mpic 1 1 292 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
292 293
293 /* IDSEL 0x11 func 7 - PCI slot 1 */ 294 /* IDSEL 0x11 func 7 - PCI slot 1 */
294 8f00 0 0 1 &mpic 2 1 295 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
295 8f00 0 0 2 &mpic 3 1 296 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
296 8f00 0 0 3 &mpic 4 1 297 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
297 8f00 0 0 4 &mpic 1 1 298 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
298 299
299 /* IDSEL 0x12 func 0 - PCI slot 2 */ 300 /* IDSEL 0x12 func 0 - PCI slot 2 */
300 9000 0 0 1 &mpic 3 1 301 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
301 9000 0 0 2 &mpic 4 1 302 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
302 9000 0 0 3 &mpic 1 1 303 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
303 9000 0 0 4 &mpic 2 1 304 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
304 305
305 /* IDSEL 0x12 func 1 - PCI slot 2 */ 306 /* IDSEL 0x12 func 1 - PCI slot 2 */
306 9100 0 0 1 &mpic 3 1 307 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
307 9100 0 0 2 &mpic 4 1 308 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
308 9100 0 0 3 &mpic 1 1 309 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
309 9100 0 0 4 &mpic 2 1 310 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
310 311
311 /* IDSEL 0x12 func 2 - PCI slot 2 */ 312 /* IDSEL 0x12 func 2 - PCI slot 2 */
312 9200 0 0 1 &mpic 3 1 313 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
313 9200 0 0 2 &mpic 4 1 314 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
314 9200 0 0 3 &mpic 1 1 315 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
315 9200 0 0 4 &mpic 2 1 316 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
316 317
317 /* IDSEL 0x12 func 3 - PCI slot 2 */ 318 /* IDSEL 0x12 func 3 - PCI slot 2 */
318 9300 0 0 1 &mpic 3 1 319 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
319 9300 0 0 2 &mpic 4 1 320 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
320 9300 0 0 3 &mpic 1 1 321 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
321 9300 0 0 4 &mpic 2 1 322 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
322 323
323 /* IDSEL 0x12 func 4 - PCI slot 2 */ 324 /* IDSEL 0x12 func 4 - PCI slot 2 */
324 9400 0 0 1 &mpic 3 1 325 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
325 9400 0 0 2 &mpic 4 1 326 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
326 9400 0 0 3 &mpic 1 1 327 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
327 9400 0 0 4 &mpic 2 1 328 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
328 329
329 /* IDSEL 0x12 func 5 - PCI slot 2 */ 330 /* IDSEL 0x12 func 5 - PCI slot 2 */
330 9500 0 0 1 &mpic 3 1 331 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
331 9500 0 0 2 &mpic 4 1 332 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
332 9500 0 0 3 &mpic 1 1 333 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
333 9500 0 0 4 &mpic 2 1 334 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
334 335
335 /* IDSEL 0x12 func 6 - PCI slot 2 */ 336 /* IDSEL 0x12 func 6 - PCI slot 2 */
336 9600 0 0 1 &mpic 3 1 337 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
337 9600 0 0 2 &mpic 4 1 338 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
338 9600 0 0 3 &mpic 1 1 339 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
339 9600 0 0 4 &mpic 2 1 340 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
340 341
341 /* IDSEL 0x12 func 7 - PCI slot 2 */ 342 /* IDSEL 0x12 func 7 - PCI slot 2 */
342 9700 0 0 1 &mpic 3 1 343 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
343 9700 0 0 2 &mpic 4 1 344 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
344 9700 0 0 3 &mpic 1 1 345 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
345 9700 0 0 4 &mpic 2 1 346 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
346 347
347 // IDSEL 0x1c USB 348 // IDSEL 0x1c USB
348 e000 0 0 1 &i8259 c 2 349 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
349 e100 0 0 2 &i8259 9 2 350 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
350 e200 0 0 3 &i8259 a 2 351 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
351 e300 0 0 4 &i8259 b 2 352 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
352 353
353 // IDSEL 0x1d Audio 354 // IDSEL 0x1d Audio
354 e800 0 0 1 &i8259 6 2 355 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
355 356
356 // IDSEL 0x1e Legacy 357 // IDSEL 0x1e Legacy
357 f000 0 0 1 &i8259 7 2 358 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
358 f100 0 0 1 &i8259 7 2 359 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
359 360
360 // IDSEL 0x1f IDE/SATA 361 // IDSEL 0x1f IDE/SATA
361 f800 0 0 1 &i8259 e 2 362 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
362 f900 0 0 1 &i8259 5 2 363 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
363 364
364 >; 365 >;
365 366
366 pcie@0 { 367 pcie@0 {
367 reg = <0 0 0 0 0>; 368 reg = <0x0 0x0 0x0 0x0 0x0>;
368 #size-cells = <2>; 369 #size-cells = <2>;
369 #address-cells = <3>; 370 #address-cells = <3>;
370 device_type = "pci"; 371 device_type = "pci";
371 ranges = <02000000 0 80000000 372 ranges = <0x2000000 0x0 0x80000000
372 02000000 0 80000000 373 0x2000000 0x0 0x80000000
373 0 20000000 374 0x0 0x20000000
374 375
375 01000000 0 00000000 376 0x1000000 0x0 0x0
376 01000000 0 00000000 377 0x1000000 0x0 0x0
377 0 00100000>; 378 0x0 0x100000>;
378 uli1575@0 { 379 uli1575@0 {
379 reg = <0 0 0 0 0>; 380 reg = <0x0 0x0 0x0 0x0 0x0>;
380 #size-cells = <2>; 381 #size-cells = <2>;
381 #address-cells = <3>; 382 #address-cells = <3>;
382 ranges = <02000000 0 80000000 383 ranges = <0x2000000 0x0 0x80000000
383 02000000 0 80000000 384 0x2000000 0x0 0x80000000
384 0 20000000 385 0x0 0x20000000
385 386
386 01000000 0 00000000 387 0x1000000 0x0 0x0
387 01000000 0 00000000 388 0x1000000 0x0 0x0
388 0 00100000>; 389 0x0 0x100000>;
389 isa@1e { 390 isa@1e {
390 device_type = "isa"; 391 device_type = "isa";
391 #interrupt-cells = <2>; 392 #interrupt-cells = <2>;
392 #size-cells = <1>; 393 #size-cells = <1>;
393 #address-cells = <2>; 394 #address-cells = <2>;
394 reg = <f000 0 0 0 0>; 395 reg = <0xf000 0x0 0x0 0x0 0x0>;
395 ranges = <1 0 01000000 0 0 396 ranges = <0x1 0x0 0x1000000 0x0 0x0
396 00001000>; 397 0x1000>;
397 interrupt-parent = <&i8259>; 398 interrupt-parent = <&i8259>;
398 399
399 i8259: interrupt-controller@20 { 400 i8259: interrupt-controller@20 {
400 reg = <1 20 2 401 reg = <0x1 0x20 0x2
401 1 a0 2 402 0x1 0xa0 0x2
402 1 4d0 2>; 403 0x1 0x4d0 0x2>;
403 interrupt-controller; 404 interrupt-controller;
404 device_type = "interrupt-controller"; 405 device_type = "interrupt-controller";
405 #address-cells = <0>; 406 #address-cells = <0>;
@@ -412,29 +413,29 @@
412 i8042@60 { 413 i8042@60 {
413 #size-cells = <0>; 414 #size-cells = <0>;
414 #address-cells = <1>; 415 #address-cells = <1>;
415 reg = <1 60 1 1 64 1>; 416 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
416 interrupts = <1 3 c 3>; 417 interrupts = <1 3 12 3>;
417 interrupt-parent = 418 interrupt-parent =
418 <&i8259>; 419 <&i8259>;
419 420
420 keyboard@0 { 421 keyboard@0 {
421 reg = <0>; 422 reg = <0x0>;
422 compatible = "pnpPNP,303"; 423 compatible = "pnpPNP,303";
423 }; 424 };
424 425
425 mouse@1 { 426 mouse@1 {
426 reg = <1>; 427 reg = <0x1>;
427 compatible = "pnpPNP,f03"; 428 compatible = "pnpPNP,f03";
428 }; 429 };
429 }; 430 };
430 431
431 rtc@70 { 432 rtc@70 {
432 compatible = "pnpPNP,b00"; 433 compatible = "pnpPNP,b00";
433 reg = <1 70 2>; 434 reg = <0x1 0x70 0x2>;
434 }; 435 };
435 436
436 gpio@400 { 437 gpio@400 {
437 reg = <1 400 80>; 438 reg = <0x1 0x400 0x80>;
438 }; 439 };
439 }; 440 };
440 }; 441 };
@@ -449,33 +450,33 @@
449 #interrupt-cells = <1>; 450 #interrupt-cells = <1>;
450 #size-cells = <2>; 451 #size-cells = <2>;
451 #address-cells = <3>; 452 #address-cells = <3>;
452 reg = <ffe09000 1000>; 453 reg = <0xffe09000 0x1000>;
453 bus-range = <0 ff>; 454 bus-range = <0 255>;
454 ranges = <02000000 0 a0000000 a0000000 0 20000000 455 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
455 01000000 0 00000000 ffc10000 0 00010000>; 456 0x1000000 0x0 0x0 0xffc10000 0x0 0x10000>;
456 clock-frequency = <1fca055>; 457 clock-frequency = <33333333>;
457 interrupt-parent = <&mpic>; 458 interrupt-parent = <&mpic>;
458 interrupts = <1a 2>; 459 interrupts = <26 2>;
459 interrupt-map-mask = <f800 0 0 7>; 460 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
460 interrupt-map = < 461 interrupt-map = <
461 /* IDSEL 0x0 */ 462 /* IDSEL 0x0 */
462 0000 0 0 1 &mpic 4 1 463 0000 0x0 0x0 0x1 &mpic 0x4 0x1
463 0000 0 0 2 &mpic 5 1 464 0000 0x0 0x0 0x2 &mpic 0x5 0x1
464 0000 0 0 3 &mpic 6 1 465 0000 0x0 0x0 0x3 &mpic 0x6 0x1
465 0000 0 0 4 &mpic 7 1 466 0000 0x0 0x0 0x4 &mpic 0x7 0x1
466 >; 467 >;
467 pcie@0 { 468 pcie@0 {
468 reg = <0 0 0 0 0>; 469 reg = <0x0 0x0 0x0 0x0 0x0>;
469 #size-cells = <2>; 470 #size-cells = <2>;
470 #address-cells = <3>; 471 #address-cells = <3>;
471 device_type = "pci"; 472 device_type = "pci";
472 ranges = <02000000 0 a0000000 473 ranges = <0x2000000 0x0 0xa0000000
473 02000000 0 a0000000 474 0x2000000 0x0 0xa0000000
474 0 20000000 475 0x0 0x20000000
475 476
476 01000000 0 00000000 477 0x1000000 0x0 0x0
477 01000000 0 00000000 478 0x1000000 0x0 0x0
478 0 00100000>; 479 0x0 0x100000>;
479 }; 480 };
480 }; 481 };
481 482
@@ -486,33 +487,33 @@
486 #interrupt-cells = <1>; 487 #interrupt-cells = <1>;
487 #size-cells = <2>; 488 #size-cells = <2>;
488 #address-cells = <3>; 489 #address-cells = <3>;
489 reg = <ffe0a000 1000>; 490 reg = <0xffe0a000 0x1000>;
490 bus-range = <0 ff>; 491 bus-range = <0 255>;
491 ranges = <02000000 0 c0000000 c0000000 0 20000000 492 ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
492 01000000 0 00000000 ffc20000 0 00010000>; 493 0x1000000 0x0 0x0 0xffc20000 0x0 0x10000>;
493 clock-frequency = <1fca055>; 494 clock-frequency = <33333333>;
494 interrupt-parent = <&mpic>; 495 interrupt-parent = <&mpic>;
495 interrupts = <1b 2>; 496 interrupts = <27 2>;
496 interrupt-map-mask = <f800 0 0 7>; 497 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
497 interrupt-map = < 498 interrupt-map = <
498 /* IDSEL 0x0 */ 499 /* IDSEL 0x0 */
499 0000 0 0 1 &mpic 0 1 500 0000 0x0 0x0 0x1 &mpic 0x0 0x1
500 0000 0 0 2 &mpic 1 1 501 0000 0x0 0x0 0x2 &mpic 0x1 0x1
501 0000 0 0 3 &mpic 2 1 502 0000 0x0 0x0 0x3 &mpic 0x2 0x1
502 0000 0 0 4 &mpic 3 1 503 0000 0x0 0x0 0x4 &mpic 0x3 0x1
503 >; 504 >;
504 pcie@0 { 505 pcie@0 {
505 reg = <0 0 0 0 0>; 506 reg = <0x0 0x0 0x0 0x0 0x0>;
506 #size-cells = <2>; 507 #size-cells = <2>;
507 #address-cells = <3>; 508 #address-cells = <3>;
508 device_type = "pci"; 509 device_type = "pci";
509 ranges = <02000000 0 c0000000 510 ranges = <0x2000000 0x0 0xc0000000
510 02000000 0 c0000000 511 0x2000000 0x0 0xc0000000
511 0 20000000 512 0x0 0x20000000
512 513
513 01000000 0 00000000 514 0x1000000 0x0 0x0
514 01000000 0 00000000 515 0x1000000 0x0 0x0
515 0 00100000>; 516 0x0 0x100000>;
516 }; 517 };
517 }; 518 };
518}; 519};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-24 23:14:08 -0500