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diff --git a/arch/powerpc/boot/dts/mpc8569mds.dts b/arch/powerpc/boot/dts/mpc8569mds.dts
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+++ b/arch/powerpc/boot/dts/mpc8569mds.dts
@@ -0,0 +1,668 @@
1/*
2 * MPC8569E MDS Device Tree Source
3 *
4 * Copyright (C) 2009 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 model = "MPC8569EMDS";
16 compatible = "fsl,MPC8569EMDS";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 serial0 = &serial0;
22 serial1 = &serial1;
23 ethernet0 = &enet0;
24 ethernet1 = &enet1;
25 ethernet2 = &enet2;
26 ethernet3 = &enet3;
27 ethernet5 = &enet5;
28 ethernet7 = &enet7;
29 pci1 = &pci1;
30 rapidio0 = &rio0;
31 };
32
33 cpus {
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 PowerPC,8569@0 {
38 device_type = "cpu";
39 reg = <0x0>;
40 d-cache-line-size = <32>; // 32 bytes
41 i-cache-line-size = <32>; // 32 bytes
42 d-cache-size = <0x8000>; // L1, 32K
43 i-cache-size = <0x8000>; // L1, 32K
44 timebase-frequency = <0>;
45 bus-frequency = <0>;
46 clock-frequency = <0>;
47 next-level-cache = <&L2>;
48 };
49 };
50
51 memory {
52 device_type = "memory";
53 };
54
55 localbus@e0005000 {
56 #address-cells = <2>;
57 #size-cells = <1>;
58 compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus";
59 reg = <0xe0005000 0x1000>;
60 interrupts = <19 2>;
61 interrupt-parent = <&mpic>;
62
63 ranges = <0x0 0x0 0xfe000000 0x02000000
64 0x1 0x0 0xf8000000 0x00008000
65 0x2 0x0 0xf0000000 0x04000000
66 0x3 0x0 0xfc000000 0x00008000
67 0x4 0x0 0xf8008000 0x00008000
68 0x5 0x0 0xf8010000 0x00008000>;
69
70 nor@0,0 {
71 #address-cells = <1>;
72 #size-cells = <1>;
73 compatible = "cfi-flash";
74 reg = <0x0 0x0 0x02000000>;
75 bank-width = <1>;
76 device-width = <1>;
77 partition@0 {
78 label = "ramdisk";
79 reg = <0x00000000 0x01c00000>;
80 };
81 partition@1c00000 {
82 label = "kernel";
83 reg = <0x01c00000 0x002e0000>;
84 };
85 partiton@1ee0000 {
86 label = "dtb";
87 reg = <0x01ee0000 0x00020000>;
88 };
89 partition@1f00000 {
90 label = "firmware";
91 reg = <0x01f00000 0x00080000>;
92 read-only;
93 };
94 partition@1f80000 {
95 label = "u-boot";
96 reg = <0x01f80000 0x00080000>;
97 read-only;
98 };
99 };
100
101 bcsr@1,0 {
102 compatible = "fsl,mpc8569mds-bcsr";
103 reg = <1 0 0x8000>;
104 };
105
106 nand@3,0 {
107 compatible = "fsl,mpc8569-fcm-nand",
108 "fsl,elbc-fcm-nand";
109 reg = <3 0 0x8000>;
110 };
111
112 pib@4,0 {
113 compatible = "fsl,mpc8569mds-pib";
114 reg = <4 0 0x8000>;
115 };
116
117 pib@5,0 {
118 compatible = "fsl,mpc8569mds-pib";
119 reg = <5 0 0x8000>;
120 };
121 };
122
123 soc@e0000000 {
124 #address-cells = <1>;
125 #size-cells = <1>;
126 device_type = "soc";
127 compatible = "fsl,mpc8569-immr", "simple-bus";
128 ranges = <0x0 0xe0000000 0x100000>;
129 bus-frequency = <0>;
130
131 ecm-law@0 {
132 compatible = "fsl,ecm-law";
133 reg = <0x0 0x1000>;
134 fsl,num-laws = <10>;
135 };
136
137 ecm@1000 {
138 compatible = "fsl,mpc8569-ecm", "fsl,ecm";
139 reg = <0x1000 0x1000>;
140 interrupts = <17 2>;
141 interrupt-parent = <&mpic>;
142 };
143
144 memory-controller@2000 {
145 compatible = "fsl,mpc8569-memory-controller";
146 reg = <0x2000 0x1000>;
147 interrupt-parent = <&mpic>;
148 interrupts = <18 2>;
149 };
150
151 i2c@3000 {
152 #address-cells = <1>;
153 #size-cells = <0>;
154 cell-index = <0>;
155 compatible = "fsl-i2c";
156 reg = <0x3000 0x100>;
157 interrupts = <43 2>;
158 interrupt-parent = <&mpic>;
159 dfsrr;
160
161 rtc@68 {
162 compatible = "dallas,ds1374";
163 reg = <0x68>;
164 };
165 };
166
167 i2c@3100 {
168 #address-cells = <1>;
169 #size-cells = <0>;
170 cell-index = <1>;
171 compatible = "fsl-i2c";
172 reg = <0x3100 0x100>;
173 interrupts = <43 2>;
174 interrupt-parent = <&mpic>;
175 dfsrr;
176 };
177
178 serial0: serial@4500 {
179 cell-index = <0>;
180 device_type = "serial";
181 compatible = "ns16550";
182 reg = <0x4500 0x100>;
183 clock-frequency = <0>;
184 interrupts = <42 2>;
185 interrupt-parent = <&mpic>;
186 };
187
188 serial1: serial@4600 {
189 cell-index = <1>;
190 device_type = "serial";
191 compatible = "ns16550";
192 reg = <0x4600 0x100>;
193 clock-frequency = <0>;
194 interrupts = <42 2>;
195 interrupt-parent = <&mpic>;
196 };
197
198 L2: l2-cache-controller@20000 {
199 compatible = "fsl,mpc8569-l2-cache-controller";
200 reg = <0x20000 0x1000>;
201 cache-line-size = <32>; // 32 bytes
202 cache-size = <0x80000>; // L2, 512K
203 interrupt-parent = <&mpic>;
204 interrupts = <16 2>;
205 };
206
207 dma@21300 {
208 #address-cells = <1>;
209 #size-cells = <1>;
210 compatible = "fsl,mpc8569-dma", "fsl,eloplus-dma";
211 reg = <0x21300 0x4>;
212 ranges = <0x0 0x21100 0x200>;
213 cell-index = <0>;
214 dma-channel@0 {
215 compatible = "fsl,mpc8569-dma-channel",
216 "fsl,eloplus-dma-channel";
217 reg = <0x0 0x80>;
218 cell-index = <0>;
219 interrupt-parent = <&mpic>;
220 interrupts = <20 2>;
221 };
222 dma-channel@80 {
223 compatible = "fsl,mpc8569-dma-channel",
224 "fsl,eloplus-dma-channel";
225 reg = <0x80 0x80>;
226 cell-index = <1>;
227 interrupt-parent = <&mpic>;
228 interrupts = <21 2>;
229 };
230 dma-channel@100 {
231 compatible = "fsl,mpc8569-dma-channel",
232 "fsl,eloplus-dma-channel";
233 reg = <0x100 0x80>;
234 cell-index = <2>;
235 interrupt-parent = <&mpic>;
236 interrupts = <22 2>;
237 };
238 dma-channel@180 {
239 compatible = "fsl,mpc8569-dma-channel",
240 "fsl,eloplus-dma-channel";
241 reg = <0x180 0x80>;
242 cell-index = <3>;
243 interrupt-parent = <&mpic>;
244 interrupts = <23 2>;
245 };
246 };
247
248 sdhci@2e000 {
249 compatible = "fsl,mpc8569-esdhc", "fsl,esdhc";
250 reg = <0x2e000 0x1000>;
251 interrupts = <72 0x8>;
252 interrupt-parent = <&mpic>;
253 /* Filled in by U-Boot */
254 clock-frequency = <0>;
255 status = "disabled";
256 };
257
258 crypto@30000 {
259 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
260 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
261 reg = <0x30000 0x10000>;
262 interrupts = <45 2 58 2>;
263 interrupt-parent = <&mpic>;
264 fsl,num-channels = <4>;
265 fsl,channel-fifo-len = <24>;
266 fsl,exec-units-mask = <0xbfe>;
267 fsl,descriptor-types-mask = <0x3ab0ebf>;
268 };
269
270 mpic: pic@40000 {
271 interrupt-controller;
272 #address-cells = <0>;
273 #interrupt-cells = <2>;
274 reg = <0x40000 0x40000>;
275 compatible = "chrp,open-pic";
276 device_type = "open-pic";
277 };
278
279 msi@41600 {
280 compatible = "fsl,mpc8568-msi", "fsl,mpic-msi";
281 reg = <0x41600 0x80>;
282 msi-available-ranges = <0 0x100>;
283 interrupts = <
284 0xe0 0
285 0xe1 0
286 0xe2 0
287 0xe3 0
288 0xe4 0
289 0xe5 0
290 0xe6 0
291 0xe7 0>;
292 interrupt-parent = <&mpic>;
293 };
294
295 global-utilities@e0000 {
296 compatible = "fsl,mpc8569-guts";
297 reg = <0xe0000 0x1000>;
298 fsl,has-rstcr;
299 };
300
301 par_io@e0100 {
302 #address-cells = <1>;
303 #size-cells = <1>;
304 reg = <0xe0100 0x100>;
305 ranges = <0x0 0xe0100 0x100>;
306 device_type = "par_io";
307 num-ports = <7>;
308
309 qe_pio_e: gpio-controller@80 {
310 #gpio-cells = <2>;
311 compatible = "fsl,mpc8569-qe-pario-bank",
312 "fsl,mpc8323-qe-pario-bank";
313 reg = <0x80 0x18>;
314 gpio-controller;
315 };
316
317 pio1: ucc_pin@01 {
318 pio-map = <
319 /* port pin dir open_drain assignment has_irq */
320 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
321 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
322 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/
323 0x0 0x0 0x1 0x0 0x3 0x0 /* ENET1_TXD0_SER1_TXD0 */
324 0x0 0x1 0x1 0x0 0x3 0x0 /* ENET1_TXD1_SER1_TXD1 */
325 0x0 0x2 0x1 0x0 0x1 0x0 /* ENET1_TXD2_SER1_TXD2 */
326 0x0 0x3 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
327 0x0 0x6 0x2 0x0 0x3 0x0 /* ENET1_RXD0_SER1_RXD0 */
328 0x0 0x7 0x2 0x0 0x1 0x0 /* ENET1_RXD1_SER1_RXD1 */
329 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
330 0x0 0x9 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
331 0x0 0x4 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
332 0x0 0xc 0x2 0x0 0x3 0x0 /* ENET1_RX_DV_SER1_CTS_B */
333 0x2 0x8 0x2 0x0 0x1 0x0 /* ENET1_GRXCLK */
334 0x2 0x14 0x1 0x0 0x2 0x0>; /* ENET1_GTXCLK */
335 };
336
337 pio2: ucc_pin@02 {
338 pio-map = <
339 /* port pin dir open_drain assignment has_irq */
340 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
341 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
342 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */
343 0x0 0xe 0x1 0x0 0x2 0x0 /* ENET2_TXD0_SER2_TXD0 */
344 0x0 0xf 0x1 0x0 0x2 0x0 /* ENET2_TXD1_SER2_TXD1 */
345 0x0 0x10 0x1 0x0 0x1 0x0 /* ENET2_TXD2_SER2_TXD2 */
346 0x0 0x11 0x1 0x0 0x1 0x0 /* ENET2_TXD3_SER2_TXD3 */
347 0x0 0x14 0x2 0x0 0x2 0x0 /* ENET2_RXD0_SER2_RXD0 */
348 0x0 0x15 0x2 0x0 0x1 0x0 /* ENET2_RXD1_SER2_RXD1 */
349 0x0 0x16 0x2 0x0 0x1 0x0 /* ENET2_RXD2_SER2_RXD2 */
350 0x0 0x17 0x2 0x0 0x1 0x0 /* ENET2_RXD3_SER2_RXD3 */
351 0x0 0x12 0x1 0x0 0x2 0x0 /* ENET2_TX_EN_SER2_RTS_B */
352 0x0 0x1a 0x2 0x0 0x3 0x0 /* ENET2_RX_DV_SER2_CTS_B */
353 0x2 0x3 0x2 0x0 0x1 0x0 /* ENET2_GRXCLK */
354 0x2 0x2 0x1 0x0 0x2 0x0>; /* ENET2_GTXCLK */
355 };
356
357 pio3: ucc_pin@03 {
358 pio-map = <
359 /* port pin dir open_drain assignment has_irq */
360 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
361 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
362 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/
363 0x0 0x1d 0x1 0x0 0x2 0x0 /* ENET3_TXD0_SER3_TXD0 */
364 0x0 0x1e 0x1 0x0 0x3 0x0 /* ENET3_TXD1_SER3_TXD1 */
365 0x0 0x1f 0x1 0x0 0x2 0x0 /* ENET3_TXD2_SER3_TXD2 */
366 0x1 0x0 0x1 0x0 0x3 0x0 /* ENET3_TXD3_SER3_TXD3 */
367 0x1 0x3 0x2 0x0 0x3 0x0 /* ENET3_RXD0_SER3_RXD0 */
368 0x1 0x4 0x2 0x0 0x1 0x0 /* ENET3_RXD1_SER3_RXD1 */
369 0x1 0x5 0x2 0x0 0x2 0x0 /* ENET3_RXD2_SER3_RXD2 */
370 0x1 0x6 0x2 0x0 0x3 0x0 /* ENET3_RXD3_SER3_RXD3 */
371 0x1 0x1 0x1 0x0 0x1 0x0 /* ENET3_TX_EN_SER3_RTS_B */
372 0x1 0x9 0x2 0x0 0x3 0x0 /* ENET3_RX_DV_SER3_CTS_B */
373 0x2 0x9 0x2 0x0 0x2 0x0 /* ENET3_GRXCLK */
374 0x2 0x19 0x1 0x0 0x2 0x0>; /* ENET3_GTXCLK */
375 };
376
377 pio4: ucc_pin@04 {
378 pio-map = <
379 /* port pin dir open_drain assignment has_irq */
380 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
381 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
382 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */
383 0x1 0xc 0x1 0x0 0x2 0x0 /* ENET4_TXD0_SER4_TXD0 */
384 0x1 0xd 0x1 0x0 0x2 0x0 /* ENET4_TXD1_SER4_TXD1 */
385 0x1 0xe 0x1 0x0 0x1 0x0 /* ENET4_TXD2_SER4_TXD2 */
386 0x1 0xf 0x1 0x0 0x2 0x0 /* ENET4_TXD3_SER4_TXD3 */
387 0x1 0x12 0x2 0x0 0x2 0x0 /* ENET4_RXD0_SER4_RXD0 */
388 0x1 0x13 0x2 0x0 0x1 0x0 /* ENET4_RXD1_SER4_RXD1 */
389 0x1 0x14 0x2 0x0 0x1 0x0 /* ENET4_RXD2_SER4_RXD2 */
390 0x1 0x15 0x2 0x0 0x2 0x0 /* ENET4_RXD3_SER4_RXD3 */
391 0x1 0x10 0x1 0x0 0x2 0x0 /* ENET4_TX_EN_SER4_RTS_B */
392 0x1 0x18 0x2 0x0 0x3 0x0 /* ENET4_RX_DV_SER4_CTS_B */
393 0x2 0x11 0x2 0x0 0x2 0x0 /* ENET4_GRXCLK */
394 0x2 0x18 0x1 0x0 0x2 0x0>; /* ENET4_GTXCLK */
395 };
396 };
397 };
398
399 qe@e0080000 {
400 #address-cells = <1>;
401 #size-cells = <1>;
402 device_type = "qe";
403 compatible = "fsl,qe";
404 ranges = <0x0 0xe0080000 0x40000>;
405 reg = <0xe0080000 0x480>;
406 brg-frequency = <0>;
407 bus-frequency = <0>;
408 fsl,qe-num-riscs = <4>;
409 fsl,qe-num-snums = <46>;
410
411 qeic: interrupt-controller@80 {
412 interrupt-controller;
413 compatible = "fsl,qe-ic";
414 #address-cells = <0>;
415 #interrupt-cells = <1>;
416 reg = <0x80 0x80>;
417 interrupts = <46 2 46 2>; //high:30 low:30
418 interrupt-parent = <&mpic>;
419 };
420
421 spi@4c0 {
422 #address-cells = <1>;
423 #size-cells = <0>;
424 compatible = "fsl,mpc8569-qe-spi", "fsl,spi";
425 reg = <0x4c0 0x40>;
426 cell-index = <0>;
427 interrupts = <2>;
428 interrupt-parent = <&qeic>;
429 gpios = <&qe_pio_e 30 0>;
430 mode = "cpu-qe";
431
432 serial-flash@0 {
433 compatible = "stm,m25p40";
434 reg = <0>;
435 spi-max-frequency = <25000000>;
436 };
437 };
438
439 spi@500 {
440 cell-index = <1>;
441 compatible = "fsl,spi";
442 reg = <0x500 0x40>;
443 interrupts = <1>;
444 interrupt-parent = <&qeic>;
445 mode = "cpu";
446 };
447
448 enet0: ucc@2000 {
449 device_type = "network";
450 compatible = "ucc_geth";
451 cell-index = <1>;
452 reg = <0x2000 0x200>;
453 interrupts = <32>;
454 interrupt-parent = <&qeic>;
455 local-mac-address = [ 00 00 00 00 00 00 ];
456 rx-clock-name = "none";
457 tx-clock-name = "clk12";
458 pio-handle = <&pio1>;
459 phy-handle = <&qe_phy0>;
460 phy-connection-type = "rgmii-id";
461 };
462
463 mdio@2120 {
464 #address-cells = <1>;
465 #size-cells = <0>;
466 reg = <0x2120 0x18>;
467 compatible = "fsl,ucc-mdio";
468
469 qe_phy0: ethernet-phy@07 {
470 interrupt-parent = <&mpic>;
471 interrupts = <1 1>;
472 reg = <0x7>;
473 device_type = "ethernet-phy";
474 };
475 qe_phy1: ethernet-phy@01 {
476 interrupt-parent = <&mpic>;
477 interrupts = <2 1>;
478 reg = <0x1>;
479 device_type = "ethernet-phy";
480 };
481 qe_phy2: ethernet-phy@02 {
482 interrupt-parent = <&mpic>;
483 interrupts = <3 1>;
484 reg = <0x2>;
485 device_type = "ethernet-phy";
486 };
487 qe_phy3: ethernet-phy@03 {
488 interrupt-parent = <&mpic>;
489 interrupts = <4 1>;
490 reg = <0x3>;
491 device_type = "ethernet-phy";
492 };
493 qe_phy5: ethernet-phy@04 {
494 interrupt-parent = <&mpic>;
495 reg = <0x04>;
496 device_type = "ethernet-phy";
497 };
498 qe_phy7: ethernet-phy@06 {
499 interrupt-parent = <&mpic>;
500 reg = <0x6>;
501 device_type = "ethernet-phy";
502 };
503 };
504 mdio@3520 {
505 #address-cells = <1>;
506 #size-cells = <0>;
507 reg = <0x3520 0x18>;
508 compatible = "fsl,ucc-mdio";
509
510 tbi0: tbi-phy@15 {
511 reg = <0x15>;
512 device_type = "tbi-phy";
513 };
514 };
515 mdio@3720 {
516 #address-cells = <1>;
517 #size-cells = <0>;
518 reg = <0x3720 0x38>;
519 compatible = "fsl,ucc-mdio";
520 tbi1: tbi-phy@17 {
521 reg = <0x17>;
522 device_type = "tbi-phy";
523 };
524 };
525
526 enet2: ucc@2200 {
527 device_type = "network";
528 compatible = "ucc_geth";
529 cell-index = <3>;
530 reg = <0x2200 0x200>;
531 interrupts = <34>;
532 interrupt-parent = <&qeic>;
533 local-mac-address = [ 00 00 00 00 00 00 ];
534 rx-clock-name = "none";
535 tx-clock-name = "clk12";
536 pio-handle = <&pio3>;
537 phy-handle = <&qe_phy2>;
538 phy-connection-type = "rgmii-id";
539 };
540
541 enet1: ucc@3000 {
542 device_type = "network";
543 compatible = "ucc_geth";
544 cell-index = <2>;
545 reg = <0x3000 0x200>;
546 interrupts = <33>;
547 interrupt-parent = <&qeic>;
548 local-mac-address = [ 00 00 00 00 00 00 ];
549 rx-clock-name = "none";
550 tx-clock-name = "clk17";
551 pio-handle = <&pio2>;
552 phy-handle = <&qe_phy1>;
553 phy-connection-type = "rgmii-id";
554 };
555
556 enet3: ucc@3200 {
557 device_type = "network";
558 compatible = "ucc_geth";
559 cell-index = <4>;
560 reg = <0x3200 0x200>;
561 interrupts = <35>;
562 interrupt-parent = <&qeic>;
563 local-mac-address = [ 00 00 00 00 00 00 ];
564 rx-clock-name = "none";
565 tx-clock-name = "clk17";
566 pio-handle = <&pio4>;
567 phy-handle = <&qe_phy3>;
568 phy-connection-type = "rgmii-id";
569 };
570
571 enet5: ucc@3400 {
572 device_type = "network";
573 compatible = "ucc_geth";
574 cell-index = <6>;
575 reg = <0x3400 0x200>;
576 interrupts = <41>;
577 interrupt-parent = <&qeic>;
578 local-mac-address = [ 00 00 00 00 00 00 ];
579 rx-clock-name = "none";
580 tx-clock-name = "none";
581 tbi-handle = <&tbi0>;
582 phy-handle = <&qe_phy5>;
583 phy-connection-type = "sgmii";
584 };
585
586 enet7: ucc@3600 {
587 device_type = "network";
588 compatible = "ucc_geth";
589 cell-index = <8>;
590 reg = <0x3600 0x200>;
591 interrupts = <43>;
592 interrupt-parent = <&qeic>;
593 local-mac-address = [ 00 00 00 00 00 00 ];
594 rx-clock-name = "none";
595 tx-clock-name = "none";
596 tbi-handle = <&tbi1>;
597 phy-handle = <&qe_phy7>;
598 phy-connection-type = "sgmii";
599 };
600
601 muram@10000 {
602 #address-cells = <1>;
603 #size-cells = <1>;
604 compatible = "fsl,qe-muram", "fsl,cpm-muram";
605 ranges = <0x0 0x10000 0x20000>;
606
607 data-only@0 {
608 compatible = "fsl,qe-muram-data",
609 "fsl,cpm-muram-data";
610 reg = <0x0 0x20000>;
611 };
612 };
613
614 };
615
616 /* PCI Express */
617 pci1: pcie@e000a000 {
618 compatible = "fsl,mpc8548-pcie";
619 device_type = "pci";
620 #interrupt-cells = <1>;
621 #size-cells = <2>;
622 #address-cells = <3>;
623 reg = <0xe000a000 0x1000>;
624 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
625 interrupt-map = <
626 /* IDSEL 0x0 (PEX) */
627 00000 0x0 0x0 0x1 &mpic 0x0 0x1
628 00000 0x0 0x0 0x2 &mpic 0x1 0x1
629 00000 0x0 0x0 0x3 &mpic 0x2 0x1
630 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
631
632 interrupt-parent = <&mpic>;
633 interrupts = <26 2>;
634 bus-range = <0 255>;
635 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
636 0x1000000 0x0 0x00000000 0xe2800000 0x0 0x00800000>;
637 clock-frequency = <33333333>;
638 pcie@0 {
639 reg = <0x0 0x0 0x0 0x0 0x0>;
640 #size-cells = <2>;
641 #address-cells = <3>;
642 device_type = "pci";
643 ranges = <0x2000000 0x0 0xa0000000
644 0x2000000 0x0 0xa0000000
645 0x0 0x10000000
646
647 0x1000000 0x0 0x0
648 0x1000000 0x0 0x0
649 0x0 0x800000>;
650 };
651 };
652
653 rio0: rapidio@e00c00000 {
654 #address-cells = <2>;
655 #size-cells = <2>;
656 compatible = "fsl,mpc8569-rapidio", "fsl,rapidio-delta";
657 reg = <0xe00c0000 0x20000>;
658 ranges = <0x0 0x0 0xc0000000 0x0 0x20000000>;
659 interrupts = <48 2 /* error */
660 49 2 /* bell_outb */
661 50 2 /* bell_inb */
662 53 2 /* msg1_tx */
663 54 2 /* msg1_rx */
664 55 2 /* msg2_tx */
665 56 2 /* msg2_rx */>;
666 interrupt-parent = <&mpic>;
667 };
668};
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-27 10:25:56 -0500