1 files changed, 73 insertions, 38 deletions
diff --git a/arch/powerpc/boot/dts/mpc8569mds.dts b/arch/powerpc/boot/dts/mpc8569mds.dts
index 1e3ec8f059bf..795eb362fcf9 100644
--- a/arch/powerpc/boot/dts/mpc8569mds.dts
+++ b/arch/powerpc/boot/dts/mpc8569mds.dts
@@ -41,6 +41,8 @@
                        i-cache-line-size = <32>;       // 32 bytes
                        d-cache-size = <0x8000>;                // L1, 32K
                        i-cache-size = <0x8000>;                // L1, 32K
+                        sleep = <&pmc 0x00008000        // core
+                                 &pmc 0x00004000>;      // timebase
                        timebase-frequency = <0>;
                        bus-frequency = <0>;
                        clock-frequency = <0>;
@@ -59,6 +61,7 @@
                reg = <0xe0005000 0x1000>;
                interrupts = <19 2>;
                interrupt-parent = <&mpic>;
+                sleep = <&pmc 0x08000000>;
                ranges = <0x0 0x0 0xfe000000 0x02000000
                          0x1 0x0 0xf8000000 0x00008000
@@ -158,51 +161,69 @@
                        interrupts = <18 2>;
                };
-                i2c@3000 {
+                i2c-sleep-nexus {
                        #address-cells = <1>;
-                        #size-cells = <0>;
+                        #size-cells = <1>;
-                        cell-index = <0>;
+                        compatible = "simple-bus";
-                        compatible = "fsl-i2c";
+                        sleep = <&pmc 0x00000004>;
-                        reg = <0x3000 0x100>;
+                        ranges;
-                        interrupts = <43 2>;
-                        interrupt-parent = <&mpic>;
+                        i2c@3000 {
-                        dfsrr;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                cell-index = <0>;
+                                compatible = "fsl-i2c";
+                                reg = <0x3000 0x100>;
+                                interrupts = <43 2>;
+                                interrupt-parent = <&mpic>;
+                                dfsrr;
+                                rtc@68 {
+                                        compatible = "dallas,ds1374";
+                                        reg = <0x68>;
+                                        interrupts = <3 1>;
+                                        interrupt-parent = <&mpic>;
+                                };
+                        };
-                        rtc@68 {
+                        i2c@3100 {
-                                compatible = "dallas,ds1374";
+                                #address-cells = <1>;
-                                reg = <0x68>;
+                                #size-cells = <0>;
+                                cell-index = <1>;
+                                compatible = "fsl-i2c";
+                                reg = <0x3100 0x100>;
+                                interrupts = <43 2>;
+                                interrupt-parent = <&mpic>;
+                                dfsrr;
                        };
                };
-                i2c@3100 {
+                duart-sleep-nexus {
                        #address-cells = <1>;
-                        #size-cells = <0>;
+                        #size-cells = <1>;
-                        cell-index = <1>;
+                        compatible = "simple-bus";
-                        compatible = "fsl-i2c";
+                        sleep = <&pmc 0x00000002>;
-                        reg = <0x3100 0x100>;
+                        ranges;
-                        interrupts = <43 2>;
-                        interrupt-parent = <&mpic>;
-                        dfsrr;
-                };
-                serial0: serial@4500 {
+                        serial0: serial@4500 {
-                        cell-index = <0>;
+                                cell-index = <0>;
-                        device_type = "serial";
+                                device_type = "serial";
-                        compatible = "ns16550";
+                                compatible = "ns16550";
-                        reg = <0x4500 0x100>;
+                                reg = <0x4500 0x100>;
-                        clock-frequency = <0>;
+                                clock-frequency = <0>;
-                        interrupts = <42 2>;
+                                interrupts = <42 2>;
-                        interrupt-parent = <&mpic>;
+                                interrupt-parent = <&mpic>;
-                };
+                        };
-                serial1: serial@4600 {
+                        serial1: serial@4600 {
-                        cell-index = <1>;
+                                cell-index = <1>;
-                        device_type = "serial";
+                                device_type = "serial";
-                        compatible = "ns16550";
+                                compatible = "ns16550";
-                        reg = <0x4600 0x100>;
+                                reg = <0x4600 0x100>;
-                        clock-frequency = <0>;
+                                clock-frequency = <0>;
-                        interrupts = <42 2>;
+                                interrupts = <42 2>;
-                        interrupt-parent = <&mpic>;
+                                interrupt-parent = <&mpic>;
+                        };
                };
                L2: l2-cache-controller@20000 {
@@ -260,6 +281,7 @@
                        reg = <0x2e000 0x1000>;
                        interrupts = <72 0x8>;
                        interrupt-parent = <&mpic>;
+                        sleep = <&pmc 0x00200000>;
                        /* Filled in by U-Boot */
                        clock-frequency = <0>;
                        status = "disabled";
@@ -276,6 +298,7 @@
                        fsl,channel-fifo-len = <24>;
                        fsl,exec-units-mask = <0xbfe>;
                        fsl,descriptor-types-mask = <0x3ab0ebf>;
+                        sleep = <&pmc 0x01000000>;
                };
                mpic: pic@40000 {
@@ -304,9 +327,18 @@
                };
                global-utilities@e0000 {
-                        compatible = "fsl,mpc8569-guts";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,mpc8569-guts", "fsl,mpc8548-guts";
                        reg = <0xe0000 0x1000>;
+                        ranges = <0 0xe0000 0x1000>;
                        fsl,has-rstcr;
+                        pmc: power@70 {
+                                compatible = "fsl,mpc8569-pmc",
+                                             "fsl,mpc8548-pmc";
+                                reg = <0x70 0x20>;
+                        };
                };
                par_io@e0100 {
@@ -422,6 +454,7 @@
                compatible = "fsl,qe";
                ranges = <0x0 0xe0080000 0x40000>;
                reg = <0xe0080000 0x480>;
+                sleep = <&pmc 0x00000800>;
                brg-frequency = <0>;
                bus-frequency = <0>;
                fsl,qe-num-riscs = <4>;
@@ -684,6 +717,7 @@
                bus-range = <0 255>;
                ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
                          0x1000000 0x0 0x00000000 0xe2800000 0x0 0x00800000>;
+                sleep = <&pmc 0x20000000>;
                clock-frequency = <33333333>;
                pcie@0 {
                        reg = <0x0 0x0 0x0 0x0 0x0>;
@@ -714,5 +748,6 @@
                              55 2 /* msg2_tx   */
                              56 2 /* msg2_rx   */>;
                interrupt-parent = <&mpic>;
+                sleep = <&pmc 0x00080000>;
        };
 };

diff --git a/arch/powerpc/boot/dts/mpc8569mds.dts b/arch/powerpc/boot/dts/mpc8569mds.dts index 1e3ec8f059bf..795eb362fcf9 100644 --- a/arch/powerpc/boot/dts/mpc8569mds.dts +++ b/arch/powerpc/boot/dts/mpc8569mds.dts
@@ -41,6 +41,8 @@
41	i-cache-line-size = <32>; // 32 bytes	41	i-cache-line-size = <32>; // 32 bytes
42	d-cache-size = <0x8000>; // L1, 32K	42	d-cache-size = <0x8000>; // L1, 32K
43	i-cache-size = <0x8000>; // L1, 32K	43	i-cache-size = <0x8000>; // L1, 32K
		44	sleep = <&pmc 0x00008000 // core
		45	&pmc 0x00004000>; // timebase
44	timebase-frequency = <0>;	46	timebase-frequency = <0>;
45	bus-frequency = <0>;	47	bus-frequency = <0>;
46	clock-frequency = <0>;	48	clock-frequency = <0>;
@@ -59,6 +61,7 @@
59	reg = <0xe0005000 0x1000>;	61	reg = <0xe0005000 0x1000>;
60	interrupts = <19 2>;	62	interrupts = <19 2>;
61	interrupt-parent = <&mpic>;	63	interrupt-parent = <&mpic>;
		64	sleep = <&pmc 0x08000000>;
62		65
63	ranges = <0x0 0x0 0xfe000000 0x02000000	66	ranges = <0x0 0x0 0xfe000000 0x02000000
64	0x1 0x0 0xf8000000 0x00008000	67	0x1 0x0 0xf8000000 0x00008000
@@ -158,51 +161,69 @@
158	interrupts = <18 2>;	161	interrupts = <18 2>;
159	};	162	};
160		163
161	i2c@3000 {	164	i2c-sleep-nexus {
162	#address-cells = <1>;	165	#address-cells = <1>;
163	#size-cells = <0>;	166	#size-cells = <1>;
164	cell-index = <0>;	167	compatible = "simple-bus";
165	compatible = "fsl-i2c";	168	sleep = <&pmc 0x00000004>;
166	reg = <0x3000 0x100>;	169	ranges;
167	interrupts = <43 2>;	170
168	interrupt-parent = <&mpic>;	171	i2c@3000 {
169	dfsrr;	172	#address-cells = <1>;
		173	#size-cells = <0>;
		174	cell-index = <0>;
		175	compatible = "fsl-i2c";
		176	reg = <0x3000 0x100>;
		177	interrupts = <43 2>;
		178	interrupt-parent = <&mpic>;
		179	dfsrr;
		180
		181	rtc@68 {
		182	compatible = "dallas,ds1374";
		183	reg = <0x68>;
		184	interrupts = <3 1>;
		185	interrupt-parent = <&mpic>;
		186	};
		187	};
170		188
171	rtc@68 {	189	i2c@3100 {
172	compatible = "dallas,ds1374";	190	#address-cells = <1>;
173	reg = <0x68>;	191	#size-cells = <0>;
		192	cell-index = <1>;
		193	compatible = "fsl-i2c";
		194	reg = <0x3100 0x100>;
		195	interrupts = <43 2>;
		196	interrupt-parent = <&mpic>;
		197	dfsrr;
174	};	198	};
175	};	199	};
176		200
177	i2c@3100 {	201	duart-sleep-nexus {
178	#address-cells = <1>;	202	#address-cells = <1>;
179	#size-cells = <0>;	203	#size-cells = <1>;
180	cell-index = <1>;	204	compatible = "simple-bus";
181	compatible = "fsl-i2c";	205	sleep = <&pmc 0x00000002>;
182	reg = <0x3100 0x100>;	206	ranges;
183	interrupts = <43 2>;
184	interrupt-parent = <&mpic>;
185	dfsrr;
186	};
187		207
188	serial0: serial@4500 {	208	serial0: serial@4500 {
189	cell-index = <0>;	209	cell-index = <0>;
190	device_type = "serial";	210	device_type = "serial";
191	compatible = "ns16550";	211	compatible = "ns16550";
192	reg = <0x4500 0x100>;	212	reg = <0x4500 0x100>;
193	clock-frequency = <0>;	213	clock-frequency = <0>;
194	interrupts = <42 2>;	214	interrupts = <42 2>;
195	interrupt-parent = <&mpic>;	215	interrupt-parent = <&mpic>;
196	};	216	};
197		217
198	serial1: serial@4600 {	218	serial1: serial@4600 {
199	cell-index = <1>;	219	cell-index = <1>;
200	device_type = "serial";	220	device_type = "serial";
201	compatible = "ns16550";	221	compatible = "ns16550";
202	reg = <0x4600 0x100>;	222	reg = <0x4600 0x100>;
203	clock-frequency = <0>;	223	clock-frequency = <0>;
204	interrupts = <42 2>;	224	interrupts = <42 2>;
205	interrupt-parent = <&mpic>;	225	interrupt-parent = <&mpic>;
		226	};
206	};	227	};
207		228
208	L2: l2-cache-controller@20000 {	229	L2: l2-cache-controller@20000 {
@@ -260,6 +281,7 @@
260	reg = <0x2e000 0x1000>;	281	reg = <0x2e000 0x1000>;
261	interrupts = <72 0x8>;	282	interrupts = <72 0x8>;
262	interrupt-parent = <&mpic>;	283	interrupt-parent = <&mpic>;
		284	sleep = <&pmc 0x00200000>;
263	/* Filled in by U-Boot */	285	/* Filled in by U-Boot */
264	clock-frequency = <0>;	286	clock-frequency = <0>;
265	status = "disabled";	287	status = "disabled";
@@ -276,6 +298,7 @@
276	fsl,channel-fifo-len = <24>;	298	fsl,channel-fifo-len = <24>;
277	fsl,exec-units-mask = <0xbfe>;	299	fsl,exec-units-mask = <0xbfe>;
278	fsl,descriptor-types-mask = <0x3ab0ebf>;	300	fsl,descriptor-types-mask = <0x3ab0ebf>;
		301	sleep = <&pmc 0x01000000>;
279	};	302	};
280		303
281	mpic: pic@40000 {	304	mpic: pic@40000 {
@@ -304,9 +327,18 @@
304	};	327	};
305		328
306	global-utilities@e0000 {	329	global-utilities@e0000 {
307	compatible = "fsl,mpc8569-guts";	330	#address-cells = <1>;
		331	#size-cells = <1>;
		332	compatible = "fsl,mpc8569-guts", "fsl,mpc8548-guts";
308	reg = <0xe0000 0x1000>;	333	reg = <0xe0000 0x1000>;
		334	ranges = <0 0xe0000 0x1000>;
309	fsl,has-rstcr;	335	fsl,has-rstcr;
		336
		337	pmc: power@70 {
		338	compatible = "fsl,mpc8569-pmc",
		339	"fsl,mpc8548-pmc";
		340	reg = <0x70 0x20>;
		341	};
310	};	342	};
311		343
312	par_io@e0100 {	344	par_io@e0100 {
@@ -422,6 +454,7 @@
422	compatible = "fsl,qe";	454	compatible = "fsl,qe";
423	ranges = <0x0 0xe0080000 0x40000>;	455	ranges = <0x0 0xe0080000 0x40000>;
424	reg = <0xe0080000 0x480>;	456	reg = <0xe0080000 0x480>;
		457	sleep = <&pmc 0x00000800>;
425	brg-frequency = <0>;	458	brg-frequency = <0>;
426	bus-frequency = <0>;	459	bus-frequency = <0>;
427	fsl,qe-num-riscs = <4>;	460	fsl,qe-num-riscs = <4>;
@@ -684,6 +717,7 @@
684	bus-range = <0 255>;	717	bus-range = <0 255>;
685	ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000	718	ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
686	0x1000000 0x0 0x00000000 0xe2800000 0x0 0x00800000>;	719	0x1000000 0x0 0x00000000 0xe2800000 0x0 0x00800000>;
		720	sleep = <&pmc 0x20000000>;
687	clock-frequency = <33333333>;	721	clock-frequency = <33333333>;
688	pcie@0 {	722	pcie@0 {
689	reg = <0x0 0x0 0x0 0x0 0x0>;	723	reg = <0x0 0x0 0x0 0x0 0x0>;
@@ -714,5 +748,6 @@
714	55 2 /* msg2_tx */	748	55 2 /* msg2_tx */
715	56 2 /* msg2_rx */>;	749	56 2 /* msg2_rx */>;
716	interrupt-parent = <&mpic>;	750	interrupt-parent = <&mpic>;
		751	sleep = <&pmc 0x00080000>;
717	};	752	};
718	};	753	};