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-rw-r--r--arch/powerpc/boot/dts/mpc8568mds.dts291
1 files changed, 142 insertions, 149 deletions
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index 97bc048f2158..a025a8ededc5 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8568E MDS Device Tree Source 2 * MPC8568E MDS Device Tree Source
3 * 3 *
4 * Copyright 2007 Freescale Semiconductor Inc. 4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,10 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12 12/dts-v1/;
13/*
14/memreserve/ 00000000 1000000;
15*/
16 13
17/ { 14/ {
18 model = "MPC8568EMDS"; 15 model = "MPC8568EMDS";
@@ -37,11 +34,11 @@
37 34
38 PowerPC,8568@0 { 35 PowerPC,8568@0 {
39 device_type = "cpu"; 36 device_type = "cpu";
40 reg = <0>; 37 reg = <0x0>;
41 d-cache-line-size = <20>; // 32 bytes 38 d-cache-line-size = <32>; // 32 bytes
42 i-cache-line-size = <20>; // 32 bytes 39 i-cache-line-size = <32>; // 32 bytes
43 d-cache-size = <8000>; // L1, 32K 40 d-cache-size = <0x8000>; // L1, 32K
44 i-cache-size = <8000>; // L1, 32K 41 i-cache-size = <0x8000>; // L1, 32K
45 timebase-frequency = <0>; 42 timebase-frequency = <0>;
46 bus-frequency = <0>; 43 bus-frequency = <0>;
47 clock-frequency = <0>; 44 clock-frequency = <0>;
@@ -50,36 +47,36 @@
50 47
51 memory { 48 memory {
52 device_type = "memory"; 49 device_type = "memory";
53 reg = <00000000 10000000>; 50 reg = <0x0 0x10000000>;
54 }; 51 };
55 52
56 bcsr@f8000000 { 53 bcsr@f8000000 {
57 device_type = "board-control"; 54 device_type = "board-control";
58 reg = <f8000000 8000>; 55 reg = <0xf8000000 0x8000>;
59 }; 56 };
60 57
61 soc8568@e0000000 { 58 soc8568@e0000000 {
62 #address-cells = <1>; 59 #address-cells = <1>;
63 #size-cells = <1>; 60 #size-cells = <1>;
64 device_type = "soc"; 61 device_type = "soc";
65 ranges = <0 e0000000 00100000>; 62 ranges = <0x0 0xe0000000 0x100000>;
66 reg = <e0000000 00001000>; 63 reg = <0xe0000000 0x1000>;
67 bus-frequency = <0>; 64 bus-frequency = <0>;
68 65
69 memory-controller@2000 { 66 memory-controller@2000 {
70 compatible = "fsl,8568-memory-controller"; 67 compatible = "fsl,8568-memory-controller";
71 reg = <2000 1000>; 68 reg = <0x2000 0x1000>;
72 interrupt-parent = <&mpic>; 69 interrupt-parent = <&mpic>;
73 interrupts = <12 2>; 70 interrupts = <18 2>;
74 }; 71 };
75 72
76 l2-cache-controller@20000 { 73 l2-cache-controller@20000 {
77 compatible = "fsl,8568-l2-cache-controller"; 74 compatible = "fsl,8568-l2-cache-controller";
78 reg = <20000 1000>; 75 reg = <0x20000 0x1000>;
79 cache-line-size = <20>; // 32 bytes 76 cache-line-size = <32>; // 32 bytes
80 cache-size = <80000>; // L2, 512K 77 cache-size = <0x80000>; // L2, 512K
81 interrupt-parent = <&mpic>; 78 interrupt-parent = <&mpic>;
82 interrupts = <10 2>; 79 interrupts = <16 2>;
83 }; 80 };
84 81
85 i2c@3000 { 82 i2c@3000 {
@@ -87,14 +84,14 @@
87 #size-cells = <0>; 84 #size-cells = <0>;
88 cell-index = <0>; 85 cell-index = <0>;
89 compatible = "fsl-i2c"; 86 compatible = "fsl-i2c";
90 reg = <3000 100>; 87 reg = <0x3000 0x100>;
91 interrupts = <2b 2>; 88 interrupts = <43 2>;
92 interrupt-parent = <&mpic>; 89 interrupt-parent = <&mpic>;
93 dfsrr; 90 dfsrr;
94 91
95 rtc@68 { 92 rtc@68 {
96 compatible = "dallas,ds1374"; 93 compatible = "dallas,ds1374";
97 reg = <68>; 94 reg = <0x68>;
98 }; 95 };
99 }; 96 };
100 97
@@ -103,8 +100,8 @@
103 #size-cells = <0>; 100 #size-cells = <0>;
104 cell-index = <1>; 101 cell-index = <1>;
105 compatible = "fsl-i2c"; 102 compatible = "fsl-i2c";
106 reg = <3100 100>; 103 reg = <0x3100 0x100>;
107 interrupts = <2b 2>; 104 interrupts = <43 2>;
108 interrupt-parent = <&mpic>; 105 interrupt-parent = <&mpic>;
109 dfsrr; 106 dfsrr;
110 }; 107 };
@@ -113,30 +110,30 @@
113 #address-cells = <1>; 110 #address-cells = <1>;
114 #size-cells = <0>; 111 #size-cells = <0>;
115 compatible = "fsl,gianfar-mdio"; 112 compatible = "fsl,gianfar-mdio";
116 reg = <24520 20>; 113 reg = <0x24520 0x20>;
117 114
118 phy0: ethernet-phy@7 { 115 phy0: ethernet-phy@7 {
119 interrupt-parent = <&mpic>; 116 interrupt-parent = <&mpic>;
120 interrupts = <1 1>; 117 interrupts = <1 1>;
121 reg = <7>; 118 reg = <0x7>;
122 device_type = "ethernet-phy"; 119 device_type = "ethernet-phy";
123 }; 120 };
124 phy1: ethernet-phy@1 { 121 phy1: ethernet-phy@1 {
125 interrupt-parent = <&mpic>; 122 interrupt-parent = <&mpic>;
126 interrupts = <2 1>; 123 interrupts = <2 1>;
127 reg = <1>; 124 reg = <0x1>;
128 device_type = "ethernet-phy"; 125 device_type = "ethernet-phy";
129 }; 126 };
130 phy2: ethernet-phy@2 { 127 phy2: ethernet-phy@2 {
131 interrupt-parent = <&mpic>; 128 interrupt-parent = <&mpic>;
132 interrupts = <1 1>; 129 interrupts = <1 1>;
133 reg = <2>; 130 reg = <0x2>;
134 device_type = "ethernet-phy"; 131 device_type = "ethernet-phy";
135 }; 132 };
136 phy3: ethernet-phy@3 { 133 phy3: ethernet-phy@3 {
137 interrupt-parent = <&mpic>; 134 interrupt-parent = <&mpic>;
138 interrupts = <2 1>; 135 interrupts = <2 1>;
139 reg = <3>; 136 reg = <0x3>;
140 device_type = "ethernet-phy"; 137 device_type = "ethernet-phy";
141 }; 138 };
142 }; 139 };
@@ -146,9 +143,9 @@
146 device_type = "network"; 143 device_type = "network";
147 model = "eTSEC"; 144 model = "eTSEC";
148 compatible = "gianfar"; 145 compatible = "gianfar";
149 reg = <24000 1000>; 146 reg = <0x24000 0x1000>;
150 local-mac-address = [ 00 00 00 00 00 00 ]; 147 local-mac-address = [ 00 00 00 00 00 00 ];
151 interrupts = <1d 2 1e 2 22 2>; 148 interrupts = <29 2 30 2 34 2>;
152 interrupt-parent = <&mpic>; 149 interrupt-parent = <&mpic>;
153 phy-handle = <&phy2>; 150 phy-handle = <&phy2>;
154 }; 151 };
@@ -158,9 +155,9 @@
158 device_type = "network"; 155 device_type = "network";
159 model = "eTSEC"; 156 model = "eTSEC";
160 compatible = "gianfar"; 157 compatible = "gianfar";
161 reg = <25000 1000>; 158 reg = <0x25000 0x1000>;
162 local-mac-address = [ 00 00 00 00 00 00 ]; 159 local-mac-address = [ 00 00 00 00 00 00 ];
163 interrupts = <23 2 24 2 28 2>; 160 interrupts = <35 2 36 2 40 2>;
164 interrupt-parent = <&mpic>; 161 interrupt-parent = <&mpic>;
165 phy-handle = <&phy3>; 162 phy-handle = <&phy3>;
166 }; 163 };
@@ -169,15 +166,15 @@
169 cell-index = <0>; 166 cell-index = <0>;
170 device_type = "serial"; 167 device_type = "serial";
171 compatible = "ns16550"; 168 compatible = "ns16550";
172 reg = <4500 100>; 169 reg = <0x4500 0x100>;
173 clock-frequency = <0>; 170 clock-frequency = <0>;
174 interrupts = <2a 2>; 171 interrupts = <42 2>;
175 interrupt-parent = <&mpic>; 172 interrupt-parent = <&mpic>;
176 }; 173 };
177 174
178 global-utilities@e0000 { //global utilities block 175 global-utilities@e0000 { //global utilities block
179 compatible = "fsl,mpc8548-guts"; 176 compatible = "fsl,mpc8548-guts";
180 reg = <e0000 1000>; 177 reg = <0xe0000 0x1000>;
181 fsl,has-rstcr; 178 fsl,has-rstcr;
182 }; 179 };
183 180
@@ -185,9 +182,9 @@
185 cell-index = <1>; 182 cell-index = <1>;
186 device_type = "serial"; 183 device_type = "serial";
187 compatible = "ns16550"; 184 compatible = "ns16550";
188 reg = <4600 100>; 185 reg = <0x4600 0x100>;
189 clock-frequency = <0>; 186 clock-frequency = <0>;
190 interrupts = <2a 2>; 187 interrupts = <42 2>;
191 interrupt-parent = <&mpic>; 188 interrupt-parent = <&mpic>;
192 }; 189 };
193 190
@@ -195,13 +192,13 @@
195 device_type = "crypto"; 192 device_type = "crypto";
196 model = "SEC2"; 193 model = "SEC2";
197 compatible = "talitos"; 194 compatible = "talitos";
198 reg = <30000 f000>; 195 reg = <0x30000 0xf000>;
199 interrupts = <2d 2>; 196 interrupts = <45 2>;
200 interrupt-parent = <&mpic>; 197 interrupt-parent = <&mpic>;
201 num-channels = <4>; 198 num-channels = <4>;
202 channel-fifo-len = <18>; 199 channel-fifo-len = <24>;
203 exec-units-mask = <000000fe>; 200 exec-units-mask = <0xfe>;
204 descriptor-types-mask = <012b0ebf>; 201 descriptor-types-mask = <0x12b0ebf>;
205 }; 202 };
206 203
207 mpic: pic@40000 { 204 mpic: pic@40000 {
@@ -209,73 +206,73 @@
209 interrupt-controller; 206 interrupt-controller;
210 #address-cells = <0>; 207 #address-cells = <0>;
211 #interrupt-cells = <2>; 208 #interrupt-cells = <2>;
212 reg = <40000 40000>; 209 reg = <0x40000 0x40000>;
213 compatible = "chrp,open-pic"; 210 compatible = "chrp,open-pic";
214 device_type = "open-pic"; 211 device_type = "open-pic";
215 big-endian; 212 big-endian;
216 }; 213 };
217 214
218 par_io@e0100 { 215 par_io@e0100 {
219 reg = <e0100 100>; 216 reg = <0xe0100 0x100>;
220 device_type = "par_io"; 217 device_type = "par_io";
221 num-ports = <7>; 218 num-ports = <7>;
222 219
223 pio1: ucc_pin@01 { 220 pio1: ucc_pin@01 {
224 pio-map = < 221 pio-map = <
225 /* port pin dir open_drain assignment has_irq */ 222 /* port pin dir open_drain assignment has_irq */
226 4 0a 1 0 2 0 /* TxD0 */ 223 0x4 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
227 4 09 1 0 2 0 /* TxD1 */ 224 0x4 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
228 4 08 1 0 2 0 /* TxD2 */ 225 0x4 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
229 4 07 1 0 2 0 /* TxD3 */ 226 0x4 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
230 4 17 1 0 2 0 /* TxD4 */ 227 0x4 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
231 4 16 1 0 2 0 /* TxD5 */ 228 0x4 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
232 4 15 1 0 2 0 /* TxD6 */ 229 0x4 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
233 4 14 1 0 2 0 /* TxD7 */ 230 0x4 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
234 4 0f 2 0 2 0 /* RxD0 */ 231 0x4 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
235 4 0e 2 0 2 0 /* RxD1 */ 232 0x4 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
236 4 0d 2 0 2 0 /* RxD2 */ 233 0x4 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
237 4 0c 2 0 2 0 /* RxD3 */ 234 0x4 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
238 4 1d 2 0 2 0 /* RxD4 */ 235 0x4 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
239 4 1c 2 0 2 0 /* RxD5 */ 236 0x4 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
240 4 1b 2 0 2 0 /* RxD6 */ 237 0x4 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
241 4 1a 2 0 2 0 /* RxD7 */ 238 0x4 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
242 4 0b 1 0 2 0 /* TX_EN */ 239 0x4 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
243 4 18 1 0 2 0 /* TX_ER */ 240 0x4 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
244 4 10 2 0 2 0 /* RX_DV */ 241 0x4 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
245 4 1e 2 0 2 0 /* RX_ER */ 242 0x4 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
246 4 11 2 0 2 0 /* RX_CLK */ 243 0x4 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
247 4 13 1 0 2 0 /* GTX_CLK */ 244 0x4 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
248 1 1f 2 0 3 0>; /* GTX125 */ 245 0x1 0x1f 0x2 0x0 0x3 0x0>; /* GTX125 */
249 }; 246 };
250 247
251 pio2: ucc_pin@02 { 248 pio2: ucc_pin@02 {
252 pio-map = < 249 pio-map = <
253 /* port pin dir open_drain assignment has_irq */ 250 /* port pin dir open_drain assignment has_irq */
254 5 0a 1 0 2 0 /* TxD0 */ 251 0x5 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
255 5 09 1 0 2 0 /* TxD1 */ 252 0x5 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
256 5 08 1 0 2 0 /* TxD2 */ 253 0x5 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
257 5 07 1 0 2 0 /* TxD3 */ 254 0x5 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
258 5 17 1 0 2 0 /* TxD4 */ 255 0x5 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
259 5 16 1 0 2 0 /* TxD5 */ 256 0x5 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
260 5 15 1 0 2 0 /* TxD6 */ 257 0x5 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
261 5 14 1 0 2 0 /* TxD7 */ 258 0x5 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
262 5 0f 2 0 2 0 /* RxD0 */ 259 0x5 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
263 5 0e 2 0 2 0 /* RxD1 */ 260 0x5 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
264 5 0d 2 0 2 0 /* RxD2 */ 261 0x5 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
265 5 0c 2 0 2 0 /* RxD3 */ 262 0x5 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
266 5 1d 2 0 2 0 /* RxD4 */ 263 0x5 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
267 5 1c 2 0 2 0 /* RxD5 */ 264 0x5 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
268 5 1b 2 0 2 0 /* RxD6 */ 265 0x5 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
269 5 1a 2 0 2 0 /* RxD7 */ 266 0x5 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
270 5 0b 1 0 2 0 /* TX_EN */ 267 0x5 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
271 5 18 1 0 2 0 /* TX_ER */ 268 0x5 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
272 5 10 2 0 2 0 /* RX_DV */ 269 0x5 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
273 5 1e 2 0 2 0 /* RX_ER */ 270 0x5 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
274 5 11 2 0 2 0 /* RX_CLK */ 271 0x5 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
275 5 13 1 0 2 0 /* GTX_CLK */ 272 0x5 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
276 1 1f 2 0 3 0 /* GTX125 */ 273 0x1 0x1f 0x2 0x0 0x3 0x0 /* GTX125 */
277 4 06 3 0 2 0 /* MDIO */ 274 0x4 0x6 0x3 0x0 0x2 0x0 /* MDIO */
278 4 05 1 0 2 0>; /* MDC */ 275 0x4 0x5 0x1 0x0 0x2 0x0>; /* MDC */
279 }; 276 };
280 }; 277 };
281 }; 278 };
@@ -285,28 +282,28 @@
285 #size-cells = <1>; 282 #size-cells = <1>;
286 device_type = "qe"; 283 device_type = "qe";
287 compatible = "fsl,qe"; 284 compatible = "fsl,qe";
288 ranges = <0 e0080000 00040000>; 285 ranges = <0x0 0xe0080000 0x40000>;
289 reg = <e0080000 480>; 286 reg = <0xe0080000 0x480>;
290 brg-frequency = <0>; 287 brg-frequency = <0>;
291 bus-frequency = <179A7B00>; 288 bus-frequency = <396000000>;
292 289
293 muram@10000 { 290 muram@10000 {
294 #address-cells = <1>; 291 #address-cells = <1>;
295 #size-cells = <1>; 292 #size-cells = <1>;
296 compatible = "fsl,qe-muram", "fsl,cpm-muram"; 293 compatible = "fsl,qe-muram", "fsl,cpm-muram";
297 ranges = <0 00010000 0000c000>; 294 ranges = <0x0 0x10000 0x10000>;
298 295
299 data-only@0 { 296 data-only@0 {
300 compatible = "fsl,qe-muram-data", 297 compatible = "fsl,qe-muram-data",
301 "fsl,cpm-muram-data"; 298 "fsl,cpm-muram-data";
302 reg = <0 c000>; 299 reg = <0x0 0x10000>;
303 }; 300 };
304 }; 301 };
305 302
306 spi@4c0 { 303 spi@4c0 {
307 cell-index = <0>; 304 cell-index = <0>;
308 compatible = "fsl,spi"; 305 compatible = "fsl,spi";
309 reg = <4c0 40>; 306 reg = <0x4c0 0x40>;
310 interrupts = <2>; 307 interrupts = <2>;
311 interrupt-parent = <&qeic>; 308 interrupt-parent = <&qeic>;
312 mode = "cpu"; 309 mode = "cpu";
@@ -315,7 +312,7 @@
315 spi@500 { 312 spi@500 {
316 cell-index = <1>; 313 cell-index = <1>;
317 compatible = "fsl,spi"; 314 compatible = "fsl,spi";
318 reg = <500 40>; 315 reg = <0x500 0x40>;
319 interrupts = <1>; 316 interrupts = <1>;
320 interrupt-parent = <&qeic>; 317 interrupt-parent = <&qeic>;
321 mode = "cpu"; 318 mode = "cpu";
@@ -324,11 +321,9 @@
324 enet2: ucc@2000 { 321 enet2: ucc@2000 {
325 device_type = "network"; 322 device_type = "network";
326 compatible = "ucc_geth"; 323 compatible = "ucc_geth";
327 model = "UCC";
328 cell-index = <1>; 324 cell-index = <1>;
329 device-id = <1>; 325 reg = <0x2000 0x200>;
330 reg = <2000 200>; 326 interrupts = <32>;
331 interrupts = <20>;
332 interrupt-parent = <&qeic>; 327 interrupt-parent = <&qeic>;
333 local-mac-address = [ 00 00 00 00 00 00 ]; 328 local-mac-address = [ 00 00 00 00 00 00 ];
334 rx-clock-name = "none"; 329 rx-clock-name = "none";
@@ -341,11 +336,9 @@
341 enet3: ucc@3000 { 336 enet3: ucc@3000 {
342 device_type = "network"; 337 device_type = "network";
343 compatible = "ucc_geth"; 338 compatible = "ucc_geth";
344 model = "UCC";
345 cell-index = <2>; 339 cell-index = <2>;
346 device-id = <2>; 340 reg = <0x3000 0x200>;
347 reg = <3000 200>; 341 interrupts = <33>;
348 interrupts = <21>;
349 interrupt-parent = <&qeic>; 342 interrupt-parent = <&qeic>;
350 local-mac-address = [ 00 00 00 00 00 00 ]; 343 local-mac-address = [ 00 00 00 00 00 00 ];
351 rx-clock-name = "none"; 344 rx-clock-name = "none";
@@ -358,7 +351,7 @@
358 mdio@2120 { 351 mdio@2120 {
359 #address-cells = <1>; 352 #address-cells = <1>;
360 #size-cells = <0>; 353 #size-cells = <0>;
361 reg = <2120 18>; 354 reg = <0x2120 0x18>;
362 compatible = "fsl,ucc-mdio"; 355 compatible = "fsl,ucc-mdio";
363 356
364 /* These are the same PHYs as on 357 /* These are the same PHYs as on
@@ -366,25 +359,25 @@
366 qe_phy0: ethernet-phy@07 { 359 qe_phy0: ethernet-phy@07 {
367 interrupt-parent = <&mpic>; 360 interrupt-parent = <&mpic>;
368 interrupts = <1 1>; 361 interrupts = <1 1>;
369 reg = <7>; 362 reg = <0x7>;
370 device_type = "ethernet-phy"; 363 device_type = "ethernet-phy";
371 }; 364 };
372 qe_phy1: ethernet-phy@01 { 365 qe_phy1: ethernet-phy@01 {
373 interrupt-parent = <&mpic>; 366 interrupt-parent = <&mpic>;
374 interrupts = <2 1>; 367 interrupts = <2 1>;
375 reg = <1>; 368 reg = <0x1>;
376 device_type = "ethernet-phy"; 369 device_type = "ethernet-phy";
377 }; 370 };
378 qe_phy2: ethernet-phy@02 { 371 qe_phy2: ethernet-phy@02 {
379 interrupt-parent = <&mpic>; 372 interrupt-parent = <&mpic>;
380 interrupts = <1 1>; 373 interrupts = <1 1>;
381 reg = <2>; 374 reg = <0x2>;
382 device_type = "ethernet-phy"; 375 device_type = "ethernet-phy";
383 }; 376 };
384 qe_phy3: ethernet-phy@03 { 377 qe_phy3: ethernet-phy@03 {
385 interrupt-parent = <&mpic>; 378 interrupt-parent = <&mpic>;
386 interrupts = <2 1>; 379 interrupts = <2 1>;
387 reg = <3>; 380 reg = <0x3>;
388 device_type = "ethernet-phy"; 381 device_type = "ethernet-phy";
389 }; 382 };
390 }; 383 };
@@ -394,9 +387,9 @@
394 compatible = "fsl,qe-ic"; 387 compatible = "fsl,qe-ic";
395 #address-cells = <0>; 388 #address-cells = <0>;
396 #interrupt-cells = <1>; 389 #interrupt-cells = <1>;
397 reg = <80 80>; 390 reg = <0x80 0x80>;
398 big-endian; 391 big-endian;
399 interrupts = <2e 2 2e 2>; //high:30 low:30 392 interrupts = <46 2 46 2>; //high:30 low:30
400 interrupt-parent = <&mpic>; 393 interrupt-parent = <&mpic>;
401 }; 394 };
402 395
@@ -404,30 +397,30 @@
404 397
405 pci0: pci@e0008000 { 398 pci0: pci@e0008000 {
406 cell-index = <0>; 399 cell-index = <0>;
407 interrupt-map-mask = <f800 0 0 7>; 400 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
408 interrupt-map = < 401 interrupt-map = <
409 /* IDSEL 0x12 AD18 */ 402 /* IDSEL 0x12 AD18 */
410 9000 0 0 1 &mpic 5 1 403 0x9000 0x0 0x0 0x1 &mpic 0x5 0x1
411 9000 0 0 2 &mpic 6 1 404 0x9000 0x0 0x0 0x2 &mpic 0x6 0x1
412 9000 0 0 3 &mpic 7 1 405 0x9000 0x0 0x0 0x3 &mpic 0x7 0x1
413 9000 0 0 4 &mpic 4 1 406 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
414 407
415 /* IDSEL 0x13 AD19 */ 408 /* IDSEL 0x13 AD19 */
416 9800 0 0 1 &mpic 6 1 409 0x9800 0x0 0x0 0x1 &mpic 0x6 0x1
417 9800 0 0 2 &mpic 7 1 410 0x9800 0x0 0x0 0x2 &mpic 0x7 0x1
418 9800 0 0 3 &mpic 4 1 411 0x9800 0x0 0x0 0x3 &mpic 0x4 0x1
419 9800 0 0 4 &mpic 5 1>; 412 0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>;
420 413
421 interrupt-parent = <&mpic>; 414 interrupt-parent = <&mpic>;
422 interrupts = <18 2>; 415 interrupts = <24 2>;
423 bus-range = <0 ff>; 416 bus-range = <0 255>;
424 ranges = <02000000 0 80000000 80000000 0 20000000 417 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
425 01000000 0 00000000 e2000000 0 00800000>; 418 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
426 clock-frequency = <3f940aa>; 419 clock-frequency = <66666666>;
427 #interrupt-cells = <1>; 420 #interrupt-cells = <1>;
428 #size-cells = <2>; 421 #size-cells = <2>;
429 #address-cells = <3>; 422 #address-cells = <3>;
430 reg = <e0008000 1000>; 423 reg = <0xe0008000 0x1000>;
431 compatible = "fsl,mpc8540-pci"; 424 compatible = "fsl,mpc8540-pci";
432 device_type = "pci"; 425 device_type = "pci";
433 }; 426 };
@@ -435,39 +428,39 @@
435 /* PCI Express */ 428 /* PCI Express */
436 pci1: pcie@e000a000 { 429 pci1: pcie@e000a000 {
437 cell-index = <2>; 430 cell-index = <2>;
438 interrupt-map-mask = <f800 0 0 7>; 431 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
439 interrupt-map = < 432 interrupt-map = <
440 433
441 /* IDSEL 0x0 (PEX) */ 434 /* IDSEL 0x0 (PEX) */
442 00000 0 0 1 &mpic 0 1 435 00000 0x0 0x0 0x1 &mpic 0x0 0x1
443 00000 0 0 2 &mpic 1 1 436 00000 0x0 0x0 0x2 &mpic 0x1 0x1
444 00000 0 0 3 &mpic 2 1 437 00000 0x0 0x0 0x3 &mpic 0x2 0x1
445 00000 0 0 4 &mpic 3 1>; 438 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
446 439
447 interrupt-parent = <&mpic>; 440 interrupt-parent = <&mpic>;
448 interrupts = <1a 2>; 441 interrupts = <26 2>;
449 bus-range = <0 ff>; 442 bus-range = <0 255>;
450 ranges = <02000000 0 a0000000 a0000000 0 10000000 443 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
451 01000000 0 00000000 e2800000 0 00800000>; 444 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
452 clock-frequency = <1fca055>; 445 clock-frequency = <33333333>;
453 #interrupt-cells = <1>; 446 #interrupt-cells = <1>;
454 #size-cells = <2>; 447 #size-cells = <2>;
455 #address-cells = <3>; 448 #address-cells = <3>;
456 reg = <e000a000 1000>; 449 reg = <0xe000a000 0x1000>;
457 compatible = "fsl,mpc8548-pcie"; 450 compatible = "fsl,mpc8548-pcie";
458 device_type = "pci"; 451 device_type = "pci";
459 pcie@0 { 452 pcie@0 {
460 reg = <0 0 0 0 0>; 453 reg = <0x0 0x0 0x0 0x0 0x0>;
461 #size-cells = <2>; 454 #size-cells = <2>;
462 #address-cells = <3>; 455 #address-cells = <3>;
463 device_type = "pci"; 456 device_type = "pci";
464 ranges = <02000000 0 a0000000 457 ranges = <0x2000000 0x0 0xa0000000
465 02000000 0 a0000000 458 0x2000000 0x0 0xa0000000
466 0 10000000 459 0x0 0x10000000
467 460
468 01000000 0 00000000 461 0x1000000 0x0 0x0
469 01000000 0 00000000 462 0x1000000 0x0 0x0
470 0 00800000>; 463 0x0 0x800000>;
471 }; 464 };
472 }; 465 };
473}; 466};
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-04 13:54:34 -0500