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-rw-r--r--arch/powerpc/boot/dts/mpc8568mds.dts160
1 files changed, 90 insertions, 70 deletions
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index b1dcfbe8c1f8..54394372b12a 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -34,7 +34,6 @@
34 timebase-frequency = <0>; 34 timebase-frequency = <0>;
35 bus-frequency = <0>; 35 bus-frequency = <0>;
36 clock-frequency = <0>; 36 clock-frequency = <0>;
37 32-bit;
38 }; 37 };
39 }; 38 };
40 39
@@ -51,10 +50,9 @@
51 soc8568@e0000000 { 50 soc8568@e0000000 {
52 #address-cells = <1>; 51 #address-cells = <1>;
53 #size-cells = <1>; 52 #size-cells = <1>;
54 #interrupt-cells = <2>;
55 device_type = "soc"; 53 device_type = "soc";
56 ranges = <0 e0000000 00100000>; 54 ranges = <0 e0000000 00100000>;
57 reg = <e0000000 00100000>; 55 reg = <e0000000 00001000>;
58 bus-frequency = <0>; 56 bus-frequency = <0>;
59 57
60 memory-controller@2000 { 58 memory-controller@2000 {
@@ -74,15 +72,24 @@
74 }; 72 };
75 73
76 i2c@3000 { 74 i2c@3000 {
75 #address-cells = <1>;
76 #size-cells = <0>;
77 device_type = "i2c"; 77 device_type = "i2c";
78 compatible = "fsl-i2c"; 78 compatible = "fsl-i2c";
79 reg = <3000 100>; 79 reg = <3000 100>;
80 interrupts = <2b 2>; 80 interrupts = <2b 2>;
81 interrupt-parent = <&mpic>; 81 interrupt-parent = <&mpic>;
82 dfsrr; 82 dfsrr;
83
84 rtc@68 {
85 compatible = "dallas,ds1374";
86 reg = <68>;
87 };
83 }; 88 };
84 89
85 i2c@3100 { 90 i2c@3100 {
91 #address-cells = <1>;
92 #size-cells = <0>;
86 device_type = "i2c"; 93 device_type = "i2c";
87 compatible = "fsl-i2c"; 94 compatible = "fsl-i2c";
88 reg = <3100 100>; 95 reg = <3100 100>;
@@ -97,10 +104,10 @@
97 device_type = "mdio"; 104 device_type = "mdio";
98 compatible = "gianfar"; 105 compatible = "gianfar";
99 reg = <24520 20>; 106 reg = <24520 20>;
100 phy0: ethernet-phy@0 { 107 phy0: ethernet-phy@7 {
101 interrupt-parent = <&mpic>; 108 interrupt-parent = <&mpic>;
102 interrupts = <1 1>; 109 interrupts = <1 1>;
103 reg = <0>; 110 reg = <7>;
104 device_type = "ethernet-phy"; 111 device_type = "ethernet-phy";
105 }; 112 };
106 phy1: ethernet-phy@1 { 113 phy1: ethernet-phy@1 {
@@ -176,60 +183,6 @@
176 fsl,has-rstcr; 183 fsl,has-rstcr;
177 }; 184 };
178 185
179 pci@8000 {
180 interrupt-map-mask = <f800 0 0 7>;
181 interrupt-map = <
182 /* IDSEL 0x12 AD18 */
183 9000 0 0 1 &mpic 5 1
184 9000 0 0 2 &mpic 6 1
185 9000 0 0 3 &mpic 7 1
186 9000 0 0 4 &mpic 4 1
187
188 /* IDSEL 0x13 AD19 */
189 9800 0 0 1 &mpic 6 1
190 9800 0 0 2 &mpic 7 1
191 9800 0 0 3 &mpic 4 1
192 9800 0 0 4 &mpic 5 1>;
193
194 interrupt-parent = <&mpic>;
195 interrupts = <18 2>;
196 bus-range = <0 ff>;
197 ranges = <02000000 0 80000000 80000000 0 20000000
198 01000000 0 00000000 e2000000 0 00800000>;
199 clock-frequency = <3f940aa>;
200 #interrupt-cells = <1>;
201 #size-cells = <2>;
202 #address-cells = <3>;
203 reg = <8000 1000>;
204 compatible = "fsl,mpc8540-pci";
205 device_type = "pci";
206 };
207
208 /* PCI Express */
209 pcie@a000 {
210 interrupt-map-mask = <f800 0 0 7>;
211 interrupt-map = <
212
213 /* IDSEL 0x0 (PEX) */
214 00000 0 0 1 &mpic 0 1
215 00000 0 0 2 &mpic 1 1
216 00000 0 0 3 &mpic 2 1
217 00000 0 0 4 &mpic 3 1>;
218
219 interrupt-parent = <&mpic>;
220 interrupts = <1a 2>;
221 bus-range = <0 ff>;
222 ranges = <02000000 0 a0000000 a0000000 0 20000000
223 01000000 0 00000000 e3000000 0 08000000>;
224 clock-frequency = <1fca055>;
225 #interrupt-cells = <1>;
226 #size-cells = <2>;
227 #address-cells = <3>;
228 reg = <a000 1000>;
229 compatible = "fsl,mpc8548-pcie";
230 device_type = "pci";
231 };
232
233 serial@4600 { 186 serial@4600 {
234 device_type = "serial"; 187 device_type = "serial";
235 compatible = "ns16550"; 188 compatible = "ns16550";
@@ -258,11 +211,11 @@
258 #address-cells = <0>; 211 #address-cells = <0>;
259 #interrupt-cells = <2>; 212 #interrupt-cells = <2>;
260 reg = <40000 40000>; 213 reg = <40000 40000>;
261 built-in;
262 compatible = "chrp,open-pic"; 214 compatible = "chrp,open-pic";
263 device_type = "open-pic"; 215 device_type = "open-pic";
264 big-endian; 216 big-endian;
265 }; 217 };
218
266 par_io@e0100 { 219 par_io@e0100 {
267 reg = <e0100 100>; 220 reg = <e0100 100>;
268 device_type = "par_io"; 221 device_type = "par_io";
@@ -289,12 +242,13 @@
289 4 1a 2 0 2 0 /* RxD7 */ 242 4 1a 2 0 2 0 /* RxD7 */
290 4 0b 1 0 2 0 /* TX_EN */ 243 4 0b 1 0 2 0 /* TX_EN */
291 4 18 1 0 2 0 /* TX_ER */ 244 4 18 1 0 2 0 /* TX_ER */
292 4 0f 2 0 2 0 /* RX_DV */ 245 4 10 2 0 2 0 /* RX_DV */
293 4 1e 2 0 2 0 /* RX_ER */ 246 4 1e 2 0 2 0 /* RX_ER */
294 4 11 2 0 2 0 /* RX_CLK */ 247 4 11 2 0 2 0 /* RX_CLK */
295 4 13 1 0 2 0 /* GTX_CLK */ 248 4 13 1 0 2 0 /* GTX_CLK */
296 1 1f 2 0 3 0>; /* GTX125 */ 249 1 1f 2 0 3 0>; /* GTX125 */
297 }; 250 };
251
298 pio2: ucc_pin@02 { 252 pio2: ucc_pin@02 {
299 pio-map = < 253 pio-map = <
300 /* port pin dir open_drain assignment has_irq */ 254 /* port pin dir open_drain assignment has_irq */
@@ -380,10 +334,10 @@
380 mac-address = [ 00 00 00 00 00 00 ]; 334 mac-address = [ 00 00 00 00 00 00 ];
381 local-mac-address = [ 00 00 00 00 00 00 ]; 335 local-mac-address = [ 00 00 00 00 00 00 ];
382 rx-clock = <0>; 336 rx-clock = <0>;
383 tx-clock = <19>; 337 tx-clock = <20>;
384 phy-handle = <&qe_phy0>;
385 phy-connection-type = "gmii";
386 pio-handle = <&pio1>; 338 pio-handle = <&pio1>;
339 phy-handle = <&phy0>;
340 phy-connection-type = "rgmii-id";
387 }; 341 };
388 342
389 ucc@3000 { 343 ucc@3000 {
@@ -402,10 +356,10 @@
402 mac-address = [ 00 00 00 00 00 00 ]; 356 mac-address = [ 00 00 00 00 00 00 ];
403 local-mac-address = [ 00 00 00 00 00 00 ]; 357 local-mac-address = [ 00 00 00 00 00 00 ];
404 rx-clock = <0>; 358 rx-clock = <0>;
405 tx-clock = <14>; 359 tx-clock = <20>;
406 phy-handle = <&qe_phy1>;
407 phy-connection-type = "gmii";
408 pio-handle = <&pio2>; 360 pio-handle = <&pio2>;
361 phy-handle = <&phy1>;
362 phy-connection-type = "rgmii-id";
409 }; 363 };
410 364
411 mdio@2120 { 365 mdio@2120 {
@@ -417,10 +371,10 @@
417 371
418 /* These are the same PHYs as on 372 /* These are the same PHYs as on
419 * gianfar's MDIO bus */ 373 * gianfar's MDIO bus */
420 qe_phy0: ethernet-phy@00 { 374 qe_phy0: ethernet-phy@07 {
421 interrupt-parent = <&mpic>; 375 interrupt-parent = <&mpic>;
422 interrupts = <1 1>; 376 interrupts = <1 1>;
423 reg = <0>; 377 reg = <7>;
424 device_type = "ethernet-phy"; 378 device_type = "ethernet-phy";
425 }; 379 };
426 qe_phy1: ethernet-phy@01 { 380 qe_phy1: ethernet-phy@01 {
@@ -449,11 +403,77 @@
449 #address-cells = <0>; 403 #address-cells = <0>;
450 #interrupt-cells = <1>; 404 #interrupt-cells = <1>;
451 reg = <80 80>; 405 reg = <80 80>;
452 built-in;
453 big-endian; 406 big-endian;
454 interrupts = <2e 2 2e 2>; //high:30 low:30 407 interrupts = <2e 2 2e 2>; //high:30 low:30
455 interrupt-parent = <&mpic>; 408 interrupt-parent = <&mpic>;
456 }; 409 };
457 410
458 }; 411 };
412
413 pci@e0008000 {
414 interrupt-map-mask = <f800 0 0 7>;
415 interrupt-map = <
416 /* IDSEL 0x12 AD18 */
417 9000 0 0 1 &mpic 5 1
418 9000 0 0 2 &mpic 6 1
419 9000 0 0 3 &mpic 7 1
420 9000 0 0 4 &mpic 4 1
421
422 /* IDSEL 0x13 AD19 */
423 9800 0 0 1 &mpic 6 1
424 9800 0 0 2 &mpic 7 1
425 9800 0 0 3 &mpic 4 1
426 9800 0 0 4 &mpic 5 1>;
427
428 interrupt-parent = <&mpic>;
429 interrupts = <18 2>;
430 bus-range = <0 ff>;
431 ranges = <02000000 0 80000000 80000000 0 20000000
432 01000000 0 00000000 e2000000 0 00800000>;
433 clock-frequency = <3f940aa>;
434 #interrupt-cells = <1>;
435 #size-cells = <2>;
436 #address-cells = <3>;
437 reg = <e0008000 1000>;
438 compatible = "fsl,mpc8540-pci";
439 device_type = "pci";
440 };
441
442 /* PCI Express */
443 pcie@e000a000 {
444 interrupt-map-mask = <f800 0 0 7>;
445 interrupt-map = <
446
447 /* IDSEL 0x0 (PEX) */
448 00000 0 0 1 &mpic 0 1
449 00000 0 0 2 &mpic 1 1
450 00000 0 0 3 &mpic 2 1
451 00000 0 0 4 &mpic 3 1>;
452
453 interrupt-parent = <&mpic>;
454 interrupts = <1a 2>;
455 bus-range = <0 ff>;
456 ranges = <02000000 0 a0000000 a0000000 0 10000000
457 01000000 0 00000000 e2800000 0 00800000>;
458 clock-frequency = <1fca055>;
459 #interrupt-cells = <1>;
460 #size-cells = <2>;
461 #address-cells = <3>;
462 reg = <e000a000 1000>;
463 compatible = "fsl,mpc8548-pcie";
464 device_type = "pci";
465 pcie@0 {
466 reg = <0 0 0 0 0>;
467 #size-cells = <2>;
468 #address-cells = <3>;
469 device_type = "pci";
470 ranges = <02000000 0 a0000000
471 02000000 0 a0000000
472 0 10000000
473
474 01000000 0 00000000
475 01000000 0 00000000
476 0 00800000>;
477 };
478 };
459}; 479};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-17 17:58:55 -0500