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-rw-r--r--arch/powerpc/boot/dts/mpc8555cds.dts228
1 files changed, 129 insertions, 99 deletions
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index c3c888252121..57029cca32b2 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -30,7 +30,6 @@
30 timebase-frequency = <0>; // 33 MHz, from uboot 30 timebase-frequency = <0>; // 33 MHz, from uboot
31 bus-frequency = <0>; // 166 MHz 31 bus-frequency = <0>; // 166 MHz
32 clock-frequency = <0>; // 825 MHz, from uboot 32 clock-frequency = <0>; // 825 MHz, from uboot
33 32-bit;
34 }; 33 };
35 }; 34 };
36 35
@@ -42,10 +41,9 @@
42 soc8555@e0000000 { 41 soc8555@e0000000 {
43 #address-cells = <1>; 42 #address-cells = <1>;
44 #size-cells = <1>; 43 #size-cells = <1>;
45 #interrupt-cells = <2>;
46 device_type = "soc"; 44 device_type = "soc";
47 ranges = <0 e0000000 00100000>; 45 ranges = <0 e0000000 00100000>;
48 reg = <e0000000 00100000>; // CCSRBAR 1M 46 reg = <e0000000 00001000>; // CCSRBAR 1M
49 bus-frequency = <0>; 47 bus-frequency = <0>;
50 48
51 memory-controller@2000 { 49 memory-controller@2000 {
@@ -137,113 +135,145 @@
137 interrupt-parent = <&mpic>; 135 interrupt-parent = <&mpic>;
138 }; 136 };
139 137
140 pci1: pci@8000 { 138 mpic: pic@40000 {
141 interrupt-map-mask = <1f800 0 0 7>; 139 clock-frequency = <0>;
142 interrupt-map = < 140 interrupt-controller;
143 141 #address-cells = <0>;
144 /* IDSEL 0x10 */ 142 #interrupt-cells = <2>;
145 08000 0 0 1 &mpic 0 1 143 reg = <40000 40000>;
146 08000 0 0 2 &mpic 1 1 144 compatible = "chrp,open-pic";
147 08000 0 0 3 &mpic 2 1 145 device_type = "open-pic";
148 08000 0 0 4 &mpic 3 1 146 big-endian;
149 147 };
150 /* IDSEL 0x11 */ 148
151 08800 0 0 1 &mpic 0 1 149 cpm@919c0 {
152 08800 0 0 2 &mpic 1 1 150 #address-cells = <1>;
153 08800 0 0 3 &mpic 2 1 151 #size-cells = <1>;
154 08800 0 0 4 &mpic 3 1 152 compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
155 153 reg = <919c0 30>;
156 /* IDSEL 0x12 (Slot 1) */ 154 ranges;
157 09000 0 0 1 &mpic 0 1 155
158 09000 0 0 2 &mpic 1 1 156 muram@80000 {
159 09000 0 0 3 &mpic 2 1 157 #address-cells = <1>;
160 09000 0 0 4 &mpic 3 1 158 #size-cells = <1>;
161 159 ranges = <0 80000 10000>;
162 /* IDSEL 0x13 (Slot 2) */ 160
163 09800 0 0 1 &mpic 1 1 161 data@0 {
164 09800 0 0 2 &mpic 2 1 162 compatible = "fsl,cpm-muram-data";
165 09800 0 0 3 &mpic 3 1 163 reg = <0 2000 9000 1000>;
166 09800 0 0 4 &mpic 0 1 164 };
167 165 };
168 /* IDSEL 0x14 (Slot 3) */ 166
169 0a000 0 0 1 &mpic 2 1 167 brg@919f0 {
170 0a000 0 0 2 &mpic 3 1 168 compatible = "fsl,mpc8555-brg",
171 0a000 0 0 3 &mpic 0 1 169 "fsl,cpm2-brg",
172 0a000 0 0 4 &mpic 1 1 170 "fsl,cpm-brg";
173 171 reg = <919f0 10 915f0 10>;
174 /* IDSEL 0x15 (Slot 4) */ 172 };
175 0a800 0 0 1 &mpic 3 1 173
176 0a800 0 0 2 &mpic 0 1 174 cpmpic: pic@90c00 {
177 0a800 0 0 3 &mpic 1 1
178 0a800 0 0 4 &mpic 2 1
179
180 /* Bus 1 (Tundra Bridge) */
181 /* IDSEL 0x12 (ISA bridge) */
182 19000 0 0 1 &mpic 0 1
183 19000 0 0 2 &mpic 1 1
184 19000 0 0 3 &mpic 2 1
185 19000 0 0 4 &mpic 3 1>;
186 interrupt-parent = <&mpic>;
187 interrupts = <18 2>;
188 bus-range = <0 0>;
189 ranges = <02000000 0 80000000 80000000 0 20000000
190 01000000 0 00000000 e2000000 0 00100000>;
191 clock-frequency = <3f940aa>;
192 #interrupt-cells = <1>;
193 #size-cells = <2>;
194 #address-cells = <3>;
195 reg = <8000 1000>;
196 compatible = "fsl,mpc8540-pci";
197 device_type = "pci";
198
199 i8259@19000 {
200 clock-frequency = <0>;
201 interrupt-controller; 175 interrupt-controller;
202 device_type = "interrupt-controller";
203 reg = <19000 0 0 0 1>;
204 #address-cells = <0>; 176 #address-cells = <0>;
205 #interrupt-cells = <2>; 177 #interrupt-cells = <2>;
206 built-in; 178 interrupts = <2e 2>;
207 compatible = "chrp,iic"; 179 interrupt-parent = <&mpic>;
208 big-endian; 180 reg = <90c00 80>;
209 interrupts = <1>; 181 compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
210 interrupt-parent = <&pci1>;
211 }; 182 };
212 }; 183 };
184 };
213 185
214 pci@9000 { 186 pci1: pci@e0008000 {
215 interrupt-map-mask = <f800 0 0 7>; 187 interrupt-map-mask = <1f800 0 0 7>;
216 interrupt-map = < 188 interrupt-map = <
217 189
218 /* IDSEL 0x15 */ 190 /* IDSEL 0x10 */
219 a800 0 0 1 &mpic b 1 191 08000 0 0 1 &mpic 0 1
220 a800 0 0 2 &mpic b 1 192 08000 0 0 2 &mpic 1 1
221 a800 0 0 3 &mpic b 1 193 08000 0 0 3 &mpic 2 1
222 a800 0 0 4 &mpic b 1>; 194 08000 0 0 4 &mpic 3 1
223 interrupt-parent = <&mpic>;
224 interrupts = <19 2>;
225 bus-range = <0 0>;
226 ranges = <02000000 0 a0000000 a0000000 0 20000000
227 01000000 0 00000000 e3000000 0 00100000>;
228 clock-frequency = <3f940aa>;
229 #interrupt-cells = <1>;
230 #size-cells = <2>;
231 #address-cells = <3>;
232 reg = <9000 1000>;
233 compatible = "fsl,mpc8540-pci";
234 device_type = "pci";
235 };
236 195
237 mpic: pic@40000 { 196 /* IDSEL 0x11 */
238 clock-frequency = <0>; 197 08800 0 0 1 &mpic 0 1
198 08800 0 0 2 &mpic 1 1
199 08800 0 0 3 &mpic 2 1
200 08800 0 0 4 &mpic 3 1
201
202 /* IDSEL 0x12 (Slot 1) */
203 09000 0 0 1 &mpic 0 1
204 09000 0 0 2 &mpic 1 1
205 09000 0 0 3 &mpic 2 1
206 09000 0 0 4 &mpic 3 1
207
208 /* IDSEL 0x13 (Slot 2) */
209 09800 0 0 1 &mpic 1 1
210 09800 0 0 2 &mpic 2 1
211 09800 0 0 3 &mpic 3 1
212 09800 0 0 4 &mpic 0 1
213
214 /* IDSEL 0x14 (Slot 3) */
215 0a000 0 0 1 &mpic 2 1
216 0a000 0 0 2 &mpic 3 1
217 0a000 0 0 3 &mpic 0 1
218 0a000 0 0 4 &mpic 1 1
219
220 /* IDSEL 0x15 (Slot 4) */
221 0a800 0 0 1 &mpic 3 1
222 0a800 0 0 2 &mpic 0 1
223 0a800 0 0 3 &mpic 1 1
224 0a800 0 0 4 &mpic 2 1
225
226 /* Bus 1 (Tundra Bridge) */
227 /* IDSEL 0x12 (ISA bridge) */
228 19000 0 0 1 &mpic 0 1
229 19000 0 0 2 &mpic 1 1
230 19000 0 0 3 &mpic 2 1
231 19000 0 0 4 &mpic 3 1>;
232 interrupt-parent = <&mpic>;
233 interrupts = <18 2>;
234 bus-range = <0 0>;
235 ranges = <02000000 0 80000000 80000000 0 20000000
236 01000000 0 00000000 e2000000 0 00100000>;
237 clock-frequency = <3f940aa>;
238 #interrupt-cells = <1>;
239 #size-cells = <2>;
240 #address-cells = <3>;
241 reg = <e0008000 1000>;
242 compatible = "fsl,mpc8540-pci";
243 device_type = "pci";
244
245 i8259@19000 {
239 interrupt-controller; 246 interrupt-controller;
247 device_type = "interrupt-controller";
248 reg = <19000 0 0 0 1>;
240 #address-cells = <0>; 249 #address-cells = <0>;
241 #interrupt-cells = <2>; 250 #interrupt-cells = <2>;
242 reg = <40000 40000>; 251 compatible = "chrp,iic";
243 built-in; 252 interrupts = <1>;
244 compatible = "chrp,open-pic"; 253 interrupt-parent = <&pci1>;
245 device_type = "open-pic";
246 big-endian;
247 }; 254 };
248 }; 255 };
256
257 pci@e0009000 {
258 interrupt-map-mask = <f800 0 0 7>;
259 interrupt-map = <
260
261 /* IDSEL 0x15 */
262 a800 0 0 1 &mpic b 1
263 a800 0 0 2 &mpic b 1
264 a800 0 0 3 &mpic b 1
265 a800 0 0 4 &mpic b 1>;
266 interrupt-parent = <&mpic>;
267 interrupts = <19 2>;
268 bus-range = <0 0>;
269 ranges = <02000000 0 a0000000 a0000000 0 20000000
270 01000000 0 00000000 e3000000 0 00100000>;
271 clock-frequency = <3f940aa>;
272 #interrupt-cells = <1>;
273 #size-cells = <2>;
274 #address-cells = <3>;
275 reg = <e0009000 1000>;
276 compatible = "fsl,mpc8540-pci";
277 device_type = "pci";
278 };
249}; 279};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-21 02:29:57 -0500