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Diffstat (limited to 'arch/powerpc/boot/dts/mpc8548cds.dts')
-rw-r--r--arch/powerpc/boot/dts/mpc8548cds.dts8
1 files changed, 2 insertions, 6 deletions
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 4173af387c63..a17a5572fb73 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -20,10 +20,8 @@
20 aliases { 20 aliases {
21 ethernet0 = &enet0; 21 ethernet0 = &enet0;
22 ethernet1 = &enet1; 22 ethernet1 = &enet1;
23/*
24 ethernet2 = &enet2; 23 ethernet2 = &enet2;
25 ethernet3 = &enet3; 24 ethernet3 = &enet3;
26*/
27 serial0 = &serial0; 25 serial0 = &serial0;
28 serial1 = &serial1; 26 serial1 = &serial1;
29 pci0 = &pci0; 27 pci0 = &pci0;
@@ -76,14 +74,14 @@
76 }; 74 };
77 75
78 memory-controller@2000 { 76 memory-controller@2000 {
79 compatible = "fsl,8548-memory-controller"; 77 compatible = "fsl,mpc8548-memory-controller";
80 reg = <0x2000 0x1000>; 78 reg = <0x2000 0x1000>;
81 interrupt-parent = <&mpic>; 79 interrupt-parent = <&mpic>;
82 interrupts = <18 2>; 80 interrupts = <18 2>;
83 }; 81 };
84 82
85 L2: l2-cache-controller@20000 { 83 L2: l2-cache-controller@20000 {
86 compatible = "fsl,8548-l2-cache-controller"; 84 compatible = "fsl,mpc8548-l2-cache-controller";
87 reg = <0x20000 0x1000>; 85 reg = <0x20000 0x1000>;
88 cache-line-size = <32>; // 32 bytes 86 cache-line-size = <32>; // 32 bytes
89 cache-size = <0x80000>; // L2, 512K 87 cache-size = <0x80000>; // L2, 512K
@@ -254,7 +252,6 @@
254 }; 252 };
255 }; 253 };
256 254
257/* eTSEC 3/4 are currently broken
258 enet2: ethernet@26000 { 255 enet2: ethernet@26000 {
259 #address-cells = <1>; 256 #address-cells = <1>;
260 #size-cells = <1>; 257 #size-cells = <1>;
@@ -310,7 +307,6 @@
310 }; 307 };
311 }; 308 };
312 }; 309 };
313 */
314 310
315 serial0: serial@4500 { 311 serial0: serial@4500 {
316 cell-index = <0>; 312 cell-index = <0>;