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-rw-r--r--arch/powerpc/boot/dts/mpc8548cds.dts404
1 files changed, 203 insertions, 201 deletions
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index d215d21fff42..69ca5025d972 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -30,7 +30,6 @@
30 timebase-frequency = <0>; // 33 MHz, from uboot 30 timebase-frequency = <0>; // 33 MHz, from uboot
31 bus-frequency = <0>; // 166 MHz 31 bus-frequency = <0>; // 166 MHz
32 clock-frequency = <0>; // 825 MHz, from uboot 32 clock-frequency = <0>; // 825 MHz, from uboot
33 32-bit;
34 }; 33 };
35 }; 34 };
36 35
@@ -42,15 +41,8 @@
42 soc8548@e0000000 { 41 soc8548@e0000000 {
43 #address-cells = <1>; 42 #address-cells = <1>;
44 #size-cells = <1>; 43 #size-cells = <1>;
45 #interrupt-cells = <2>;
46 device_type = "soc"; 44 device_type = "soc";
47 ranges = <00001000 e0001000 000ff000 45 ranges = <00000000 e0000000 00100000>;
48 80000000 80000000 10000000
49 e2000000 e2000000 00800000
50 90000000 90000000 10000000
51 e2800000 e2800000 00800000
52 a0000000 a0000000 20000000
53 e3000000 e3000000 01000000>;
54 reg = <e0000000 00001000>; // CCSRBAR 46 reg = <e0000000 00001000>; // CCSRBAR
55 bus-frequency = <0>; 47 bus-frequency = <0>;
56 48
@@ -189,215 +181,225 @@
189 fsl,has-rstcr; 181 fsl,has-rstcr;
190 }; 182 };
191 183
192 pci@8000 { 184 mpic: pic@40000 {
185 clock-frequency = <0>;
186 interrupt-controller;
187 #address-cells = <0>;
188 #interrupt-cells = <2>;
189 reg = <40000 40000>;
190 compatible = "chrp,open-pic";
191 device_type = "open-pic";
192 big-endian;
193 };
194 };
195
196 pci@e0008000 {
197 interrupt-map-mask = <f800 0 0 7>;
198 interrupt-map = <
199 /* IDSEL 0x4 (PCIX Slot 2) */
200 02000 0 0 1 &mpic 0 1
201 02000 0 0 2 &mpic 1 1
202 02000 0 0 3 &mpic 2 1
203 02000 0 0 4 &mpic 3 1
204
205 /* IDSEL 0x5 (PCIX Slot 3) */
206 02800 0 0 1 &mpic 1 1
207 02800 0 0 2 &mpic 2 1
208 02800 0 0 3 &mpic 3 1
209 02800 0 0 4 &mpic 0 1
210
211 /* IDSEL 0x6 (PCIX Slot 4) */
212 03000 0 0 1 &mpic 2 1
213 03000 0 0 2 &mpic 3 1
214 03000 0 0 3 &mpic 0 1
215 03000 0 0 4 &mpic 1 1
216
217 /* IDSEL 0x8 (PCIX Slot 5) */
218 04000 0 0 1 &mpic 0 1
219 04000 0 0 2 &mpic 1 1
220 04000 0 0 3 &mpic 2 1
221 04000 0 0 4 &mpic 3 1
222
223 /* IDSEL 0xC (Tsi310 bridge) */
224 06000 0 0 1 &mpic 0 1
225 06000 0 0 2 &mpic 1 1
226 06000 0 0 3 &mpic 2 1
227 06000 0 0 4 &mpic 3 1
228
229 /* IDSEL 0x14 (Slot 2) */
230 0a000 0 0 1 &mpic 0 1
231 0a000 0 0 2 &mpic 1 1
232 0a000 0 0 3 &mpic 2 1
233 0a000 0 0 4 &mpic 3 1
234
235 /* IDSEL 0x15 (Slot 3) */
236 0a800 0 0 1 &mpic 1 1
237 0a800 0 0 2 &mpic 2 1
238 0a800 0 0 3 &mpic 3 1
239 0a800 0 0 4 &mpic 0 1
240
241 /* IDSEL 0x16 (Slot 4) */
242 0b000 0 0 1 &mpic 2 1
243 0b000 0 0 2 &mpic 3 1
244 0b000 0 0 3 &mpic 0 1
245 0b000 0 0 4 &mpic 1 1
246
247 /* IDSEL 0x18 (Slot 5) */
248 0c000 0 0 1 &mpic 0 1
249 0c000 0 0 2 &mpic 1 1
250 0c000 0 0 3 &mpic 2 1
251 0c000 0 0 4 &mpic 3 1
252
253 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
254 0E000 0 0 1 &mpic 0 1
255 0E000 0 0 2 &mpic 1 1
256 0E000 0 0 3 &mpic 2 1
257 0E000 0 0 4 &mpic 3 1>;
258
259 interrupt-parent = <&mpic>;
260 interrupts = <18 2>;
261 bus-range = <0 0>;
262 ranges = <02000000 0 80000000 80000000 0 10000000
263 01000000 0 00000000 e2000000 0 00800000>;
264 clock-frequency = <3f940aa>;
265 #interrupt-cells = <1>;
266 #size-cells = <2>;
267 #address-cells = <3>;
268 reg = <e0008000 1000>;
269 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
270 device_type = "pci";
271
272 pci_bridge@1c {
193 interrupt-map-mask = <f800 0 0 7>; 273 interrupt-map-mask = <f800 0 0 7>;
194 interrupt-map = < 274 interrupt-map = <
195 /* IDSEL 0x4 (PCIX Slot 2) */
196 02000 0 0 1 &mpic 0 1
197 02000 0 0 2 &mpic 1 1
198 02000 0 0 3 &mpic 2 1
199 02000 0 0 4 &mpic 3 1
200
201 /* IDSEL 0x5 (PCIX Slot 3) */
202 02800 0 0 1 &mpic 1 1
203 02800 0 0 2 &mpic 2 1
204 02800 0 0 3 &mpic 3 1
205 02800 0 0 4 &mpic 0 1
206
207 /* IDSEL 0x6 (PCIX Slot 4) */
208 03000 0 0 1 &mpic 2 1
209 03000 0 0 2 &mpic 3 1
210 03000 0 0 3 &mpic 0 1
211 03000 0 0 4 &mpic 1 1
212
213 /* IDSEL 0x8 (PCIX Slot 5) */
214 04000 0 0 1 &mpic 0 1
215 04000 0 0 2 &mpic 1 1
216 04000 0 0 3 &mpic 2 1
217 04000 0 0 4 &mpic 3 1
218
219 /* IDSEL 0xC (Tsi310 bridge) */
220 06000 0 0 1 &mpic 0 1
221 06000 0 0 2 &mpic 1 1
222 06000 0 0 3 &mpic 2 1
223 06000 0 0 4 &mpic 3 1
224
225 /* IDSEL 0x14 (Slot 2) */
226 0a000 0 0 1 &mpic 0 1
227 0a000 0 0 2 &mpic 1 1
228 0a000 0 0 3 &mpic 2 1
229 0a000 0 0 4 &mpic 3 1
230
231 /* IDSEL 0x15 (Slot 3) */
232 0a800 0 0 1 &mpic 1 1
233 0a800 0 0 2 &mpic 2 1
234 0a800 0 0 3 &mpic 3 1
235 0a800 0 0 4 &mpic 0 1
236
237 /* IDSEL 0x16 (Slot 4) */
238 0b000 0 0 1 &mpic 2 1
239 0b000 0 0 2 &mpic 3 1
240 0b000 0 0 3 &mpic 0 1
241 0b000 0 0 4 &mpic 1 1
242
243 /* IDSEL 0x18 (Slot 5) */
244 0c000 0 0 1 &mpic 0 1
245 0c000 0 0 2 &mpic 1 1
246 0c000 0 0 3 &mpic 2 1
247 0c000 0 0 4 &mpic 3 1
248
249 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
250 0E000 0 0 1 &mpic 0 1
251 0E000 0 0 2 &mpic 1 1
252 0E000 0 0 3 &mpic 2 1
253 0E000 0 0 4 &mpic 3 1>;
254 275
255 interrupt-parent = <&mpic>; 276 /* IDSEL 0x00 (PrPMC Site) */
256 interrupts = <18 2>; 277 0000 0 0 1 &mpic 0 1
257 bus-range = <0 0>; 278 0000 0 0 2 &mpic 1 1
258 ranges = <02000000 0 80000000 80000000 0 10000000 279 0000 0 0 3 &mpic 2 1
259 01000000 0 00000000 e2000000 0 00800000>; 280 0000 0 0 4 &mpic 3 1
260 clock-frequency = <3f940aa>; 281
282 /* IDSEL 0x04 (VIA chip) */
283 2000 0 0 1 &mpic 0 1
284 2000 0 0 2 &mpic 1 1
285 2000 0 0 3 &mpic 2 1
286 2000 0 0 4 &mpic 3 1
287
288 /* IDSEL 0x05 (8139) */
289 2800 0 0 1 &mpic 1 1
290
291 /* IDSEL 0x06 (Slot 6) */
292 3000 0 0 1 &mpic 2 1
293 3000 0 0 2 &mpic 3 1
294 3000 0 0 3 &mpic 0 1
295 3000 0 0 4 &mpic 1 1
296
297 /* IDESL 0x07 (Slot 7) */
298 3800 0 0 1 &mpic 3 1
299 3800 0 0 2 &mpic 0 1
300 3800 0 0 3 &mpic 1 1
301 3800 0 0 4 &mpic 2 1>;
302
303 reg = <e000 0 0 0 0>;
261 #interrupt-cells = <1>; 304 #interrupt-cells = <1>;
262 #size-cells = <2>; 305 #size-cells = <2>;
263 #address-cells = <3>; 306 #address-cells = <3>;
264 reg = <8000 1000>; 307 ranges = <02000000 0 80000000
265 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 308 02000000 0 80000000
266 device_type = "pci"; 309 0 20000000
310 01000000 0 00000000
311 01000000 0 00000000
312 0 00080000>;
313 clock-frequency = <1fca055>;
267 314
268 pci_bridge@1c { 315 isa@4 {
269 interrupt-map-mask = <f800 0 0 7>; 316 device_type = "isa";
270 interrupt-map = < 317 #interrupt-cells = <2>;
271 318 #size-cells = <1>;
272 /* IDSEL 0x00 (PrPMC Site) */ 319 #address-cells = <2>;
273 0000 0 0 1 &mpic 0 1 320 reg = <2000 0 0 0 0>;
274 0000 0 0 2 &mpic 1 1 321 ranges = <1 0 01000000 0 0 00001000>;
275 0000 0 0 3 &mpic 2 1 322 interrupt-parent = <&i8259>;
276 0000 0 0 4 &mpic 3 1 323
277 324 i8259: interrupt-controller@20 {
278 /* IDSEL 0x04 (VIA chip) */ 325 interrupt-controller;
279 2000 0 0 1 &mpic 0 1 326 device_type = "interrupt-controller";
280 2000 0 0 2 &mpic 1 1 327 reg = <1 20 2
281 2000 0 0 3 &mpic 2 1 328 1 a0 2
282 2000 0 0 4 &mpic 3 1 329 1 4d0 2>;
283 330 #address-cells = <0>;
284 /* IDSEL 0x05 (8139) */
285 2800 0 0 1 &mpic 1 1
286
287 /* IDSEL 0x06 (Slot 6) */
288 3000 0 0 1 &mpic 2 1
289 3000 0 0 2 &mpic 3 1
290 3000 0 0 3 &mpic 0 1
291 3000 0 0 4 &mpic 1 1
292
293 /* IDESL 0x07 (Slot 7) */
294 3800 0 0 1 &mpic 3 1
295 3800 0 0 2 &mpic 0 1
296 3800 0 0 3 &mpic 1 1
297 3800 0 0 4 &mpic 2 1>;
298
299 reg = <e000 0 0 0 0>;
300 #interrupt-cells = <1>;
301 #size-cells = <2>;
302 #address-cells = <3>;
303 ranges = <02000000 0 80000000
304 02000000 0 80000000
305 0 20000000
306 01000000 0 00000000
307 01000000 0 00000000
308 0 00080000>;
309 clock-frequency = <1fca055>;
310
311 isa@4 {
312 device_type = "isa";
313 #interrupt-cells = <2>; 331 #interrupt-cells = <2>;
314 #size-cells = <1>; 332 compatible = "chrp,iic";
315 #address-cells = <2>; 333 interrupts = <0 1>;
316 reg = <2000 0 0 0 0>; 334 interrupt-parent = <&mpic>;
317 ranges = <1 0 01000000 0 0 00001000>;
318 interrupt-parent = <&i8259>;
319
320 i8259: interrupt-controller@20 {
321 clock-frequency = <0>;
322 interrupt-controller;
323 device_type = "interrupt-controller";
324 reg = <1 20 2
325 1 a0 2
326 1 4d0 2>;
327 #address-cells = <0>;
328 #interrupt-cells = <2>;
329 built-in;
330 compatible = "chrp,iic";
331 interrupts = <0 1>;
332 interrupt-parent = <&mpic>;
333 };
334
335 rtc@70 {
336 compatible = "pnpPNP,b00";
337 reg = <1 70 2>;
338 };
339 }; 335 };
340 };
341 };
342 336
343 pci@9000 { 337 rtc@70 {
344 interrupt-map-mask = <f800 0 0 7>; 338 compatible = "pnpPNP,b00";
345 interrupt-map = < 339 reg = <1 70 2>;
346 340 };
347 /* IDSEL 0x15 */ 341 };
348 a800 0 0 1 &mpic b 1
349 a800 0 0 2 &mpic 1 1
350 a800 0 0 3 &mpic 2 1
351 a800 0 0 4 &mpic 3 1>;
352
353 interrupt-parent = <&mpic>;
354 interrupts = <19 2>;
355 bus-range = <0 0>;
356 ranges = <02000000 0 90000000 90000000 0 10000000
357 01000000 0 00000000 e2800000 0 00800000>;
358 clock-frequency = <3f940aa>;
359 #interrupt-cells = <1>;
360 #size-cells = <2>;
361 #address-cells = <3>;
362 reg = <9000 1000>;
363 compatible = "fsl,mpc8540-pci";
364 device_type = "pci";
365 }; 342 };
366 /* PCI Express */ 343 };
367 pcie@a000 {
368 interrupt-map-mask = <f800 0 0 7>;
369 interrupt-map = <
370 344
371 /* IDSEL 0x0 (PEX) */ 345 pci@e0009000 {
372 00000 0 0 1 &mpic 0 1 346 interrupt-map-mask = <f800 0 0 7>;
373 00000 0 0 2 &mpic 1 1 347 interrupt-map = <
374 00000 0 0 3 &mpic 2 1 348
375 00000 0 0 4 &mpic 3 1>; 349 /* IDSEL 0x15 */
350 a800 0 0 1 &mpic b 1
351 a800 0 0 2 &mpic 1 1
352 a800 0 0 3 &mpic 2 1
353 a800 0 0 4 &mpic 3 1>;
354
355 interrupt-parent = <&mpic>;
356 interrupts = <19 2>;
357 bus-range = <0 0>;
358 ranges = <02000000 0 90000000 90000000 0 10000000
359 01000000 0 00000000 e2800000 0 00800000>;
360 clock-frequency = <3f940aa>;
361 #interrupt-cells = <1>;
362 #size-cells = <2>;
363 #address-cells = <3>;
364 reg = <e0009000 1000>;
365 compatible = "fsl,mpc8540-pci";
366 device_type = "pci";
367 };
376 368
377 interrupt-parent = <&mpic>; 369 pcie@e000a000 {
378 interrupts = <1a 2>; 370 interrupt-map-mask = <f800 0 0 7>;
379 bus-range = <0 ff>; 371 interrupt-map = <
380 ranges = <02000000 0 a0000000 a0000000 0 20000000 372
381 01000000 0 00000000 e3000000 0 08000000>; 373 /* IDSEL 0x0 (PEX) */
382 clock-frequency = <1fca055>; 374 00000 0 0 1 &mpic 0 1
383 #interrupt-cells = <1>; 375 00000 0 0 2 &mpic 1 1
376 00000 0 0 3 &mpic 2 1
377 00000 0 0 4 &mpic 3 1>;
378
379 interrupt-parent = <&mpic>;
380 interrupts = <1a 2>;
381 bus-range = <0 ff>;
382 ranges = <02000000 0 a0000000 a0000000 0 20000000
383 01000000 0 00000000 e3000000 0 08000000>;
384 clock-frequency = <1fca055>;
385 #interrupt-cells = <1>;
386 #size-cells = <2>;
387 #address-cells = <3>;
388 reg = <e000a000 1000>;
389 compatible = "fsl,mpc8548-pcie";
390 device_type = "pci";
391 pcie@0 {
392 reg = <0 0 0 0 0>;
384 #size-cells = <2>; 393 #size-cells = <2>;
385 #address-cells = <3>; 394 #address-cells = <3>;
386 reg = <a000 1000>;
387 compatible = "fsl,mpc8548-pcie";
388 device_type = "pci"; 395 device_type = "pci";
389 }; 396 ranges = <02000000 0 a0000000
397 02000000 0 a0000000
398 0 20000000
390 399
391 mpic: pic@40000 { 400 01000000 0 00000000
392 clock-frequency = <0>; 401 01000000 0 00000000
393 interrupt-controller; 402 0 08000000>;
394 #address-cells = <0>;
395 #interrupt-cells = <2>;
396 reg = <40000 40000>;
397 built-in;
398 compatible = "chrp,open-pic";
399 device_type = "open-pic";
400 big-endian;
401 }; 403 };
402 }; 404 };
403}; 405};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-01 19:12:43 -0500