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Diffstat (limited to 'arch/powerpc/boot/dts/mpc8548cds.dts')
-rw-r--r--arch/powerpc/boot/dts/mpc8548cds.dts108
1 files changed, 57 insertions, 51 deletions
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index ad96381033c0..9d0b84b66cd4 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -52,7 +52,7 @@
52 compatible = "fsl,8548-memory-controller"; 52 compatible = "fsl,8548-memory-controller";
53 reg = <2000 1000>; 53 reg = <2000 1000>;
54 interrupt-parent = <&mpic>; 54 interrupt-parent = <&mpic>;
55 interrupts = <2 2>; 55 interrupts = <12 2>;
56 }; 56 };
57 57
58 l2-cache-controller@20000 { 58 l2-cache-controller@20000 {
@@ -61,14 +61,14 @@
61 cache-line-size = <20>; // 32 bytes 61 cache-line-size = <20>; // 32 bytes
62 cache-size = <80000>; // L2, 512K 62 cache-size = <80000>; // L2, 512K
63 interrupt-parent = <&mpic>; 63 interrupt-parent = <&mpic>;
64 interrupts = <0 2>; 64 interrupts = <10 2>;
65 }; 65 };
66 66
67 i2c@3000 { 67 i2c@3000 {
68 device_type = "i2c"; 68 device_type = "i2c";
69 compatible = "fsl-i2c"; 69 compatible = "fsl-i2c";
70 reg = <3000 100>; 70 reg = <3000 100>;
71 interrupts = <1b 2>; 71 interrupts = <2b 2>;
72 interrupt-parent = <&mpic>; 72 interrupt-parent = <&mpic>;
73 dfsrr; 73 dfsrr;
74 }; 74 };
@@ -81,25 +81,25 @@
81 reg = <24520 20>; 81 reg = <24520 20>;
82 phy0: ethernet-phy@0 { 82 phy0: ethernet-phy@0 {
83 interrupt-parent = <&mpic>; 83 interrupt-parent = <&mpic>;
84 interrupts = <35 0>; 84 interrupts = <5 1>;
85 reg = <0>; 85 reg = <0>;
86 device_type = "ethernet-phy"; 86 device_type = "ethernet-phy";
87 }; 87 };
88 phy1: ethernet-phy@1 { 88 phy1: ethernet-phy@1 {
89 interrupt-parent = <&mpic>; 89 interrupt-parent = <&mpic>;
90 interrupts = <35 0>; 90 interrupts = <5 1>;
91 reg = <1>; 91 reg = <1>;
92 device_type = "ethernet-phy"; 92 device_type = "ethernet-phy";
93 }; 93 };
94 phy2: ethernet-phy@2 { 94 phy2: ethernet-phy@2 {
95 interrupt-parent = <&mpic>; 95 interrupt-parent = <&mpic>;
96 interrupts = <35 0>; 96 interrupts = <5 1>;
97 reg = <2>; 97 reg = <2>;
98 device_type = "ethernet-phy"; 98 device_type = "ethernet-phy";
99 }; 99 };
100 phy3: ethernet-phy@3 { 100 phy3: ethernet-phy@3 {
101 interrupt-parent = <&mpic>; 101 interrupt-parent = <&mpic>;
102 interrupts = <35 0>; 102 interrupts = <5 1>;
103 reg = <3>; 103 reg = <3>;
104 device_type = "ethernet-phy"; 104 device_type = "ethernet-phy";
105 }; 105 };
@@ -112,8 +112,8 @@
112 model = "eTSEC"; 112 model = "eTSEC";
113 compatible = "gianfar"; 113 compatible = "gianfar";
114 reg = <24000 1000>; 114 reg = <24000 1000>;
115 local-mac-address = [ 00 E0 0C 00 73 00 ]; 115 local-mac-address = [ 00 00 00 00 00 00 ];
116 interrupts = <d 2 e 2 12 2>; 116 interrupts = <1d 2 1e 2 22 2>;
117 interrupt-parent = <&mpic>; 117 interrupt-parent = <&mpic>;
118 phy-handle = <&phy0>; 118 phy-handle = <&phy0>;
119 }; 119 };
@@ -125,8 +125,8 @@
125 model = "eTSEC"; 125 model = "eTSEC";
126 compatible = "gianfar"; 126 compatible = "gianfar";
127 reg = <25000 1000>; 127 reg = <25000 1000>;
128 local-mac-address = [ 00 E0 0C 00 73 01 ]; 128 local-mac-address = [ 00 00 00 00 00 00 ];
129 interrupts = <13 2 14 2 18 2>; 129 interrupts = <23 2 24 2 28 2>;
130 interrupt-parent = <&mpic>; 130 interrupt-parent = <&mpic>;
131 phy-handle = <&phy1>; 131 phy-handle = <&phy1>;
132 }; 132 };
@@ -139,8 +139,8 @@
139 model = "eTSEC"; 139 model = "eTSEC";
140 compatible = "gianfar"; 140 compatible = "gianfar";
141 reg = <26000 1000>; 141 reg = <26000 1000>;
142 local-mac-address = [ 00 E0 0C 00 73 02 ]; 142 local-mac-address = [ 00 00 00 00 00 00 ];
143 interrupts = <f 2 10 2 11 2>; 143 interrupts = <1f 2 20 2 21 2>;
144 interrupt-parent = <&mpic>; 144 interrupt-parent = <&mpic>;
145 phy-handle = <&phy2>; 145 phy-handle = <&phy2>;
146 }; 146 };
@@ -152,8 +152,8 @@
152 model = "eTSEC"; 152 model = "eTSEC";
153 compatible = "gianfar"; 153 compatible = "gianfar";
154 reg = <27000 1000>; 154 reg = <27000 1000>;
155 local-mac-address = [ 00 E0 0C 00 73 03 ]; 155 local-mac-address = [ 00 00 00 00 00 00 ];
156 interrupts = <15 2 16 2 17 2>; 156 interrupts = <25 2 26 2 27 2>;
157 interrupt-parent = <&mpic>; 157 interrupt-parent = <&mpic>;
158 phy-handle = <&phy3>; 158 phy-handle = <&phy3>;
159 }; 159 };
@@ -164,7 +164,7 @@
164 compatible = "ns16550"; 164 compatible = "ns16550";
165 reg = <4500 100>; // reg base, size 165 reg = <4500 100>; // reg base, size
166 clock-frequency = <0>; // should we fill in in uboot? 166 clock-frequency = <0>; // should we fill in in uboot?
167 interrupts = <1a 2>; 167 interrupts = <2a 2>;
168 interrupt-parent = <&mpic>; 168 interrupt-parent = <&mpic>;
169 }; 169 };
170 170
@@ -173,58 +173,64 @@
173 compatible = "ns16550"; 173 compatible = "ns16550";
174 reg = <4600 100>; // reg base, size 174 reg = <4600 100>; // reg base, size
175 clock-frequency = <0>; // should we fill in in uboot? 175 clock-frequency = <0>; // should we fill in in uboot?
176 interrupts = <1a 2>; 176 interrupts = <2a 2>;
177 interrupt-parent = <&mpic>; 177 interrupt-parent = <&mpic>;
178 }; 178 };
179 179
180 global-utilities@e0000 { //global utilities reg
181 compatible = "fsl,mpc8548-guts";
182 reg = <e0000 1000>;
183 fsl,has-rstcr;
184 };
185
180 pci1: pci@8000 { 186 pci1: pci@8000 {
181 interrupt-map-mask = <1f800 0 0 7>; 187 interrupt-map-mask = <1f800 0 0 7>;
182 interrupt-map = < 188 interrupt-map = <
183 189
184 /* IDSEL 0x10 */ 190 /* IDSEL 0x10 */
185 08000 0 0 1 &mpic 30 1 191 08000 0 0 1 &mpic 0 1
186 08000 0 0 2 &mpic 31 1 192 08000 0 0 2 &mpic 1 1
187 08000 0 0 3 &mpic 32 1 193 08000 0 0 3 &mpic 2 1
188 08000 0 0 4 &mpic 33 1 194 08000 0 0 4 &mpic 3 1
189 195
190 /* IDSEL 0x11 */ 196 /* IDSEL 0x11 */
191 08800 0 0 1 &mpic 30 1 197 08800 0 0 1 &mpic 0 1
192 08800 0 0 2 &mpic 31 1 198 08800 0 0 2 &mpic 1 1
193 08800 0 0 3 &mpic 32 1 199 08800 0 0 3 &mpic 2 1
194 08800 0 0 4 &mpic 33 1 200 08800 0 0 4 &mpic 3 1
195 201
196 /* IDSEL 0x12 (Slot 1) */ 202 /* IDSEL 0x12 (Slot 1) */
197 09000 0 0 1 &mpic 30 1 203 09000 0 0 1 &mpic 0 1
198 09000 0 0 2 &mpic 31 1 204 09000 0 0 2 &mpic 1 1
199 09000 0 0 3 &mpic 32 1 205 09000 0 0 3 &mpic 2 1
200 09000 0 0 4 &mpic 33 1 206 09000 0 0 4 &mpic 3 1
201 207
202 /* IDSEL 0x13 (Slot 2) */ 208 /* IDSEL 0x13 (Slot 2) */
203 09800 0 0 1 &mpic 31 1 209 09800 0 0 1 &mpic 1 1
204 09800 0 0 2 &mpic 32 1 210 09800 0 0 2 &mpic 2 1
205 09800 0 0 3 &mpic 33 1 211 09800 0 0 3 &mpic 3 1
206 09800 0 0 4 &mpic 30 1 212 09800 0 0 4 &mpic 0 1
207 213
208 /* IDSEL 0x14 (Slot 3) */ 214 /* IDSEL 0x14 (Slot 3) */
209 0a000 0 0 1 &mpic 32 1 215 0a000 0 0 1 &mpic 2 1
210 0a000 0 0 2 &mpic 33 1 216 0a000 0 0 2 &mpic 3 1
211 0a000 0 0 3 &mpic 30 1 217 0a000 0 0 3 &mpic 0 1
212 0a000 0 0 4 &mpic 31 1 218 0a000 0 0 4 &mpic 1 1
213 219
214 /* IDSEL 0x15 (Slot 4) */ 220 /* IDSEL 0x15 (Slot 4) */
215 0a800 0 0 1 &mpic 33 1 221 0a800 0 0 1 &mpic 3 1
216 0a800 0 0 2 &mpic 30 1 222 0a800 0 0 2 &mpic 0 1
217 0a800 0 0 3 &mpic 31 1 223 0a800 0 0 3 &mpic 1 1
218 0a800 0 0 4 &mpic 32 1 224 0a800 0 0 4 &mpic 2 1
219 225
220 /* Bus 1 (Tundra Bridge) */ 226 /* Bus 1 (Tundra Bridge) */
221 /* IDSEL 0x12 (ISA bridge) */ 227 /* IDSEL 0x12 (ISA bridge) */
222 19000 0 0 1 &mpic 30 1 228 19000 0 0 1 &mpic 0 1
223 19000 0 0 2 &mpic 31 1 229 19000 0 0 2 &mpic 1 1
224 19000 0 0 3 &mpic 32 1 230 19000 0 0 3 &mpic 2 1
225 19000 0 0 4 &mpic 33 1>; 231 19000 0 0 4 &mpic 3 1>;
226 interrupt-parent = <&mpic>; 232 interrupt-parent = <&mpic>;
227 interrupts = <08 2>; 233 interrupts = <18 2>;
228 bus-range = <0 0>; 234 bus-range = <0 0>;
229 ranges = <02000000 0 80000000 80000000 0 20000000 235 ranges = <02000000 0 80000000 80000000 0 20000000
230 01000000 0 00000000 e2000000 0 00100000>; 236 01000000 0 00000000 e2000000 0 00100000>;
@@ -256,12 +262,12 @@
256 interrupt-map = < 262 interrupt-map = <
257 263
258 /* IDSEL 0x15 */ 264 /* IDSEL 0x15 */
259 a800 0 0 1 &mpic 3b 1 265 a800 0 0 1 &mpic b 1
260 a800 0 0 2 &mpic 3b 1 266 a800 0 0 2 &mpic b 1
261 a800 0 0 3 &mpic 3b 1 267 a800 0 0 3 &mpic b 1
262 a800 0 0 4 &mpic 3b 1>; 268 a800 0 0 4 &mpic b 1>;
263 interrupt-parent = <&mpic>; 269 interrupt-parent = <&mpic>;
264 interrupts = <09 2>; 270 interrupts = <19 2>;
265 bus-range = <0 0>; 271 bus-range = <0 0>;
266 ranges = <02000000 0 a0000000 a0000000 0 20000000 272 ranges = <02000000 0 a0000000 a0000000 0 20000000
267 01000000 0 00000000 e3000000 0 00100000>; 273 01000000 0 00000000 e3000000 0 00100000>;