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-rw-r--r--arch/powerpc/boot/dts/mpc8544ds.dts473
1 files changed, 38 insertions, 435 deletions
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index d793968743c9..e934987e882b 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -9,339 +9,52 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "fsl/mpc8544si-pre.dtsi"
13
13/ { 14/ {
14 model = "MPC8544DS"; 15 model = "MPC8544DS";
15 compatible = "MPC8544DS", "MPC85xxDS"; 16 compatible = "MPC8544DS", "MPC85xxDS";
16 #address-cells = <1>;
17 #size-cells = <1>;
18
19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 serial0 = &serial0;
23 serial1 = &serial1;
24 pci0 = &pci0;
25 pci1 = &pci1;
26 pci2 = &pci2;
27 pci3 = &pci3;
28 };
29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 PowerPC,8544@0 {
35 device_type = "cpu";
36 reg = <0x0>;
37 d-cache-line-size = <32>; // 32 bytes
38 i-cache-line-size = <32>; // 32 bytes
39 d-cache-size = <0x8000>; // L1, 32K
40 i-cache-size = <0x8000>; // L1, 32K
41 timebase-frequency = <0>;
42 bus-frequency = <0>;
43 clock-frequency = <0>;
44 next-level-cache = <&L2>;
45 };
46 };
47 17
48 memory { 18 memory {
49 device_type = "memory"; 19 device_type = "memory";
50 reg = <0x0 0x0>; // Filled by U-Boot 20 reg = <0 0 0 0>; // Filled by U-Boot
51 }; 21 };
52 22
53 soc8544@e0000000 { 23 lbc: localbus@e0005000 {
54 #address-cells = <1>; 24 reg = <0 0xe0005000 0 0x1000>;
55 #size-cells = <1>; 25 };
56 device_type = "soc";
57 compatible = "simple-bus";
58
59 ranges = <0x0 0xe0000000 0x100000>;
60 bus-frequency = <0>; // Filled out by uboot.
61
62 ecm-law@0 {
63 compatible = "fsl,ecm-law";
64 reg = <0x0 0x1000>;
65 fsl,num-laws = <10>;
66 };
67
68 ecm@1000 {
69 compatible = "fsl,mpc8544-ecm", "fsl,ecm";
70 reg = <0x1000 0x1000>;
71 interrupts = <17 2>;
72 interrupt-parent = <&mpic>;
73 };
74
75 memory-controller@2000 {
76 compatible = "fsl,mpc8544-memory-controller";
77 reg = <0x2000 0x1000>;
78 interrupt-parent = <&mpic>;
79 interrupts = <18 2>;
80 };
81
82 L2: l2-cache-controller@20000 {
83 compatible = "fsl,mpc8544-l2-cache-controller";
84 reg = <0x20000 0x1000>;
85 cache-line-size = <32>; // 32 bytes
86 cache-size = <0x40000>; // L2, 256K
87 interrupt-parent = <&mpic>;
88 interrupts = <16 2>;
89 };
90
91 i2c@3000 {
92 #address-cells = <1>;
93 #size-cells = <0>;
94 cell-index = <0>;
95 compatible = "fsl-i2c";
96 reg = <0x3000 0x100>;
97 interrupts = <43 2>;
98 interrupt-parent = <&mpic>;
99 dfsrr;
100 };
101
102 i2c@3100 {
103 #address-cells = <1>;
104 #size-cells = <0>;
105 cell-index = <1>;
106 compatible = "fsl-i2c";
107 reg = <0x3100 0x100>;
108 interrupts = <43 2>;
109 interrupt-parent = <&mpic>;
110 dfsrr;
111 };
112
113 dma@21300 {
114 #address-cells = <1>;
115 #size-cells = <1>;
116 compatible = "fsl,mpc8544-dma", "fsl,eloplus-dma";
117 reg = <0x21300 0x4>;
118 ranges = <0x0 0x21100 0x200>;
119 cell-index = <0>;
120 dma-channel@0 {
121 compatible = "fsl,mpc8544-dma-channel",
122 "fsl,eloplus-dma-channel";
123 reg = <0x0 0x80>;
124 cell-index = <0>;
125 interrupt-parent = <&mpic>;
126 interrupts = <20 2>;
127 };
128 dma-channel@80 {
129 compatible = "fsl,mpc8544-dma-channel",
130 "fsl,eloplus-dma-channel";
131 reg = <0x80 0x80>;
132 cell-index = <1>;
133 interrupt-parent = <&mpic>;
134 interrupts = <21 2>;
135 };
136 dma-channel@100 {
137 compatible = "fsl,mpc8544-dma-channel",
138 "fsl,eloplus-dma-channel";
139 reg = <0x100 0x80>;
140 cell-index = <2>;
141 interrupt-parent = <&mpic>;
142 interrupts = <22 2>;
143 };
144 dma-channel@180 {
145 compatible = "fsl,mpc8544-dma-channel",
146 "fsl,eloplus-dma-channel";
147 reg = <0x180 0x80>;
148 cell-index = <3>;
149 interrupt-parent = <&mpic>;
150 interrupts = <23 2>;
151 };
152 };
153
154 enet0: ethernet@24000 {
155 #address-cells = <1>;
156 #size-cells = <1>;
157 cell-index = <0>;
158 device_type = "network";
159 model = "TSEC";
160 compatible = "gianfar";
161 reg = <0x24000 0x1000>;
162 ranges = <0x0 0x24000 0x1000>;
163 local-mac-address = [ 00 00 00 00 00 00 ];
164 interrupts = <29 2 30 2 34 2>;
165 interrupt-parent = <&mpic>;
166 phy-handle = <&phy0>;
167 tbi-handle = <&tbi0>;
168 phy-connection-type = "rgmii-id";
169
170 mdio@520 {
171 #address-cells = <1>;
172 #size-cells = <0>;
173 compatible = "fsl,gianfar-mdio";
174 reg = <0x520 0x20>;
175
176 phy0: ethernet-phy@0 {
177 interrupt-parent = <&mpic>;
178 interrupts = <10 1>;
179 reg = <0x0>;
180 device_type = "ethernet-phy";
181 };
182 phy1: ethernet-phy@1 {
183 interrupt-parent = <&mpic>;
184 interrupts = <10 1>;
185 reg = <0x1>;
186 device_type = "ethernet-phy";
187 };
188
189 tbi0: tbi-phy@11 {
190 reg = <0x11>;
191 device_type = "tbi-phy";
192 };
193 };
194 };
195
196 enet1: ethernet@26000 {
197 #address-cells = <1>;
198 #size-cells = <1>;
199 cell-index = <1>;
200 device_type = "network";
201 model = "TSEC";
202 compatible = "gianfar";
203 reg = <0x26000 0x1000>;
204 ranges = <0x0 0x26000 0x1000>;
205 local-mac-address = [ 00 00 00 00 00 00 ];
206 interrupts = <31 2 32 2 33 2>;
207 interrupt-parent = <&mpic>;
208 phy-handle = <&phy1>;
209 tbi-handle = <&tbi1>;
210 phy-connection-type = "rgmii-id";
211
212 mdio@520 {
213 #address-cells = <1>;
214 #size-cells = <0>;
215 compatible = "fsl,gianfar-tbi";
216 reg = <0x520 0x20>;
217
218 tbi1: tbi-phy@11 {
219 reg = <0x11>;
220 device_type = "tbi-phy";
221 };
222 };
223 };
224
225 serial0: serial@4500 {
226 cell-index = <0>;
227 device_type = "serial";
228 compatible = "ns16550";
229 reg = <0x4500 0x100>;
230 clock-frequency = <0>;
231 interrupts = <42 2>;
232 interrupt-parent = <&mpic>;
233 };
234
235 serial1: serial@4600 {
236 cell-index = <1>;
237 device_type = "serial";
238 compatible = "ns16550";
239 reg = <0x4600 0x100>;
240 clock-frequency = <0>;
241 interrupts = <42 2>;
242 interrupt-parent = <&mpic>;
243 };
244
245 global-utilities@e0000 { //global utilities block
246 compatible = "fsl,mpc8548-guts";
247 reg = <0xe0000 0x1000>;
248 fsl,has-rstcr;
249 };
250
251 crypto@30000 {
252 compatible = "fsl,sec2.1", "fsl,sec2.0";
253 reg = <0x30000 0x10000>;
254 interrupts = <45 2>;
255 interrupt-parent = <&mpic>;
256 fsl,num-channels = <4>;
257 fsl,channel-fifo-len = <24>;
258 fsl,exec-units-mask = <0xfe>;
259 fsl,descriptor-types-mask = <0x12b0ebf>;
260 };
261
262 mpic: pic@40000 {
263 interrupt-controller;
264 #address-cells = <0>;
265 #interrupt-cells = <2>;
266 reg = <0x40000 0x40000>;
267 compatible = "chrp,open-pic";
268 device_type = "open-pic";
269 };
270 26
271 msi@41600 { 27 board_soc: soc: soc8544@e0000000 {
272 compatible = "fsl,mpc8544-msi", "fsl,mpic-msi"; 28 ranges = <0x0 0x0 0xe0000000 0x100000>;
273 reg = <0x41600 0x80>;
274 msi-available-ranges = <0 0x100>;
275 interrupts = <
276 0xe0 0
277 0xe1 0
278 0xe2 0
279 0xe3 0
280 0xe4 0
281 0xe5 0
282 0xe6 0
283 0xe7 0>;
284 interrupt-parent = <&mpic>;
285 };
286 }; 29 };
287 30
288 pci0: pci@e0008000 { 31 pci0: pci@e0008000 {
289 compatible = "fsl,mpc8540-pci"; 32 reg = <0 0xe0008000 0 0x1000>;
290 device_type = "pci"; 33 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
34 0x1000000 0x0 0x00000000 0 0xe1000000 0x0 0x10000>;
35 clock-frequency = <66666666>;
291 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 36 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
292 interrupt-map = < 37 interrupt-map = <
293 38
294 /* IDSEL 0x11 J17 Slot 1 */ 39 /* IDSEL 0x11 J17 Slot 1 */
295 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 40 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
296 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 41 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
297 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 42 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
298 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1 43 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
299 44
300 /* IDSEL 0x12 J16 Slot 2 */ 45 /* IDSEL 0x12 J16 Slot 2 */
301 46
302 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1 47 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
303 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1 48 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
304 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1 49 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
305 0x9000 0x0 0x0 0x4 &mpic 0x1 0x1>; 50 0x9000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0>;
306
307 interrupt-parent = <&mpic>;
308 interrupts = <24 2>;
309 bus-range = <0 255>;
310 ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
311 0x1000000 0x0 0x0 0xe1000000 0x0 0x10000>;
312 clock-frequency = <66666666>;
313 #interrupt-cells = <1>;
314 #size-cells = <2>;
315 #address-cells = <3>;
316 reg = <0xe0008000 0x1000>;
317 }; 51 };
318 52
319 pci1: pcie@e0009000 { 53 pci1: pcie@e0009000 {
320 compatible = "fsl,mpc8548-pcie"; 54 reg = <0x0 0xe0009000 0x0 0x1000>;
321 device_type = "pci"; 55 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
322 #interrupt-cells = <1>; 56 0x1000000 0x0 0x00000000 0 0xe1010000 0x0 0x10000>;
323 #size-cells = <2>;
324 #address-cells = <3>;
325 reg = <0xe0009000 0x1000>;
326 bus-range = <0 255>;
327 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
328 0x1000000 0x0 0x0 0xe1010000 0x0 0x10000>;
329 clock-frequency = <33333333>;
330 interrupt-parent = <&mpic>;
331 interrupts = <25 2>;
332 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
333 interrupt-map = <
334 /* IDSEL 0x0 */
335 0000 0x0 0x0 0x1 &mpic 0x4 0x1
336 0000 0x0 0x0 0x2 &mpic 0x5 0x1
337 0000 0x0 0x0 0x3 &mpic 0x6 0x1
338 0000 0x0 0x0 0x4 &mpic 0x7 0x1
339 >;
340 pcie@0 { 57 pcie@0 {
341 reg = <0x0 0x0 0x0 0x0 0x0>;
342 #size-cells = <2>;
343 #address-cells = <3>;
344 device_type = "pci";
345 ranges = <0x2000000 0x0 0x80000000 58 ranges = <0x2000000 0x0 0x80000000
346 0x2000000 0x0 0x80000000 59 0x2000000 0x0 0x80000000
347 0x0 0x20000000 60 0x0 0x20000000
@@ -353,31 +66,10 @@
353 }; 66 };
354 67
355 pci2: pcie@e000a000 { 68 pci2: pcie@e000a000 {
356 compatible = "fsl,mpc8548-pcie"; 69 reg = <0x0 0xe000a000 0x0 0x1000>;
357 device_type = "pci"; 70 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x10000000
358 #interrupt-cells = <1>; 71 0x1000000 0x0 0x00000000 0 0xe1020000 0x0 0x10000>;
359 #size-cells = <2>;
360 #address-cells = <3>;
361 reg = <0xe000a000 0x1000>;
362 bus-range = <0 255>;
363 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
364 0x1000000 0x0 0x0 0xe1020000 0x0 0x10000>;
365 clock-frequency = <33333333>;
366 interrupt-parent = <&mpic>;
367 interrupts = <26 2>;
368 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
369 interrupt-map = <
370 /* IDSEL 0x0 */
371 0000 0x0 0x0 0x1 &mpic 0x0 0x1
372 0000 0x0 0x0 0x2 &mpic 0x1 0x1
373 0000 0x0 0x0 0x3 &mpic 0x2 0x1
374 0000 0x0 0x0 0x4 &mpic 0x3 0x1
375 >;
376 pcie@0 { 72 pcie@0 {
377 reg = <0x0 0x0 0x0 0x0 0x0>;
378 #size-cells = <2>;
379 #address-cells = <3>;
380 device_type = "pci";
381 ranges = <0x2000000 0x0 0xa0000000 73 ranges = <0x2000000 0x0 0xa0000000
382 0x2000000 0x0 0xa0000000 74 0x2000000 0x0 0xa0000000
383 0x0 0x10000000 75 0x0 0x10000000
@@ -388,44 +80,11 @@
388 }; 80 };
389 }; 81 };
390 82
391 pci3: pcie@e000b000 { 83 board_pci3: pci3: pcie@e000b000 {
392 compatible = "fsl,mpc8548-pcie"; 84 reg = <0x0 0xe000b000 0x0 0x1000>;
393 device_type = "pci"; 85 ranges = <0x2000000 0x0 0xb0000000 0 0xb0000000 0x0 0x100000
394 #interrupt-cells = <1>; 86 0x1000000 0x0 0x00000000 0 0xb0100000 0x0 0x100000>;
395 #size-cells = <2>;
396 #address-cells = <3>;
397 reg = <0xe000b000 0x1000>;
398 bus-range = <0 255>;
399 ranges = <0x2000000 0x0 0xb0000000 0xb0000000 0x0 0x100000
400 0x1000000 0x0 0x0 0xb0100000 0x0 0x100000>;
401 clock-frequency = <33333333>;
402 interrupt-parent = <&mpic>;
403 interrupts = <27 2>;
404 interrupt-map-mask = <0xff00 0x0 0x0 0x1>;
405 interrupt-map = <
406 // IDSEL 0x1c USB
407 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
408 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
409 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
410 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
411
412 // IDSEL 0x1d Audio
413 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
414
415 // IDSEL 0x1e Legacy
416 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
417 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
418
419 // IDSEL 0x1f IDE/SATA
420 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
421 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
422 >;
423
424 pcie@0 { 87 pcie@0 {
425 reg = <0x0 0x0 0x0 0x0 0x0>;
426 #size-cells = <2>;
427 #address-cells = <3>;
428 device_type = "pci";
429 ranges = <0x2000000 0x0 0xb0000000 88 ranges = <0x2000000 0x0 0xb0000000
430 0x2000000 0x0 0xb0000000 89 0x2000000 0x0 0xb0000000
431 0x0 0x100000 90 0x0 0x100000
@@ -433,70 +92,14 @@
433 0x1000000 0x0 0x0 92 0x1000000 0x0 0x0
434 0x1000000 0x0 0x0 93 0x1000000 0x0 0x0
435 0x0 0x100000>; 94 0x0 0x100000>;
436
437 uli1575@0 {
438 reg = <0x0 0x0 0x0 0x0 0x0>;
439 #size-cells = <2>;
440 #address-cells = <3>;
441 ranges = <0x2000000 0x0 0xb0000000
442 0x2000000 0x0 0xb0000000
443 0x0 0x100000
444
445 0x1000000 0x0 0x0
446 0x1000000 0x0 0x0
447 0x0 0x100000>;
448 isa@1e {
449 device_type = "isa";
450 #interrupt-cells = <2>;
451 #size-cells = <1>;
452 #address-cells = <2>;
453 reg = <0xf000 0x0 0x0 0x0 0x0>;
454 ranges = <0x1 0x0
455 0x1000000 0x0 0x0
456 0x1000>;
457 interrupt-parent = <&i8259>;
458
459 i8259: interrupt-controller@20 {
460 reg = <0x1 0x20 0x2
461 0x1 0xa0 0x2
462 0x1 0x4d0 0x2>;
463 interrupt-controller;
464 device_type = "interrupt-controller";
465 #address-cells = <0>;
466 #interrupt-cells = <2>;
467 compatible = "chrp,iic";
468 interrupts = <9 2>;
469 interrupt-parent = <&mpic>;
470 };
471
472 i8042@60 {
473 #size-cells = <0>;
474 #address-cells = <1>;
475 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
476 interrupts = <1 3 12 3>;
477 interrupt-parent = <&i8259>;
478
479 keyboard@0 {
480 reg = <0x0>;
481 compatible = "pnpPNP,303";
482 };
483
484 mouse@1 {
485 reg = <0x1>;
486 compatible = "pnpPNP,f03";
487 };
488 };
489
490 rtc@70 {
491 compatible = "pnpPNP,b00";
492 reg = <0x1 0x70 0x2>;
493 };
494
495 gpio@400 {
496 reg = <0x1 0x400 0x80>;
497 };
498 };
499 };
500 }; 95 };
501 }; 96 };
502}; 97};
98
99/*
100 * mpc8544ds.dtsi must be last to ensure board_pci3 overrides pci3 settings
101 * for interrupt-map & interrupt-map-mask
102 */
103
104/include/ "fsl/mpc8544si-post.dtsi"
105/include/ "mpc8544ds.dtsi"
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-01 17:44:35 -0500