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-rw-r--r--arch/powerpc/boot/dts/mpc8544ds.dts299
1 files changed, 170 insertions, 129 deletions
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index 688af9d06382..6a0d8db96d97 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8544 DS Device Tree Source 2 * MPC8544 DS Device Tree Source
3 * 3 *
4 * Copyright 2007 Freescale Semiconductor Inc. 4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,6 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
12/ { 13/ {
13 model = "MPC8544DS"; 14 model = "MPC8544DS";
14 compatible = "MPC8544DS", "MPC85xxDS"; 15 compatible = "MPC8544DS", "MPC85xxDS";
@@ -27,17 +28,16 @@
27 }; 28 };
28 29
29 cpus { 30 cpus {
30 #cpus = <1>;
31 #address-cells = <1>; 31 #address-cells = <1>;
32 #size-cells = <0>; 32 #size-cells = <0>;
33 33
34 PowerPC,8544@0 { 34 PowerPC,8544@0 {
35 device_type = "cpu"; 35 device_type = "cpu";
36 reg = <0>; 36 reg = <0x0>;
37 d-cache-line-size = <20>; // 32 bytes 37 d-cache-line-size = <32>; // 32 bytes
38 i-cache-line-size = <20>; // 32 bytes 38 i-cache-line-size = <32>; // 32 bytes
39 d-cache-size = <8000>; // L1, 32K 39 d-cache-size = <0x8000>; // L1, 32K
40 i-cache-size = <8000>; // L1, 32K 40 i-cache-size = <0x8000>; // L1, 32K
41 timebase-frequency = <0>; 41 timebase-frequency = <0>;
42 bus-frequency = <0>; 42 bus-frequency = <0>;
43 clock-frequency = <0>; 43 clock-frequency = <0>;
@@ -46,7 +46,7 @@
46 46
47 memory { 47 memory {
48 device_type = "memory"; 48 device_type = "memory";
49 reg = <00000000 00000000>; // Filled by U-Boot 49 reg = <0x0 0x0>; // Filled by U-Boot
50 }; 50 };
51 51
52 soc8544@e0000000 { 52 soc8544@e0000000 {
@@ -54,24 +54,24 @@
54 #size-cells = <1>; 54 #size-cells = <1>;
55 device_type = "soc"; 55 device_type = "soc";
56 56
57 ranges = <00000000 e0000000 00100000>; 57 ranges = <0x0 0xe0000000 0x100000>;
58 reg = <e0000000 00001000>; // CCSRBAR 1M 58 reg = <0xe0000000 0x1000>; // CCSRBAR 1M
59 bus-frequency = <0>; // Filled out by uboot. 59 bus-frequency = <0>; // Filled out by uboot.
60 60
61 memory-controller@2000 { 61 memory-controller@2000 {
62 compatible = "fsl,8544-memory-controller"; 62 compatible = "fsl,8544-memory-controller";
63 reg = <2000 1000>; 63 reg = <0x2000 0x1000>;
64 interrupt-parent = <&mpic>; 64 interrupt-parent = <&mpic>;
65 interrupts = <12 2>; 65 interrupts = <18 2>;
66 }; 66 };
67 67
68 l2-cache-controller@20000 { 68 l2-cache-controller@20000 {
69 compatible = "fsl,8544-l2-cache-controller"; 69 compatible = "fsl,8544-l2-cache-controller";
70 reg = <20000 1000>; 70 reg = <0x20000 0x1000>;
71 cache-line-size = <20>; // 32 bytes 71 cache-line-size = <32>; // 32 bytes
72 cache-size = <40000>; // L2, 256K 72 cache-size = <0x40000>; // L2, 256K
73 interrupt-parent = <&mpic>; 73 interrupt-parent = <&mpic>;
74 interrupts = <10 2>; 74 interrupts = <16 2>;
75 }; 75 };
76 76
77 i2c@3000 { 77 i2c@3000 {
@@ -79,8 +79,8 @@
79 #size-cells = <0>; 79 #size-cells = <0>;
80 cell-index = <0>; 80 cell-index = <0>;
81 compatible = "fsl-i2c"; 81 compatible = "fsl-i2c";
82 reg = <3000 100>; 82 reg = <0x3000 0x100>;
83 interrupts = <2b 2>; 83 interrupts = <43 2>;
84 interrupt-parent = <&mpic>; 84 interrupt-parent = <&mpic>;
85 dfsrr; 85 dfsrr;
86 }; 86 };
@@ -90,8 +90,8 @@
90 #size-cells = <0>; 90 #size-cells = <0>;
91 cell-index = <1>; 91 cell-index = <1>;
92 compatible = "fsl-i2c"; 92 compatible = "fsl-i2c";
93 reg = <3100 100>; 93 reg = <0x3100 0x100>;
94 interrupts = <2b 2>; 94 interrupts = <43 2>;
95 interrupt-parent = <&mpic>; 95 interrupt-parent = <&mpic>;
96 dfsrr; 96 dfsrr;
97 }; 97 };
@@ -100,30 +100,71 @@
100 #address-cells = <1>; 100 #address-cells = <1>;
101 #size-cells = <0>; 101 #size-cells = <0>;
102 compatible = "fsl,gianfar-mdio"; 102 compatible = "fsl,gianfar-mdio";
103 reg = <24520 20>; 103 reg = <0x24520 0x20>;
104 104
105 phy0: ethernet-phy@0 { 105 phy0: ethernet-phy@0 {
106 interrupt-parent = <&mpic>; 106 interrupt-parent = <&mpic>;
107 interrupts = <a 1>; 107 interrupts = <10 1>;
108 reg = <0>; 108 reg = <0x0>;
109 device_type = "ethernet-phy"; 109 device_type = "ethernet-phy";
110 }; 110 };
111 phy1: ethernet-phy@1 { 111 phy1: ethernet-phy@1 {
112 interrupt-parent = <&mpic>; 112 interrupt-parent = <&mpic>;
113 interrupts = <a 1>; 113 interrupts = <10 1>;
114 reg = <1>; 114 reg = <0x1>;
115 device_type = "ethernet-phy"; 115 device_type = "ethernet-phy";
116 }; 116 };
117 }; 117 };
118 118
119 dma@21300 {
120 #address-cells = <1>;
121 #size-cells = <1>;
122 compatible = "fsl,mpc8544-dma", "fsl,eloplus-dma";
123 reg = <0x21300 0x4>;
124 ranges = <0x0 0x21100 0x200>;
125 cell-index = <0>;
126 dma-channel@0 {
127 compatible = "fsl,mpc8544-dma-channel",
128 "fsl,eloplus-dma-channel";
129 reg = <0x0 0x80>;
130 cell-index = <0>;
131 interrupt-parent = <&mpic>;
132 interrupts = <20 2>;
133 };
134 dma-channel@80 {
135 compatible = "fsl,mpc8544-dma-channel",
136 "fsl,eloplus-dma-channel";
137 reg = <0x80 0x80>;
138 cell-index = <1>;
139 interrupt-parent = <&mpic>;
140 interrupts = <21 2>;
141 };
142 dma-channel@100 {
143 compatible = "fsl,mpc8544-dma-channel",
144 "fsl,eloplus-dma-channel";
145 reg = <0x100 0x80>;
146 cell-index = <2>;
147 interrupt-parent = <&mpic>;
148 interrupts = <22 2>;
149 };
150 dma-channel@180 {
151 compatible = "fsl,mpc8544-dma-channel",
152 "fsl,eloplus-dma-channel";
153 reg = <0x180 0x80>;
154 cell-index = <3>;
155 interrupt-parent = <&mpic>;
156 interrupts = <23 2>;
157 };
158 };
159
119 enet0: ethernet@24000 { 160 enet0: ethernet@24000 {
120 cell-index = <0>; 161 cell-index = <0>;
121 device_type = "network"; 162 device_type = "network";
122 model = "TSEC"; 163 model = "TSEC";
123 compatible = "gianfar"; 164 compatible = "gianfar";
124 reg = <24000 1000>; 165 reg = <0x24000 0x1000>;
125 local-mac-address = [ 00 00 00 00 00 00 ]; 166 local-mac-address = [ 00 00 00 00 00 00 ];
126 interrupts = <1d 2 1e 2 22 2>; 167 interrupts = <29 2 30 2 34 2>;
127 interrupt-parent = <&mpic>; 168 interrupt-parent = <&mpic>;
128 phy-handle = <&phy0>; 169 phy-handle = <&phy0>;
129 phy-connection-type = "rgmii-id"; 170 phy-connection-type = "rgmii-id";
@@ -134,9 +175,9 @@
134 device_type = "network"; 175 device_type = "network";
135 model = "TSEC"; 176 model = "TSEC";
136 compatible = "gianfar"; 177 compatible = "gianfar";
137 reg = <26000 1000>; 178 reg = <0x26000 0x1000>;
138 local-mac-address = [ 00 00 00 00 00 00 ]; 179 local-mac-address = [ 00 00 00 00 00 00 ];
139 interrupts = <1f 2 20 2 21 2>; 180 interrupts = <31 2 32 2 33 2>;
140 interrupt-parent = <&mpic>; 181 interrupt-parent = <&mpic>;
141 phy-handle = <&phy1>; 182 phy-handle = <&phy1>;
142 phy-connection-type = "rgmii-id"; 183 phy-connection-type = "rgmii-id";
@@ -146,9 +187,9 @@
146 cell-index = <0>; 187 cell-index = <0>;
147 device_type = "serial"; 188 device_type = "serial";
148 compatible = "ns16550"; 189 compatible = "ns16550";
149 reg = <4500 100>; 190 reg = <0x4500 0x100>;
150 clock-frequency = <0>; 191 clock-frequency = <0>;
151 interrupts = <2a 2>; 192 interrupts = <42 2>;
152 interrupt-parent = <&mpic>; 193 interrupt-parent = <&mpic>;
153 }; 194 };
154 195
@@ -156,15 +197,15 @@
156 cell-index = <1>; 197 cell-index = <1>;
157 device_type = "serial"; 198 device_type = "serial";
158 compatible = "ns16550"; 199 compatible = "ns16550";
159 reg = <4600 100>; 200 reg = <0x4600 0x100>;
160 clock-frequency = <0>; 201 clock-frequency = <0>;
161 interrupts = <2a 2>; 202 interrupts = <42 2>;
162 interrupt-parent = <&mpic>; 203 interrupt-parent = <&mpic>;
163 }; 204 };
164 205
165 global-utilities@e0000 { //global utilities block 206 global-utilities@e0000 { //global utilities block
166 compatible = "fsl,mpc8548-guts"; 207 compatible = "fsl,mpc8548-guts";
167 reg = <e0000 1000>; 208 reg = <0xe0000 0x1000>;
168 fsl,has-rstcr; 209 fsl,has-rstcr;
169 }; 210 };
170 211
@@ -173,7 +214,7 @@
173 interrupt-controller; 214 interrupt-controller;
174 #address-cells = <0>; 215 #address-cells = <0>;
175 #interrupt-cells = <2>; 216 #interrupt-cells = <2>;
176 reg = <40000 40000>; 217 reg = <0x40000 0x40000>;
177 compatible = "chrp,open-pic"; 218 compatible = "chrp,open-pic";
178 device_type = "open-pic"; 219 device_type = "open-pic";
179 big-endian; 220 big-endian;
@@ -184,32 +225,32 @@
184 cell-index = <0>; 225 cell-index = <0>;
185 compatible = "fsl,mpc8540-pci"; 226 compatible = "fsl,mpc8540-pci";
186 device_type = "pci"; 227 device_type = "pci";
187 interrupt-map-mask = <f800 0 0 7>; 228 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
188 interrupt-map = < 229 interrupt-map = <
189 230
190 /* IDSEL 0x11 J17 Slot 1 */ 231 /* IDSEL 0x11 J17 Slot 1 */
191 8800 0 0 1 &mpic 2 1 232 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
192 8800 0 0 2 &mpic 3 1 233 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
193 8800 0 0 3 &mpic 4 1 234 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
194 8800 0 0 4 &mpic 1 1 235 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
195 236
196 /* IDSEL 0x12 J16 Slot 2 */ 237 /* IDSEL 0x12 J16 Slot 2 */
197 238
198 9000 0 0 1 &mpic 3 1 239 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
199 9000 0 0 2 &mpic 4 1 240 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
200 9000 0 0 3 &mpic 2 1 241 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
201 9000 0 0 4 &mpic 1 1>; 242 0x9000 0x0 0x0 0x4 &mpic 0x1 0x1>;
202 243
203 interrupt-parent = <&mpic>; 244 interrupt-parent = <&mpic>;
204 interrupts = <18 2>; 245 interrupts = <24 2>;
205 bus-range = <0 ff>; 246 bus-range = <0 255>;
206 ranges = <02000000 0 c0000000 c0000000 0 20000000 247 ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
207 01000000 0 00000000 e1000000 0 00010000>; 248 0x1000000 0x0 0x0 0xe1000000 0x0 0x10000>;
208 clock-frequency = <3f940aa>; 249 clock-frequency = <66666666>;
209 #interrupt-cells = <1>; 250 #interrupt-cells = <1>;
210 #size-cells = <2>; 251 #size-cells = <2>;
211 #address-cells = <3>; 252 #address-cells = <3>;
212 reg = <e0008000 1000>; 253 reg = <0xe0008000 0x1000>;
213 }; 254 };
214 255
215 pci1: pcie@e0009000 { 256 pci1: pcie@e0009000 {
@@ -219,33 +260,33 @@
219 #interrupt-cells = <1>; 260 #interrupt-cells = <1>;
220 #size-cells = <2>; 261 #size-cells = <2>;
221 #address-cells = <3>; 262 #address-cells = <3>;
222 reg = <e0009000 1000>; 263 reg = <0xe0009000 0x1000>;
223 bus-range = <0 ff>; 264 bus-range = <0 255>;
224 ranges = <02000000 0 80000000 80000000 0 20000000 265 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
225 01000000 0 00000000 e1010000 0 00010000>; 266 0x1000000 0x0 0x0 0xe1010000 0x0 0x10000>;
226 clock-frequency = <1fca055>; 267 clock-frequency = <33333333>;
227 interrupt-parent = <&mpic>; 268 interrupt-parent = <&mpic>;
228 interrupts = <1a 2>; 269 interrupts = <26 2>;
229 interrupt-map-mask = <f800 0 0 7>; 270 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
230 interrupt-map = < 271 interrupt-map = <
231 /* IDSEL 0x0 */ 272 /* IDSEL 0x0 */
232 0000 0 0 1 &mpic 4 1 273 0000 0x0 0x0 0x1 &mpic 0x4 0x1
233 0000 0 0 2 &mpic 5 1 274 0000 0x0 0x0 0x2 &mpic 0x5 0x1
234 0000 0 0 3 &mpic 6 1 275 0000 0x0 0x0 0x3 &mpic 0x6 0x1
235 0000 0 0 4 &mpic 7 1 276 0000 0x0 0x0 0x4 &mpic 0x7 0x1
236 >; 277 >;
237 pcie@0 { 278 pcie@0 {
238 reg = <0 0 0 0 0>; 279 reg = <0x0 0x0 0x0 0x0 0x0>;
239 #size-cells = <2>; 280 #size-cells = <2>;
240 #address-cells = <3>; 281 #address-cells = <3>;
241 device_type = "pci"; 282 device_type = "pci";
242 ranges = <02000000 0 80000000 283 ranges = <0x2000000 0x0 0x80000000
243 02000000 0 80000000 284 0x2000000 0x0 0x80000000
244 0 20000000 285 0x0 0x20000000
245 286
246 01000000 0 00000000 287 0x1000000 0x0 0x0
247 01000000 0 00000000 288 0x1000000 0x0 0x0
248 0 00010000>; 289 0x0 0x10000>;
249 }; 290 };
250 }; 291 };
251 292
@@ -256,33 +297,33 @@
256 #interrupt-cells = <1>; 297 #interrupt-cells = <1>;
257 #size-cells = <2>; 298 #size-cells = <2>;
258 #address-cells = <3>; 299 #address-cells = <3>;
259 reg = <e000a000 1000>; 300 reg = <0xe000a000 0x1000>;
260 bus-range = <0 ff>; 301 bus-range = <0 255>;
261 ranges = <02000000 0 a0000000 a0000000 0 10000000 302 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
262 01000000 0 00000000 e1020000 0 00010000>; 303 0x1000000 0x0 0x0 0xe1020000 0x0 0x10000>;
263 clock-frequency = <1fca055>; 304 clock-frequency = <33333333>;
264 interrupt-parent = <&mpic>; 305 interrupt-parent = <&mpic>;
265 interrupts = <19 2>; 306 interrupts = <25 2>;
266 interrupt-map-mask = <f800 0 0 7>; 307 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
267 interrupt-map = < 308 interrupt-map = <
268 /* IDSEL 0x0 */ 309 /* IDSEL 0x0 */
269 0000 0 0 1 &mpic 0 1 310 0000 0x0 0x0 0x1 &mpic 0x0 0x1
270 0000 0 0 2 &mpic 1 1 311 0000 0x0 0x0 0x2 &mpic 0x1 0x1
271 0000 0 0 3 &mpic 2 1 312 0000 0x0 0x0 0x3 &mpic 0x2 0x1
272 0000 0 0 4 &mpic 3 1 313 0000 0x0 0x0 0x4 &mpic 0x3 0x1
273 >; 314 >;
274 pcie@0 { 315 pcie@0 {
275 reg = <0 0 0 0 0>; 316 reg = <0x0 0x0 0x0 0x0 0x0>;
276 #size-cells = <2>; 317 #size-cells = <2>;
277 #address-cells = <3>; 318 #address-cells = <3>;
278 device_type = "pci"; 319 device_type = "pci";
279 ranges = <02000000 0 a0000000 320 ranges = <0x2000000 0x0 0xa0000000
280 02000000 0 a0000000 321 0x2000000 0x0 0xa0000000
281 0 10000000 322 0x0 0x10000000
282 323
283 01000000 0 00000000 324 0x1000000 0x0 0x0
284 01000000 0 00000000 325 0x1000000 0x0 0x0
285 0 00010000>; 326 0x0 0x10000>;
286 }; 327 };
287 }; 328 };
288 329
@@ -293,72 +334,72 @@
293 #interrupt-cells = <1>; 334 #interrupt-cells = <1>;
294 #size-cells = <2>; 335 #size-cells = <2>;
295 #address-cells = <3>; 336 #address-cells = <3>;
296 reg = <e000b000 1000>; 337 reg = <0xe000b000 0x1000>;
297 bus-range = <0 ff>; 338 bus-range = <0 255>;
298 ranges = <02000000 0 b0000000 b0000000 0 00100000 339 ranges = <0x2000000 0x0 0xb0000000 0xb0000000 0x0 0x100000
299 01000000 0 00000000 b0100000 0 00100000>; 340 0x1000000 0x0 0x0 0xb0100000 0x0 0x100000>;
300 clock-frequency = <1fca055>; 341 clock-frequency = <33333333>;
301 interrupt-parent = <&mpic>; 342 interrupt-parent = <&mpic>;
302 interrupts = <1b 2>; 343 interrupts = <27 2>;
303 interrupt-map-mask = <ff00 0 0 1>; 344 interrupt-map-mask = <0xff00 0x0 0x0 0x1>;
304 interrupt-map = < 345 interrupt-map = <
305 // IDSEL 0x1c USB 346 // IDSEL 0x1c USB
306 e000 0 0 1 &i8259 c 2 347 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
307 e100 0 0 2 &i8259 9 2 348 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
308 e200 0 0 3 &i8259 a 2 349 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
309 e300 0 0 4 &i8259 b 2 350 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
310 351
311 // IDSEL 0x1d Audio 352 // IDSEL 0x1d Audio
312 e800 0 0 1 &i8259 6 2 353 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
313 354
314 // IDSEL 0x1e Legacy 355 // IDSEL 0x1e Legacy
315 f000 0 0 1 &i8259 7 2 356 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
316 f100 0 0 1 &i8259 7 2 357 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
317 358
318 // IDSEL 0x1f IDE/SATA 359 // IDSEL 0x1f IDE/SATA
319 f800 0 0 1 &i8259 e 2 360 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
320 f900 0 0 1 &i8259 5 2 361 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
321 >; 362 >;
322 363
323 pcie@0 { 364 pcie@0 {
324 reg = <0 0 0 0 0>; 365 reg = <0x0 0x0 0x0 0x0 0x0>;
325 #size-cells = <2>; 366 #size-cells = <2>;
326 #address-cells = <3>; 367 #address-cells = <3>;
327 device_type = "pci"; 368 device_type = "pci";
328 ranges = <02000000 0 b0000000 369 ranges = <0x2000000 0x0 0xb0000000
329 02000000 0 b0000000 370 0x2000000 0x0 0xb0000000
330 0 00100000 371 0x0 0x100000
331 372
332 01000000 0 00000000 373 0x1000000 0x0 0x0
333 01000000 0 00000000 374 0x1000000 0x0 0x0
334 0 00100000>; 375 0x0 0x100000>;
335 376
336 uli1575@0 { 377 uli1575@0 {
337 reg = <0 0 0 0 0>; 378 reg = <0x0 0x0 0x0 0x0 0x0>;
338 #size-cells = <2>; 379 #size-cells = <2>;
339 #address-cells = <3>; 380 #address-cells = <3>;
340 ranges = <02000000 0 b0000000 381 ranges = <0x2000000 0x0 0xb0000000
341 02000000 0 b0000000 382 0x2000000 0x0 0xb0000000
342 0 00100000 383 0x0 0x100000
343 384
344 01000000 0 00000000 385 0x1000000 0x0 0x0
345 01000000 0 00000000 386 0x1000000 0x0 0x0
346 0 00100000>; 387 0x0 0x100000>;
347 isa@1e { 388 isa@1e {
348 device_type = "isa"; 389 device_type = "isa";
349 #interrupt-cells = <2>; 390 #interrupt-cells = <2>;
350 #size-cells = <1>; 391 #size-cells = <1>;
351 #address-cells = <2>; 392 #address-cells = <2>;
352 reg = <f000 0 0 0 0>; 393 reg = <0xf000 0x0 0x0 0x0 0x0>;
353 ranges = <1 0 394 ranges = <0x1 0x0
354 01000000 0 0 395 0x1000000 0x0 0x0
355 00001000>; 396 0x1000>;
356 interrupt-parent = <&i8259>; 397 interrupt-parent = <&i8259>;
357 398
358 i8259: interrupt-controller@20 { 399 i8259: interrupt-controller@20 {
359 reg = <1 20 2 400 reg = <0x1 0x20 0x2
360 1 a0 2 401 0x1 0xa0 0x2
361 1 4d0 2>; 402 0x1 0x4d0 0x2>;
362 interrupt-controller; 403 interrupt-controller;
363 device_type = "interrupt-controller"; 404 device_type = "interrupt-controller";
364 #address-cells = <0>; 405 #address-cells = <0>;
@@ -371,28 +412,28 @@
371 i8042@60 { 412 i8042@60 {
372 #size-cells = <0>; 413 #size-cells = <0>;
373 #address-cells = <1>; 414 #address-cells = <1>;
374 reg = <1 60 1 1 64 1>; 415 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
375 interrupts = <1 3 c 3>; 416 interrupts = <1 3 12 3>;
376 interrupt-parent = <&i8259>; 417 interrupt-parent = <&i8259>;
377 418
378 keyboard@0 { 419 keyboard@0 {
379 reg = <0>; 420 reg = <0x0>;
380 compatible = "pnpPNP,303"; 421 compatible = "pnpPNP,303";
381 }; 422 };
382 423
383 mouse@1 { 424 mouse@1 {
384 reg = <1>; 425 reg = <0x1>;
385 compatible = "pnpPNP,f03"; 426 compatible = "pnpPNP,f03";
386 }; 427 };
387 }; 428 };
388 429
389 rtc@70 { 430 rtc@70 {
390 compatible = "pnpPNP,b00"; 431 compatible = "pnpPNP,b00";
391 reg = <1 70 2>; 432 reg = <0x1 0x70 0x2>;
392 }; 433 };
393 434
394 gpio@400 { 435 gpio@400 {
395 reg = <1 400 80>; 436 reg = <0x1 0x400 0x80>;
396 }; 437 };
397 }; 438 };
398 }; 439 };
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-24 23:02:37 -0500