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-rw-r--r--arch/powerpc/boot/dts/mpc8544ds.dts377
1 files changed, 196 insertions, 181 deletions
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index 3e79bf0a3159..3f9d15cf13e0 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -30,7 +30,6 @@
30 timebase-frequency = <0>; 30 timebase-frequency = <0>;
31 bus-frequency = <0>; 31 bus-frequency = <0>;
32 clock-frequency = <0>; 32 clock-frequency = <0>;
33 32-bit;
34 }; 33 };
35 }; 34 };
36 35
@@ -42,19 +41,9 @@
42 soc8544@e0000000 { 41 soc8544@e0000000 {
43 #address-cells = <1>; 42 #address-cells = <1>;
44 #size-cells = <1>; 43 #size-cells = <1>;
45 #interrupt-cells = <2>;
46 device_type = "soc"; 44 device_type = "soc";
47 45
48 46 ranges = <00000000 e0000000 00100000>;
49 ranges = <00001000 e0001000 000ff000
50 80000000 80000000 20000000
51 a0000000 a0000000 10000000
52 b0000000 b0000000 00100000
53 c0000000 c0000000 20000000
54 b0100000 b0100000 00100000
55 e1000000 e1000000 00010000
56 e1010000 e1010000 00010000
57 e1020000 e1020000 00010000>;
58 reg = <e0000000 00001000>; // CCSRBAR 1M 47 reg = <e0000000 00001000>; // CCSRBAR 1M
59 bus-frequency = <0>; // Filled out by uboot. 48 bus-frequency = <0>; // Filled out by uboot.
60 49
@@ -149,115 +138,173 @@
149 interrupt-parent = <&mpic>; 138 interrupt-parent = <&mpic>;
150 }; 139 };
151 140
152 pci@8000 { 141 global-utilities@e0000 { //global utilities block
153 compatible = "fsl,mpc8540-pci"; 142 compatible = "fsl,mpc8548-guts";
154 device_type = "pci"; 143 reg = <e0000 1000>;
155 interrupt-map-mask = <f800 0 0 7>; 144 fsl,has-rstcr;
156 interrupt-map = < 145 };
157
158 /* IDSEL 0x11 J17 Slot 1 */
159 8800 0 0 1 &mpic 2 1
160 8800 0 0 2 &mpic 3 1
161 8800 0 0 3 &mpic 4 1
162 8800 0 0 4 &mpic 1 1
163 146
164 /* IDSEL 0x12 J16 Slot 2 */ 147 mpic: pic@40000 {
148 clock-frequency = <0>;
149 interrupt-controller;
150 #address-cells = <0>;
151 #interrupt-cells = <2>;
152 reg = <40000 40000>;
153 compatible = "chrp,open-pic";
154 device_type = "open-pic";
155 big-endian;
156 };
157 };
165 158
166 9000 0 0 1 &mpic 3 1 159 pci@e0008000 {
167 9000 0 0 2 &mpic 4 1 160 compatible = "fsl,mpc8540-pci";
168 9000 0 0 3 &mpic 2 1 161 device_type = "pci";
169 9000 0 0 4 &mpic 1 1>; 162 interrupt-map-mask = <f800 0 0 7>;
163 interrupt-map = <
164
165 /* IDSEL 0x11 J17 Slot 1 */
166 8800 0 0 1 &mpic 2 1
167 8800 0 0 2 &mpic 3 1
168 8800 0 0 3 &mpic 4 1
169 8800 0 0 4 &mpic 1 1
170
171 /* IDSEL 0x12 J16 Slot 2 */
172
173 9000 0 0 1 &mpic 3 1
174 9000 0 0 2 &mpic 4 1
175 9000 0 0 3 &mpic 2 1
176 9000 0 0 4 &mpic 1 1>;
177
178 interrupt-parent = <&mpic>;
179 interrupts = <18 2>;
180 bus-range = <0 ff>;
181 ranges = <02000000 0 c0000000 c0000000 0 20000000
182 01000000 0 00000000 e1000000 0 00010000>;
183 clock-frequency = <3f940aa>;
184 #interrupt-cells = <1>;
185 #size-cells = <2>;
186 #address-cells = <3>;
187 reg = <e0008000 1000>;
188 };
170 189
171 interrupt-parent = <&mpic>; 190 pcie@e0009000 {
172 interrupts = <18 2>; 191 compatible = "fsl,mpc8548-pcie";
173 bus-range = <0 ff>; 192 device_type = "pci";
174 ranges = <02000000 0 c0000000 c0000000 0 20000000 193 #interrupt-cells = <1>;
175 01000000 0 00000000 e1000000 0 00010000>; 194 #size-cells = <2>;
176 clock-frequency = <3f940aa>; 195 #address-cells = <3>;
177 #interrupt-cells = <1>; 196 reg = <e0009000 1000>;
197 bus-range = <0 ff>;
198 ranges = <02000000 0 80000000 80000000 0 20000000
199 01000000 0 00000000 e1010000 0 00010000>;
200 clock-frequency = <1fca055>;
201 interrupt-parent = <&mpic>;
202 interrupts = <1a 2>;
203 interrupt-map-mask = <f800 0 0 7>;
204 interrupt-map = <
205 /* IDSEL 0x0 */
206 0000 0 0 1 &mpic 4 1
207 0000 0 0 2 &mpic 5 1
208 0000 0 0 3 &mpic 6 1
209 0000 0 0 4 &mpic 7 1
210 >;
211 pcie@0 {
212 reg = <0 0 0 0 0>;
178 #size-cells = <2>; 213 #size-cells = <2>;
179 #address-cells = <3>; 214 #address-cells = <3>;
180 reg = <8000 1000>;
181 };
182
183 pcie@9000 {
184 compatible = "fsl,mpc8548-pcie";
185 device_type = "pci"; 215 device_type = "pci";
186 #interrupt-cells = <1>; 216 ranges = <02000000 0 80000000
187 #size-cells = <2>; 217 02000000 0 80000000
188 #address-cells = <3>; 218 0 20000000
189 reg = <9000 1000>; 219
190 bus-range = <0 ff>; 220 01000000 0 00000000
191 ranges = <02000000 0 80000000 80000000 0 20000000 221 01000000 0 00000000
192 01000000 0 00000000 e1010000 0 00010000>; 222 0 00010000>;
193 clock-frequency = <1fca055>;
194 interrupt-parent = <&mpic>;
195 interrupts = <1a 2>;
196 interrupt-map-mask = <f800 0 0 7>;
197 interrupt-map = <
198 /* IDSEL 0x0 */
199 0000 0 0 1 &mpic 4 1
200 0000 0 0 2 &mpic 5 1
201 0000 0 0 3 &mpic 6 1
202 0000 0 0 4 &mpic 7 1
203 >;
204 }; 223 };
224 };
205 225
206 pcie@a000 { 226 pcie@e000a000 {
207 compatible = "fsl,mpc8548-pcie"; 227 compatible = "fsl,mpc8548-pcie";
208 device_type = "pci"; 228 device_type = "pci";
209 #interrupt-cells = <1>; 229 #interrupt-cells = <1>;
230 #size-cells = <2>;
231 #address-cells = <3>;
232 reg = <e000a000 1000>;
233 bus-range = <0 ff>;
234 ranges = <02000000 0 a0000000 a0000000 0 10000000
235 01000000 0 00000000 e1020000 0 00010000>;
236 clock-frequency = <1fca055>;
237 interrupt-parent = <&mpic>;
238 interrupts = <19 2>;
239 interrupt-map-mask = <f800 0 0 7>;
240 interrupt-map = <
241 /* IDSEL 0x0 */
242 0000 0 0 1 &mpic 0 1
243 0000 0 0 2 &mpic 1 1
244 0000 0 0 3 &mpic 2 1
245 0000 0 0 4 &mpic 3 1
246 >;
247 pcie@0 {
248 reg = <0 0 0 0 0>;
210 #size-cells = <2>; 249 #size-cells = <2>;
211 #address-cells = <3>; 250 #address-cells = <3>;
212 reg = <a000 1000>; 251 device_type = "pci";
213 bus-range = <0 ff>; 252 ranges = <02000000 0 a0000000
214 ranges = <02000000 0 a0000000 a0000000 0 10000000 253 02000000 0 a0000000
215 01000000 0 00000000 e1020000 0 00010000>; 254 0 10000000
216 clock-frequency = <1fca055>; 255
217 interrupt-parent = <&mpic>; 256 01000000 0 00000000
218 interrupts = <19 2>; 257 01000000 0 00000000
219 interrupt-map-mask = <f800 0 0 7>; 258 0 00010000>;
220 interrupt-map = <
221 /* IDSEL 0x0 */
222 0000 0 0 1 &mpic 0 1
223 0000 0 0 2 &mpic 1 1
224 0000 0 0 3 &mpic 2 1
225 0000 0 0 4 &mpic 3 1
226 >;
227 }; 259 };
260 };
228 261
229 pcie@b000 { 262 pcie@e000b000 {
230 compatible = "fsl,mpc8548-pcie"; 263 compatible = "fsl,mpc8548-pcie";
231 device_type = "pci"; 264 device_type = "pci";
232 #interrupt-cells = <1>; 265 #interrupt-cells = <1>;
266 #size-cells = <2>;
267 #address-cells = <3>;
268 reg = <e000b000 1000>;
269 bus-range = <0 ff>;
270 ranges = <02000000 0 b0000000 b0000000 0 00100000
271 01000000 0 00000000 b0100000 0 00100000>;
272 clock-frequency = <1fca055>;
273 interrupt-parent = <&mpic>;
274 interrupts = <1b 2>;
275 interrupt-map-mask = <fb00 0 0 0>;
276 interrupt-map = <
277 // IDSEL 0x1c USB
278 e000 0 0 0 &i8259 c 2
279 e100 0 0 0 &i8259 9 2
280 e200 0 0 0 &i8259 a 2
281 e300 0 0 0 &i8259 b 2
282
283 // IDSEL 0x1d Audio
284 e800 0 0 0 &i8259 6 2
285
286 // IDSEL 0x1e Legacy
287 f000 0 0 0 &i8259 7 2
288 f100 0 0 0 &i8259 7 2
289
290 // IDSEL 0x1f IDE/SATA
291 f800 0 0 0 &i8259 e 2
292 f900 0 0 0 &i8259 5 2
293 >;
294
295 pcie@0 {
296 reg = <0 0 0 0 0>;
233 #size-cells = <2>; 297 #size-cells = <2>;
234 #address-cells = <3>; 298 #address-cells = <3>;
235 reg = <b000 1000>; 299 device_type = "pci";
236 bus-range = <0 ff>; 300 ranges = <02000000 0 b0000000
237 ranges = <02000000 0 b0000000 b0000000 0 00100000 301 02000000 0 b0000000
238 01000000 0 00000000 b0100000 0 00100000>; 302 0 00100000
239 clock-frequency = <1fca055>; 303
240 interrupt-parent = <&mpic>; 304 01000000 0 00000000
241 interrupts = <1b 2>; 305 01000000 0 00000000
242 interrupt-map-mask = <fb00 0 0 0>; 306 0 00100000>;
243 interrupt-map = < 307
244 // IDSEL 0x1c USB
245 e000 0 0 0 &i8259 c 2
246 e100 0 0 0 &i8259 9 2
247 e200 0 0 0 &i8259 a 2
248 e300 0 0 0 &i8259 b 2
249
250 // IDSEL 0x1d Audio
251 e800 0 0 0 &i8259 6 2
252
253 // IDSEL 0x1e Legacy
254 f000 0 0 0 &i8259 7 2
255 f100 0 0 0 &i8259 7 2
256
257 // IDSEL 0x1f IDE/SATA
258 f800 0 0 0 &i8259 e 2
259 f900 0 0 0 &i8259 5 2
260 >;
261 uli1575@0 { 308 uli1575@0 {
262 reg = <0 0 0 0 0>; 309 reg = <0 0 0 0 0>;
263 #size-cells = <2>; 310 #size-cells = <2>;
@@ -265,95 +312,63 @@
265 ranges = <02000000 0 b0000000 312 ranges = <02000000 0 b0000000
266 02000000 0 b0000000 313 02000000 0 b0000000
267 0 00100000 314 0 00100000
315
268 01000000 0 00000000 316 01000000 0 00000000
269 01000000 0 00000000 317 01000000 0 00000000
270 0 00100000>; 318 0 00100000>;
271 319 isa@1e {
272 pci_bridge@0 { 320 device_type = "isa";
273 reg = <0 0 0 0 0>; 321 #interrupt-cells = <2>;
274 #size-cells = <2>; 322 #size-cells = <1>;
275 #address-cells = <3>; 323 #address-cells = <2>;
276 ranges = <02000000 0 b0000000 324 reg = <f000 0 0 0 0>;
277 02000000 0 b0000000 325 ranges = <1 0
278 0 00100000 326 01000000 0 0
279 01000000 0 00000000 327 00001000>;
280 01000000 0 00000000 328 interrupt-parent = <&i8259>;
281 0 00100000>; 329
282 330 i8259: interrupt-controller@20 {
283 isa@1e { 331 reg = <1 20 2
284 device_type = "isa"; 332 1 a0 2
333 1 4d0 2>;
334 interrupt-controller;
335 device_type = "interrupt-controller";
336 #address-cells = <0>;
285 #interrupt-cells = <2>; 337 #interrupt-cells = <2>;
286 #size-cells = <1>; 338 compatible = "chrp,iic";
287 #address-cells = <2>; 339 interrupts = <9 2>;
288 reg = <f000 0 0 0 0>; 340 interrupt-parent = <&mpic>;
289 ranges = <1 0 341 };
290 01000000 0 0 342
291 00001000>; 343 i8042@60 {
344 #size-cells = <0>;
345 #address-cells = <1>;
346 reg = <1 60 1 1 64 1>;
347 interrupts = <1 3 c 3>;
292 interrupt-parent = <&i8259>; 348 interrupt-parent = <&i8259>;
293 349
294 i8259: interrupt-controller@20 { 350 keyboard@0 {
295 reg = <1 20 2 351 reg = <0>;
296 1 a0 2 352 compatible = "pnpPNP,303";
297 1 4d0 2>;
298 clock-frequency = <0>;
299 interrupt-controller;
300 device_type = "interrupt-controller";
301 #address-cells = <0>;
302 #interrupt-cells = <2>;
303 built-in;
304 compatible = "chrp,iic";
305 interrupts = <9 2>;
306 interrupt-parent = <&mpic>;
307 }; 353 };
308 354
309 i8042@60 { 355 mouse@1 {
310 #size-cells = <0>; 356 reg = <1>;
311 #address-cells = <1>; 357 compatible = "pnpPNP,f03";
312 reg = <1 60 1 1 64 1>;
313 interrupts = <1 3 c 3>;
314 interrupt-parent = <&i8259>;
315
316 keyboard@0 {
317 reg = <0>;
318 compatible = "pnpPNP,303";
319 };
320
321 mouse@1 {
322 reg = <1>;
323 compatible = "pnpPNP,f03";
324 };
325 }; 358 };
359 };
326 360
327 rtc@70 { 361 rtc@70 {
328 compatible = "pnpPNP,b00"; 362 compatible = "pnpPNP,b00";
329 reg = <1 70 2>; 363 reg = <1 70 2>;
330 }; 364 };
331 365
332 gpio@400 { 366 gpio@400 {
333 reg = <1 400 80>; 367 reg = <1 400 80>;
334 };
335 }; 368 };
336 }; 369 };
337 }; 370 };
338
339 }; 371 };
340 372
341 global-utilities@e0000 { //global utilities block
342 compatible = "fsl,mpc8548-guts";
343 reg = <e0000 1000>;
344 fsl,has-rstcr;
345 };
346
347 mpic: pic@40000 {
348 clock-frequency = <0>;
349 interrupt-controller;
350 #address-cells = <0>;
351 #interrupt-cells = <2>;
352 reg = <40000 40000>;
353 built-in;
354 compatible = "chrp,open-pic";
355 device_type = "open-pic";
356 big-endian;
357 };
358 }; 373 };
359}; 374};
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-04 16:37:52 -0500