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-rw-r--r--arch/powerpc/boot/dts/mpc8544ds.dts372
1 files changed, 196 insertions, 176 deletions
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index 88082ac6f2cd..3f9d15cf13e0 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -43,16 +43,7 @@
43 #size-cells = <1>; 43 #size-cells = <1>;
44 device_type = "soc"; 44 device_type = "soc";
45 45
46 46 ranges = <00000000 e0000000 00100000>;
47 ranges = <00001000 e0001000 000ff000
48 80000000 80000000 20000000
49 a0000000 a0000000 10000000
50 b0000000 b0000000 00100000
51 c0000000 c0000000 20000000
52 b0100000 b0100000 00100000
53 e1000000 e1000000 00010000
54 e1010000 e1010000 00010000
55 e1020000 e1020000 00010000>;
56 reg = <e0000000 00001000>; // CCSRBAR 1M 47 reg = <e0000000 00001000>; // CCSRBAR 1M
57 bus-frequency = <0>; // Filled out by uboot. 48 bus-frequency = <0>; // Filled out by uboot.
58 49
@@ -147,115 +138,173 @@
147 interrupt-parent = <&mpic>; 138 interrupt-parent = <&mpic>;
148 }; 139 };
149 140
150 pci@8000 { 141 global-utilities@e0000 { //global utilities block
151 compatible = "fsl,mpc8540-pci"; 142 compatible = "fsl,mpc8548-guts";
152 device_type = "pci"; 143 reg = <e0000 1000>;
153 interrupt-map-mask = <f800 0 0 7>; 144 fsl,has-rstcr;
154 interrupt-map = < 145 };
155
156 /* IDSEL 0x11 J17 Slot 1 */
157 8800 0 0 1 &mpic 2 1
158 8800 0 0 2 &mpic 3 1
159 8800 0 0 3 &mpic 4 1
160 8800 0 0 4 &mpic 1 1
161 146
162 /* IDSEL 0x12 J16 Slot 2 */ 147 mpic: pic@40000 {
148 clock-frequency = <0>;
149 interrupt-controller;
150 #address-cells = <0>;
151 #interrupt-cells = <2>;
152 reg = <40000 40000>;
153 compatible = "chrp,open-pic";
154 device_type = "open-pic";
155 big-endian;
156 };
157 };
163 158
164 9000 0 0 1 &mpic 3 1 159 pci@e0008000 {
165 9000 0 0 2 &mpic 4 1 160 compatible = "fsl,mpc8540-pci";
166 9000 0 0 3 &mpic 2 1 161 device_type = "pci";
167 9000 0 0 4 &mpic 1 1>; 162 interrupt-map-mask = <f800 0 0 7>;
163 interrupt-map = <
164
165 /* IDSEL 0x11 J17 Slot 1 */
166 8800 0 0 1 &mpic 2 1
167 8800 0 0 2 &mpic 3 1
168 8800 0 0 3 &mpic 4 1
169 8800 0 0 4 &mpic 1 1
170
171 /* IDSEL 0x12 J16 Slot 2 */
172
173 9000 0 0 1 &mpic 3 1
174 9000 0 0 2 &mpic 4 1
175 9000 0 0 3 &mpic 2 1
176 9000 0 0 4 &mpic 1 1>;
177
178 interrupt-parent = <&mpic>;
179 interrupts = <18 2>;
180 bus-range = <0 ff>;
181 ranges = <02000000 0 c0000000 c0000000 0 20000000
182 01000000 0 00000000 e1000000 0 00010000>;
183 clock-frequency = <3f940aa>;
184 #interrupt-cells = <1>;
185 #size-cells = <2>;
186 #address-cells = <3>;
187 reg = <e0008000 1000>;
188 };
168 189
169 interrupt-parent = <&mpic>; 190 pcie@e0009000 {
170 interrupts = <18 2>; 191 compatible = "fsl,mpc8548-pcie";
171 bus-range = <0 ff>; 192 device_type = "pci";
172 ranges = <02000000 0 c0000000 c0000000 0 20000000 193 #interrupt-cells = <1>;
173 01000000 0 00000000 e1000000 0 00010000>; 194 #size-cells = <2>;
174 clock-frequency = <3f940aa>; 195 #address-cells = <3>;
175 #interrupt-cells = <1>; 196 reg = <e0009000 1000>;
197 bus-range = <0 ff>;
198 ranges = <02000000 0 80000000 80000000 0 20000000
199 01000000 0 00000000 e1010000 0 00010000>;
200 clock-frequency = <1fca055>;
201 interrupt-parent = <&mpic>;
202 interrupts = <1a 2>;
203 interrupt-map-mask = <f800 0 0 7>;
204 interrupt-map = <
205 /* IDSEL 0x0 */
206 0000 0 0 1 &mpic 4 1
207 0000 0 0 2 &mpic 5 1
208 0000 0 0 3 &mpic 6 1
209 0000 0 0 4 &mpic 7 1
210 >;
211 pcie@0 {
212 reg = <0 0 0 0 0>;
176 #size-cells = <2>; 213 #size-cells = <2>;
177 #address-cells = <3>; 214 #address-cells = <3>;
178 reg = <8000 1000>;
179 };
180
181 pcie@9000 {
182 compatible = "fsl,mpc8548-pcie";
183 device_type = "pci"; 215 device_type = "pci";
184 #interrupt-cells = <1>; 216 ranges = <02000000 0 80000000
185 #size-cells = <2>; 217 02000000 0 80000000
186 #address-cells = <3>; 218 0 20000000
187 reg = <9000 1000>; 219
188 bus-range = <0 ff>; 220 01000000 0 00000000
189 ranges = <02000000 0 80000000 80000000 0 20000000 221 01000000 0 00000000
190 01000000 0 00000000 e1010000 0 00010000>; 222 0 00010000>;
191 clock-frequency = <1fca055>;
192 interrupt-parent = <&mpic>;
193 interrupts = <1a 2>;
194 interrupt-map-mask = <f800 0 0 7>;
195 interrupt-map = <
196 /* IDSEL 0x0 */
197 0000 0 0 1 &mpic 4 1
198 0000 0 0 2 &mpic 5 1
199 0000 0 0 3 &mpic 6 1
200 0000 0 0 4 &mpic 7 1
201 >;
202 }; 223 };
224 };
203 225
204 pcie@a000 { 226 pcie@e000a000 {
205 compatible = "fsl,mpc8548-pcie"; 227 compatible = "fsl,mpc8548-pcie";
206 device_type = "pci"; 228 device_type = "pci";
207 #interrupt-cells = <1>; 229 #interrupt-cells = <1>;
230 #size-cells = <2>;
231 #address-cells = <3>;
232 reg = <e000a000 1000>;
233 bus-range = <0 ff>;
234 ranges = <02000000 0 a0000000 a0000000 0 10000000
235 01000000 0 00000000 e1020000 0 00010000>;
236 clock-frequency = <1fca055>;
237 interrupt-parent = <&mpic>;
238 interrupts = <19 2>;
239 interrupt-map-mask = <f800 0 0 7>;
240 interrupt-map = <
241 /* IDSEL 0x0 */
242 0000 0 0 1 &mpic 0 1
243 0000 0 0 2 &mpic 1 1
244 0000 0 0 3 &mpic 2 1
245 0000 0 0 4 &mpic 3 1
246 >;
247 pcie@0 {
248 reg = <0 0 0 0 0>;
208 #size-cells = <2>; 249 #size-cells = <2>;
209 #address-cells = <3>; 250 #address-cells = <3>;
210 reg = <a000 1000>; 251 device_type = "pci";
211 bus-range = <0 ff>; 252 ranges = <02000000 0 a0000000
212 ranges = <02000000 0 a0000000 a0000000 0 10000000 253 02000000 0 a0000000
213 01000000 0 00000000 e1020000 0 00010000>; 254 0 10000000
214 clock-frequency = <1fca055>; 255
215 interrupt-parent = <&mpic>; 256 01000000 0 00000000
216 interrupts = <19 2>; 257 01000000 0 00000000
217 interrupt-map-mask = <f800 0 0 7>; 258 0 00010000>;
218 interrupt-map = <
219 /* IDSEL 0x0 */
220 0000 0 0 1 &mpic 0 1
221 0000 0 0 2 &mpic 1 1
222 0000 0 0 3 &mpic 2 1
223 0000 0 0 4 &mpic 3 1
224 >;
225 }; 259 };
260 };
226 261
227 pcie@b000 { 262 pcie@e000b000 {
228 compatible = "fsl,mpc8548-pcie"; 263 compatible = "fsl,mpc8548-pcie";
229 device_type = "pci"; 264 device_type = "pci";
230 #interrupt-cells = <1>; 265 #interrupt-cells = <1>;
266 #size-cells = <2>;
267 #address-cells = <3>;
268 reg = <e000b000 1000>;
269 bus-range = <0 ff>;
270 ranges = <02000000 0 b0000000 b0000000 0 00100000
271 01000000 0 00000000 b0100000 0 00100000>;
272 clock-frequency = <1fca055>;
273 interrupt-parent = <&mpic>;
274 interrupts = <1b 2>;
275 interrupt-map-mask = <fb00 0 0 0>;
276 interrupt-map = <
277 // IDSEL 0x1c USB
278 e000 0 0 0 &i8259 c 2
279 e100 0 0 0 &i8259 9 2
280 e200 0 0 0 &i8259 a 2
281 e300 0 0 0 &i8259 b 2
282
283 // IDSEL 0x1d Audio
284 e800 0 0 0 &i8259 6 2
285
286 // IDSEL 0x1e Legacy
287 f000 0 0 0 &i8259 7 2
288 f100 0 0 0 &i8259 7 2
289
290 // IDSEL 0x1f IDE/SATA
291 f800 0 0 0 &i8259 e 2
292 f900 0 0 0 &i8259 5 2
293 >;
294
295 pcie@0 {
296 reg = <0 0 0 0 0>;
231 #size-cells = <2>; 297 #size-cells = <2>;
232 #address-cells = <3>; 298 #address-cells = <3>;
233 reg = <b000 1000>; 299 device_type = "pci";
234 bus-range = <0 ff>; 300 ranges = <02000000 0 b0000000
235 ranges = <02000000 0 b0000000 b0000000 0 00100000 301 02000000 0 b0000000
236 01000000 0 00000000 b0100000 0 00100000>; 302 0 00100000
237 clock-frequency = <1fca055>; 303
238 interrupt-parent = <&mpic>; 304 01000000 0 00000000
239 interrupts = <1b 2>; 305 01000000 0 00000000
240 interrupt-map-mask = <fb00 0 0 0>; 306 0 00100000>;
241 interrupt-map = < 307
242 // IDSEL 0x1c USB
243 e000 0 0 0 &i8259 c 2
244 e100 0 0 0 &i8259 9 2
245 e200 0 0 0 &i8259 a 2
246 e300 0 0 0 &i8259 b 2
247
248 // IDSEL 0x1d Audio
249 e800 0 0 0 &i8259 6 2
250
251 // IDSEL 0x1e Legacy
252 f000 0 0 0 &i8259 7 2
253 f100 0 0 0 &i8259 7 2
254
255 // IDSEL 0x1f IDE/SATA
256 f800 0 0 0 &i8259 e 2
257 f900 0 0 0 &i8259 5 2
258 >;
259 uli1575@0 { 308 uli1575@0 {
260 reg = <0 0 0 0 0>; 309 reg = <0 0 0 0 0>;
261 #size-cells = <2>; 310 #size-cells = <2>;
@@ -263,92 +312,63 @@
263 ranges = <02000000 0 b0000000 312 ranges = <02000000 0 b0000000
264 02000000 0 b0000000 313 02000000 0 b0000000
265 0 00100000 314 0 00100000
315
266 01000000 0 00000000 316 01000000 0 00000000
267 01000000 0 00000000 317 01000000 0 00000000
268 0 00100000>; 318 0 00100000>;
269 319 isa@1e {
270 pci_bridge@0 { 320 device_type = "isa";
271 reg = <0 0 0 0 0>; 321 #interrupt-cells = <2>;
272 #size-cells = <2>; 322 #size-cells = <1>;
273 #address-cells = <3>; 323 #address-cells = <2>;
274 ranges = <02000000 0 b0000000 324 reg = <f000 0 0 0 0>;
275 02000000 0 b0000000 325 ranges = <1 0
276 0 00100000 326 01000000 0 0
277 01000000 0 00000000 327 00001000>;
278 01000000 0 00000000 328 interrupt-parent = <&i8259>;
279 0 00100000>; 329
280 330 i8259: interrupt-controller@20 {
281 isa@1e { 331 reg = <1 20 2
282 device_type = "isa"; 332 1 a0 2
333 1 4d0 2>;
334 interrupt-controller;
335 device_type = "interrupt-controller";
336 #address-cells = <0>;
283 #interrupt-cells = <2>; 337 #interrupt-cells = <2>;
284 #size-cells = <1>; 338 compatible = "chrp,iic";
285 #address-cells = <2>; 339 interrupts = <9 2>;
286 reg = <f000 0 0 0 0>; 340 interrupt-parent = <&mpic>;
287 ranges = <1 0 341 };
288 01000000 0 0 342
289 00001000>; 343 i8042@60 {
344 #size-cells = <0>;
345 #address-cells = <1>;
346 reg = <1 60 1 1 64 1>;
347 interrupts = <1 3 c 3>;
290 interrupt-parent = <&i8259>; 348 interrupt-parent = <&i8259>;
291 349
292 i8259: interrupt-controller@20 { 350 keyboard@0 {
293 reg = <1 20 2 351 reg = <0>;
294 1 a0 2 352 compatible = "pnpPNP,303";
295 1 4d0 2>;
296 interrupt-controller;
297 device_type = "interrupt-controller";
298 #address-cells = <0>;
299 #interrupt-cells = <2>;
300 compatible = "chrp,iic";
301 interrupts = <9 2>;
302 interrupt-parent = <&mpic>;
303 }; 353 };
304 354
305 i8042@60 { 355 mouse@1 {
306 #size-cells = <0>; 356 reg = <1>;
307 #address-cells = <1>; 357 compatible = "pnpPNP,f03";
308 reg = <1 60 1 1 64 1>;
309 interrupts = <1 3 c 3>;
310 interrupt-parent = <&i8259>;
311
312 keyboard@0 {
313 reg = <0>;
314 compatible = "pnpPNP,303";
315 };
316
317 mouse@1 {
318 reg = <1>;
319 compatible = "pnpPNP,f03";
320 };
321 }; 358 };
359 };
322 360
323 rtc@70 { 361 rtc@70 {
324 compatible = "pnpPNP,b00"; 362 compatible = "pnpPNP,b00";
325 reg = <1 70 2>; 363 reg = <1 70 2>;
326 }; 364 };
327 365
328 gpio@400 { 366 gpio@400 {
329 reg = <1 400 80>; 367 reg = <1 400 80>;
330 };
331 }; 368 };
332 }; 369 };
333 }; 370 };
334
335 }; 371 };
336 372
337 global-utilities@e0000 { //global utilities block
338 compatible = "fsl,mpc8548-guts";
339 reg = <e0000 1000>;
340 fsl,has-rstcr;
341 };
342
343 mpic: pic@40000 {
344 clock-frequency = <0>;
345 interrupt-controller;
346 #address-cells = <0>;
347 #interrupt-cells = <2>;
348 reg = <40000 40000>;
349 compatible = "chrp,open-pic";
350 device_type = "open-pic";
351 big-endian;
352 };
353 }; 373 };
354}; 374};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-13 22:06:00 -0500