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-rw-r--r--arch/powerpc/boot/dts/mpc8541cds.dts161
1 files changed, 81 insertions, 80 deletions
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index fa8d9aaad157..663c7c50ca45 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8541 CDS Device Tree Source 2 * MPC8541 CDS Device Tree Source
3 * 3 *
4 * Copyright 2006 Freescale Semiconductor Inc. 4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,6 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
12 13
13/ { 14/ {
14 model = "MPC8541CDS"; 15 model = "MPC8541CDS";
@@ -31,11 +32,11 @@
31 32
32 PowerPC,8541@0 { 33 PowerPC,8541@0 {
33 device_type = "cpu"; 34 device_type = "cpu";
34 reg = <0>; 35 reg = <0x0>;
35 d-cache-line-size = <20>; // 32 bytes 36 d-cache-line-size = <32>; // 32 bytes
36 i-cache-line-size = <20>; // 32 bytes 37 i-cache-line-size = <32>; // 32 bytes
37 d-cache-size = <8000>; // L1, 32K 38 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <8000>; // L1, 32K 39 i-cache-size = <0x8000>; // L1, 32K
39 timebase-frequency = <0>; // 33 MHz, from uboot 40 timebase-frequency = <0>; // 33 MHz, from uboot
40 bus-frequency = <0>; // 166 MHz 41 bus-frequency = <0>; // 166 MHz
41 clock-frequency = <0>; // 825 MHz, from uboot 42 clock-frequency = <0>; // 825 MHz, from uboot
@@ -44,31 +45,31 @@
44 45
45 memory { 46 memory {
46 device_type = "memory"; 47 device_type = "memory";
47 reg = <00000000 08000000>; // 128M at 0x0 48 reg = <0x0 0x8000000>; // 128M at 0x0
48 }; 49 };
49 50
50 soc8541@e0000000 { 51 soc8541@e0000000 {
51 #address-cells = <1>; 52 #address-cells = <1>;
52 #size-cells = <1>; 53 #size-cells = <1>;
53 device_type = "soc"; 54 device_type = "soc";
54 ranges = <0 e0000000 00100000>; 55 ranges = <0x0 0xe0000000 0x100000>;
55 reg = <e0000000 00001000>; // CCSRBAR 1M 56 reg = <0xe0000000 0x1000>; // CCSRBAR 1M
56 bus-frequency = <0>; 57 bus-frequency = <0>;
57 58
58 memory-controller@2000 { 59 memory-controller@2000 {
59 compatible = "fsl,8541-memory-controller"; 60 compatible = "fsl,8541-memory-controller";
60 reg = <2000 1000>; 61 reg = <0x2000 0x1000>;
61 interrupt-parent = <&mpic>; 62 interrupt-parent = <&mpic>;
62 interrupts = <12 2>; 63 interrupts = <18 2>;
63 }; 64 };
64 65
65 l2-cache-controller@20000 { 66 l2-cache-controller@20000 {
66 compatible = "fsl,8541-l2-cache-controller"; 67 compatible = "fsl,8541-l2-cache-controller";
67 reg = <20000 1000>; 68 reg = <0x20000 0x1000>;
68 cache-line-size = <20>; // 32 bytes 69 cache-line-size = <32>; // 32 bytes
69 cache-size = <40000>; // L2, 256K 70 cache-size = <0x40000>; // L2, 256K
70 interrupt-parent = <&mpic>; 71 interrupt-parent = <&mpic>;
71 interrupts = <10 2>; 72 interrupts = <16 2>;
72 }; 73 };
73 74
74 i2c@3000 { 75 i2c@3000 {
@@ -76,8 +77,8 @@
76 #size-cells = <0>; 77 #size-cells = <0>;
77 cell-index = <0>; 78 cell-index = <0>;
78 compatible = "fsl-i2c"; 79 compatible = "fsl-i2c";
79 reg = <3000 100>; 80 reg = <0x3000 0x100>;
80 interrupts = <2b 2>; 81 interrupts = <43 2>;
81 interrupt-parent = <&mpic>; 82 interrupt-parent = <&mpic>;
82 dfsrr; 83 dfsrr;
83 }; 84 };
@@ -86,18 +87,18 @@
86 #address-cells = <1>; 87 #address-cells = <1>;
87 #size-cells = <0>; 88 #size-cells = <0>;
88 compatible = "fsl,gianfar-mdio"; 89 compatible = "fsl,gianfar-mdio";
89 reg = <24520 20>; 90 reg = <0x24520 0x20>;
90 91
91 phy0: ethernet-phy@0 { 92 phy0: ethernet-phy@0 {
92 interrupt-parent = <&mpic>; 93 interrupt-parent = <&mpic>;
93 interrupts = <5 1>; 94 interrupts = <5 1>;
94 reg = <0>; 95 reg = <0x0>;
95 device_type = "ethernet-phy"; 96 device_type = "ethernet-phy";
96 }; 97 };
97 phy1: ethernet-phy@1 { 98 phy1: ethernet-phy@1 {
98 interrupt-parent = <&mpic>; 99 interrupt-parent = <&mpic>;
99 interrupts = <5 1>; 100 interrupts = <5 1>;
100 reg = <1>; 101 reg = <0x1>;
101 device_type = "ethernet-phy"; 102 device_type = "ethernet-phy";
102 }; 103 };
103 }; 104 };
@@ -107,9 +108,9 @@
107 device_type = "network"; 108 device_type = "network";
108 model = "TSEC"; 109 model = "TSEC";
109 compatible = "gianfar"; 110 compatible = "gianfar";
110 reg = <24000 1000>; 111 reg = <0x24000 0x1000>;
111 local-mac-address = [ 00 00 00 00 00 00 ]; 112 local-mac-address = [ 00 00 00 00 00 00 ];
112 interrupts = <1d 2 1e 2 22 2>; 113 interrupts = <29 2 30 2 34 2>;
113 interrupt-parent = <&mpic>; 114 interrupt-parent = <&mpic>;
114 phy-handle = <&phy0>; 115 phy-handle = <&phy0>;
115 }; 116 };
@@ -119,9 +120,9 @@
119 device_type = "network"; 120 device_type = "network";
120 model = "TSEC"; 121 model = "TSEC";
121 compatible = "gianfar"; 122 compatible = "gianfar";
122 reg = <25000 1000>; 123 reg = <0x25000 0x1000>;
123 local-mac-address = [ 00 00 00 00 00 00 ]; 124 local-mac-address = [ 00 00 00 00 00 00 ];
124 interrupts = <23 2 24 2 28 2>; 125 interrupts = <35 2 36 2 40 2>;
125 interrupt-parent = <&mpic>; 126 interrupt-parent = <&mpic>;
126 phy-handle = <&phy1>; 127 phy-handle = <&phy1>;
127 }; 128 };
@@ -130,9 +131,9 @@
130 cell-index = <0>; 131 cell-index = <0>;
131 device_type = "serial"; 132 device_type = "serial";
132 compatible = "ns16550"; 133 compatible = "ns16550";
133 reg = <4500 100>; // reg base, size 134 reg = <0x4500 0x100>; // reg base, size
134 clock-frequency = <0>; // should we fill in in uboot? 135 clock-frequency = <0>; // should we fill in in uboot?
135 interrupts = <2a 2>; 136 interrupts = <42 2>;
136 interrupt-parent = <&mpic>; 137 interrupt-parent = <&mpic>;
137 }; 138 };
138 139
@@ -140,9 +141,9 @@
140 cell-index = <1>; 141 cell-index = <1>;
141 device_type = "serial"; 142 device_type = "serial";
142 compatible = "ns16550"; 143 compatible = "ns16550";
143 reg = <4600 100>; // reg base, size 144 reg = <0x4600 0x100>; // reg base, size
144 clock-frequency = <0>; // should we fill in in uboot? 145 clock-frequency = <0>; // should we fill in in uboot?
145 interrupts = <2a 2>; 146 interrupts = <42 2>;
146 interrupt-parent = <&mpic>; 147 interrupt-parent = <&mpic>;
147 }; 148 };
148 149
@@ -151,7 +152,7 @@
151 interrupt-controller; 152 interrupt-controller;
152 #address-cells = <0>; 153 #address-cells = <0>;
153 #interrupt-cells = <2>; 154 #interrupt-cells = <2>;
154 reg = <40000 40000>; 155 reg = <0x40000 0x40000>;
155 compatible = "chrp,open-pic"; 156 compatible = "chrp,open-pic";
156 device_type = "open-pic"; 157 device_type = "open-pic";
157 big-endian; 158 big-endian;
@@ -161,17 +162,17 @@
161 #address-cells = <1>; 162 #address-cells = <1>;
162 #size-cells = <1>; 163 #size-cells = <1>;
163 compatible = "fsl,mpc8541-cpm", "fsl,cpm2"; 164 compatible = "fsl,mpc8541-cpm", "fsl,cpm2";
164 reg = <919c0 30>; 165 reg = <0x919c0 0x30>;
165 ranges; 166 ranges;
166 167
167 muram@80000 { 168 muram@80000 {
168 #address-cells = <1>; 169 #address-cells = <1>;
169 #size-cells = <1>; 170 #size-cells = <1>;
170 ranges = <0 80000 10000>; 171 ranges = <0x0 0x80000 0x10000>;
171 172
172 data@0 { 173 data@0 {
173 compatible = "fsl,cpm-muram-data"; 174 compatible = "fsl,cpm-muram-data";
174 reg = <0 2000 9000 1000>; 175 reg = <0x0 0x2000 0x9000 0x1000>;
175 }; 176 };
176 }; 177 };
177 178
@@ -179,16 +180,16 @@
179 compatible = "fsl,mpc8541-brg", 180 compatible = "fsl,mpc8541-brg",
180 "fsl,cpm2-brg", 181 "fsl,cpm2-brg",
181 "fsl,cpm-brg"; 182 "fsl,cpm-brg";
182 reg = <919f0 10 915f0 10>; 183 reg = <0x919f0 0x10 0x915f0 0x10>;
183 }; 184 };
184 185
185 cpmpic: pic@90c00 { 186 cpmpic: pic@90c00 {
186 interrupt-controller; 187 interrupt-controller;
187 #address-cells = <0>; 188 #address-cells = <0>;
188 #interrupt-cells = <2>; 189 #interrupt-cells = <2>;
189 interrupts = <2e 2>; 190 interrupts = <46 2>;
190 interrupt-parent = <&mpic>; 191 interrupt-parent = <&mpic>;
191 reg = <90c00 80>; 192 reg = <0x90c00 0x80>;
192 compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic"; 193 compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic";
193 }; 194 };
194 }; 195 };
@@ -196,68 +197,68 @@
196 197
197 pci0: pci@e0008000 { 198 pci0: pci@e0008000 {
198 cell-index = <0>; 199 cell-index = <0>;
199 interrupt-map-mask = <1f800 0 0 7>; 200 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
200 interrupt-map = < 201 interrupt-map = <
201 202
202 /* IDSEL 0x10 */ 203 /* IDSEL 0x10 */
203 08000 0 0 1 &mpic 0 1 204 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
204 08000 0 0 2 &mpic 1 1 205 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
205 08000 0 0 3 &mpic 2 1 206 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
206 08000 0 0 4 &mpic 3 1 207 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
207 208
208 /* IDSEL 0x11 */ 209 /* IDSEL 0x11 */
209 08800 0 0 1 &mpic 0 1 210 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
210 08800 0 0 2 &mpic 1 1 211 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
211 08800 0 0 3 &mpic 2 1 212 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
212 08800 0 0 4 &mpic 3 1 213 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
213 214
214 /* IDSEL 0x12 (Slot 1) */ 215 /* IDSEL 0x12 (Slot 1) */
215 09000 0 0 1 &mpic 0 1 216 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
216 09000 0 0 2 &mpic 1 1 217 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
217 09000 0 0 3 &mpic 2 1 218 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
218 09000 0 0 4 &mpic 3 1 219 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
219 220
220 /* IDSEL 0x13 (Slot 2) */ 221 /* IDSEL 0x13 (Slot 2) */
221 09800 0 0 1 &mpic 1 1 222 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
222 09800 0 0 2 &mpic 2 1 223 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
223 09800 0 0 3 &mpic 3 1 224 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
224 09800 0 0 4 &mpic 0 1 225 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
225 226
226 /* IDSEL 0x14 (Slot 3) */ 227 /* IDSEL 0x14 (Slot 3) */
227 0a000 0 0 1 &mpic 2 1 228 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
228 0a000 0 0 2 &mpic 3 1 229 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
229 0a000 0 0 3 &mpic 0 1 230 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
230 0a000 0 0 4 &mpic 1 1 231 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
231 232
232 /* IDSEL 0x15 (Slot 4) */ 233 /* IDSEL 0x15 (Slot 4) */
233 0a800 0 0 1 &mpic 3 1 234 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
234 0a800 0 0 2 &mpic 0 1 235 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
235 0a800 0 0 3 &mpic 1 1 236 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
236 0a800 0 0 4 &mpic 2 1 237 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
237 238
238 /* Bus 1 (Tundra Bridge) */ 239 /* Bus 1 (Tundra Bridge) */
239 /* IDSEL 0x12 (ISA bridge) */ 240 /* IDSEL 0x12 (ISA bridge) */
240 19000 0 0 1 &mpic 0 1 241 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
241 19000 0 0 2 &mpic 1 1 242 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
242 19000 0 0 3 &mpic 2 1 243 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
243 19000 0 0 4 &mpic 3 1>; 244 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
244 interrupt-parent = <&mpic>; 245 interrupt-parent = <&mpic>;
245 interrupts = <18 2>; 246 interrupts = <24 2>;
246 bus-range = <0 0>; 247 bus-range = <0 0>;
247 ranges = <02000000 0 80000000 80000000 0 20000000 248 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
248 01000000 0 00000000 e2000000 0 00100000>; 249 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
249 clock-frequency = <3f940aa>; 250 clock-frequency = <66666666>;
250 #interrupt-cells = <1>; 251 #interrupt-cells = <1>;
251 #size-cells = <2>; 252 #size-cells = <2>;
252 #address-cells = <3>; 253 #address-cells = <3>;
253 reg = <e0008000 1000>; 254 reg = <0xe0008000 0x1000>;
254 compatible = "fsl,mpc8540-pci"; 255 compatible = "fsl,mpc8540-pci";
255 device_type = "pci"; 256 device_type = "pci";
256 257
257 i8259@19000 { 258 i8259@19000 {
258 interrupt-controller; 259 interrupt-controller;
259 device_type = "interrupt-controller"; 260 device_type = "interrupt-controller";
260 reg = <19000 0 0 0 1>; 261 reg = <0x19000 0x0 0x0 0x0 0x1>;
261 #address-cells = <0>; 262 #address-cells = <0>;
262 #interrupt-cells = <2>; 263 #interrupt-cells = <2>;
263 compatible = "chrp,iic"; 264 compatible = "chrp,iic";
@@ -268,24 +269,24 @@
268 269
269 pci1: pci@e0009000 { 270 pci1: pci@e0009000 {
270 cell-index = <1>; 271 cell-index = <1>;
271 interrupt-map-mask = <f800 0 0 7>; 272 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
272 interrupt-map = < 273 interrupt-map = <
273 274
274 /* IDSEL 0x15 */ 275 /* IDSEL 0x15 */
275 a800 0 0 1 &mpic b 1 276 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
276 a800 0 0 2 &mpic b 1 277 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
277 a800 0 0 3 &mpic b 1 278 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
278 a800 0 0 4 &mpic b 1>; 279 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
279 interrupt-parent = <&mpic>; 280 interrupt-parent = <&mpic>;
280 interrupts = <19 2>; 281 interrupts = <25 2>;
281 bus-range = <0 0>; 282 bus-range = <0 0>;
282 ranges = <02000000 0 a0000000 a0000000 0 20000000 283 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
283 01000000 0 00000000 e3000000 0 00100000>; 284 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
284 clock-frequency = <3f940aa>; 285 clock-frequency = <66666666>;
285 #interrupt-cells = <1>; 286 #interrupt-cells = <1>;
286 #size-cells = <2>; 287 #size-cells = <2>;
287 #address-cells = <3>; 288 #address-cells = <3>;
288 reg = <e0009000 1000>; 289 reg = <0xe0009000 0x1000>;
289 compatible = "fsl,mpc8540-pci"; 290 compatible = "fsl,mpc8540-pci";
290 device_type = "pci"; 291 device_type = "pci";
291 }; 292 };
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-06 10:34:28 -0400