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-rw-r--r--arch/powerpc/boot/dts/mpc8536ds.dts420
1 files changed, 420 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dts b/arch/powerpc/boot/dts/mpc8536ds.dts
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+++ b/arch/powerpc/boot/dts/mpc8536ds.dts
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1/*
2 * MPC8536 DS Device Tree Source
3 *
4 * Copyright 2008 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 model = "fsl,mpc8536ds";
16 compatible = "fsl,mpc8536ds";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 pci1 = &pci1;
27 pci2 = &pci2;
28 pci3 = &pci3;
29 };
30
31 cpus {
32 #cpus = <1>;
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 PowerPC,8536@0 {
37 device_type = "cpu";
38 reg = <0>;
39 next-level-cache = <&L2>;
40 };
41 };
42
43 memory {
44 device_type = "memory";
45 reg = <00000000 00000000>; // Filled by U-Boot
46 };
47
48 soc@ffe00000 {
49 #address-cells = <1>;
50 #size-cells = <1>;
51 device_type = "soc";
52 ranges = <0x0 0xffe00000 0x100000>;
53 reg = <0xffe00000 0x1000>;
54 bus-frequency = <0>; // Filled out by uboot.
55
56 memory-controller@2000 {
57 compatible = "fsl,mpc8536-memory-controller";
58 reg = <0x2000 0x1000>;
59 interrupt-parent = <&mpic>;
60 interrupts = <18 0x2>;
61 };
62
63 L2: l2-cache-controller@20000 {
64 compatible = "fsl,mpc8536-l2-cache-controller";
65 reg = <0x20000 0x1000>;
66 interrupt-parent = <&mpic>;
67 interrupts = <16 0x2>;
68 };
69
70 i2c@3000 {
71 #address-cells = <1>;
72 #size-cells = <0>;
73 cell-index = <0>;
74 compatible = "fsl-i2c";
75 reg = <0x3000 0x100>;
76 interrupts = <43 0x2>;
77 interrupt-parent = <&mpic>;
78 dfsrr;
79 };
80
81 i2c@3100 {
82 #address-cells = <1>;
83 #size-cells = <0>;
84 cell-index = <1>;
85 compatible = "fsl-i2c";
86 reg = <0x3100 0x100>;
87 interrupts = <43 0x2>;
88 interrupt-parent = <&mpic>;
89 dfsrr;
90 rtc@68 {
91 compatible = "dallas,ds3232";
92 reg = <0x68>;
93 };
94 };
95
96 dma@21300 {
97 #address-cells = <1>;
98 #size-cells = <1>;
99 compatible = "fsl,mpc8536-dma", "fsl,eloplus-dma";
100 reg = <0x21300 4>;
101 ranges = <0 0x21100 0x200>;
102 cell-index = <0>;
103 dma-channel@0 {
104 compatible = "fsl,mpc8536-dma-channel",
105 "fsl,eloplus-dma-channel";
106 reg = <0x0 0x80>;
107 cell-index = <0>;
108 interrupt-parent = <&mpic>;
109 interrupts = <14 0x2>;
110 };
111 dma-channel@80 {
112 compatible = "fsl,mpc8536-dma-channel",
113 "fsl,eloplus-dma-channel";
114 reg = <0x80 0x80>;
115 cell-index = <1>;
116 interrupt-parent = <&mpic>;
117 interrupts = <15 0x2>;
118 };
119 dma-channel@100 {
120 compatible = "fsl,mpc8536-dma-channel",
121 "fsl,eloplus-dma-channel";
122 reg = <0x100 0x80>;
123 cell-index = <2>;
124 interrupt-parent = <&mpic>;
125 interrupts = <16 0x2>;
126 };
127 dma-channel@180 {
128 compatible = "fsl,mpc8536-dma-channel",
129 "fsl,eloplus-dma-channel";
130 reg = <0x180 0x80>;
131 cell-index = <3>;
132 interrupt-parent = <&mpic>;
133 interrupts = <17 0x2>;
134 };
135 };
136
137 mdio@24520 {
138 #address-cells = <1>;
139 #size-cells = <0>;
140 compatible = "fsl,gianfar-mdio";
141 reg = <0x24520 0x20>;
142
143 phy0: ethernet-phy@0 {
144 interrupt-parent = <&mpic>;
145 interrupts = <10 0x1>;
146 reg = <0>;
147 device_type = "ethernet-phy";
148 };
149 phy1: ethernet-phy@1 {
150 interrupt-parent = <&mpic>;
151 interrupts = <10 0x1>;
152 reg = <1>;
153 device_type = "ethernet-phy";
154 };
155 };
156
157 usb@22000 {
158 compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
159 reg = <0x22000 0x1000>;
160 #address-cells = <1>;
161 #size-cells = <0>;
162 interrupt-parent = <&mpic>;
163 interrupts = <28 0x2>;
164 phy_type = "ulpi";
165 };
166
167 usb@23000 {
168 compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
169 reg = <0x23000 0x1000>;
170 #address-cells = <1>;
171 #size-cells = <0>;
172 interrupt-parent = <&mpic>;
173 interrupts = <46 0x2>;
174 phy_type = "ulpi";
175 };
176
177 enet0: ethernet@24000 {
178 cell-index = <0>;
179 device_type = "network";
180 model = "TSEC";
181 compatible = "gianfar";
182 reg = <0x24000 0x1000>;
183 local-mac-address = [ 00 00 00 00 00 00 ];
184 interrupts = <29 2 30 2 34 2>;
185 interrupt-parent = <&mpic>;
186 phy-handle = <&phy1>;
187 phy-connection-type = "rgmii-id";
188 };
189
190 enet1: ethernet@26000 {
191 cell-index = <1>;
192 device_type = "network";
193 model = "TSEC";
194 compatible = "gianfar";
195 reg = <0x26000 0x1000>;
196 local-mac-address = [ 00 00 00 00 00 00 ];
197 interrupts = <31 2 32 2 33 2>;
198 interrupt-parent = <&mpic>;
199 phy-handle = <&phy0>;
200 phy-connection-type = "rgmii-id";
201 };
202
203 usb@2b000 {
204 compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr";
205 reg = <0x2b000 0x1000>;
206 #address-cells = <1>;
207 #size-cells = <0>;
208 interrupt-parent = <&mpic>;
209 interrupts = <60 0x2>;
210 dr_mode = "peripheral";
211 phy_type = "ulpi";
212 };
213
214 serial0: serial@4500 {
215 cell-index = <0>;
216 device_type = "serial";
217 compatible = "ns16550";
218 reg = <0x4500 0x100>;
219 clock-frequency = <0>;
220 interrupts = <42 0x2>;
221 interrupt-parent = <&mpic>;
222 };
223
224 serial1: serial@4600 {
225 cell-index = <1>;
226 device_type = "serial";
227 compatible = "ns16550";
228 reg = <0x4600 0x100>;
229 clock-frequency = <0>;
230 interrupts = <42 0x2>;
231 interrupt-parent = <&mpic>;
232 };
233
234 sata@18000 {
235 compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
236 reg = <0x18000 0x1000>;
237 cell-index = <1>;
238 interrupts = <74 0x2>;
239 interrupt-parent = <&mpic>;
240 };
241
242 sata@19000 {
243 compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
244 reg = <0x19000 0x1000>;
245 cell-index = <2>;
246 interrupts = <41 0x2>;
247 interrupt-parent = <&mpic>;
248 };
249
250 global-utilities@e0000 { //global utilities block
251 compatible = "fsl,mpc8548-guts";
252 reg = <0xe0000 0x1000>;
253 fsl,has-rstcr;
254 };
255
256 mpic: pic@40000 {
257 clock-frequency = <0>;
258 interrupt-controller;
259 #address-cells = <0>;
260 #interrupt-cells = <2>;
261 reg = <0x40000 0x40000>;
262 compatible = "chrp,open-pic";
263 device_type = "open-pic";
264 big-endian;
265 };
266
267 msi@41600 {
268 compatible = "fsl,mpc8536-msi", "fsl,mpic-msi";
269 reg = <0x41600 0x80>;
270 msi-available-ranges = <0 0x100>;
271 interrupts = <
272 0xe0 0
273 0xe1 0
274 0xe2 0
275 0xe3 0
276 0xe4 0
277 0xe5 0
278 0xe6 0
279 0xe7 0>;
280 interrupt-parent = <&mpic>;
281 };
282 };
283
284 pci0: pci@ffe08000 {
285 cell-index = <0>;
286 compatible = "fsl,mpc8540-pci";
287 device_type = "pci";
288 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
289 interrupt-map = <
290
291 /* IDSEL 0x11 J17 Slot 1 */
292 0x8800 0 0 1 &mpic 1 1
293 0x8800 0 0 2 &mpic 2 1
294 0x8800 0 0 3 &mpic 3 1
295 0x8800 0 0 4 &mpic 4 1>;
296
297 interrupt-parent = <&mpic>;
298 interrupts = <24 0x2>;
299 bus-range = <0 0xff>;
300 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x10000000
301 0x01000000 0 0x00000000 0xffc00000 0 0x00010000>;
302 clock-frequency = <66666666>;
303 #interrupt-cells = <1>;
304 #size-cells = <2>;
305 #address-cells = <3>;
306 reg = <0xffe08000 0x1000>;
307 };
308
309 pci1: pcie@ffe09000 {
310 cell-index = <1>;
311 compatible = "fsl,mpc8548-pcie";
312 device_type = "pci";
313 #interrupt-cells = <1>;
314 #size-cells = <2>;
315 #address-cells = <3>;
316 reg = <0xffe09000 0x1000>;
317 bus-range = <0 0xff>;
318 ranges = <0x02000000 0 0x98000000 0x98000000 0 0x08000000
319 0x01000000 0 0x00000000 0xffc20000 0 0x00010000>;
320 clock-frequency = <33333333>;
321 interrupt-parent = <&mpic>;
322 interrupts = <25 0x2>;
323 interrupt-map-mask = <0xf800 0 0 7>;
324 interrupt-map = <
325 /* IDSEL 0x0 */
326 0000 0 0 1 &mpic 4 1
327 0000 0 0 2 &mpic 5 1
328 0000 0 0 3 &mpic 6 1
329 0000 0 0 4 &mpic 7 1
330 >;
331 pcie@0 {
332 reg = <0 0 0 0 0>;
333 #size-cells = <2>;
334 #address-cells = <3>;
335 device_type = "pci";
336 ranges = <0x02000000 0 0x98000000
337 0x02000000 0 0x98000000
338 0 0x08000000
339
340 0x01000000 0 0x00000000
341 0x01000000 0 0x00000000
342 0 0x00010000>;
343 };
344 };
345
346 pci2: pcie@ffe0a000 {
347 cell-index = <2>;
348 compatible = "fsl,mpc8548-pcie";
349 device_type = "pci";
350 #interrupt-cells = <1>;
351 #size-cells = <2>;
352 #address-cells = <3>;
353 reg = <0xffe0a000 0x1000>;
354 bus-range = <0 0xff>;
355 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x08000000
356 0x01000000 0 0x00000000 0xffc10000 0 0x00010000>;
357 clock-frequency = <33333333>;
358 interrupt-parent = <&mpic>;
359 interrupts = <26 0x2>;
360 interrupt-map-mask = <0xf800 0 0 7>;
361 interrupt-map = <
362 /* IDSEL 0x0 */
363 0000 0 0 1 &mpic 0 1
364 0000 0 0 2 &mpic 1 1
365 0000 0 0 3 &mpic 2 1
366 0000 0 0 4 &mpic 3 1
367 >;
368 pcie@0 {
369 reg = <0 0 0 0 0>;
370 #size-cells = <2>;
371 #address-cells = <3>;
372 device_type = "pci";
373 ranges = <0x02000000 0 0x90000000
374 0x02000000 0 0x90000000
375 0 0x08000000
376
377 0x01000000 0 0x00000000
378 0x01000000 0 0x00000000
379 0 0x00010000>;
380 };
381 };
382
383 pci3: pcie@ffe0b000 {
384 cell-index = <3>;
385 compatible = "fsl,mpc8548-pcie";
386 device_type = "pci";
387 #interrupt-cells = <1>;
388 #size-cells = <2>;
389 #address-cells = <3>;
390 reg = <0xffe0b000 0x1000>;
391 bus-range = <0 0xff>;
392 ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000
393 0x01000000 0 0x00000000 0xffc30000 0 0x00010000>;
394 clock-frequency = <33333333>;
395 interrupt-parent = <&mpic>;
396 interrupts = <27 0x2>;
397 interrupt-map-mask = <0xf800 0 0 7>;
398 interrupt-map = <
399 /* IDSEL 0x0 */
400 0000 0 0 1 &mpic 8 1
401 0000 0 0 2 &mpic 9 1
402 0000 0 0 3 &mpic 10 1
403 0000 0 0 4 &mpic 11 1
404 >;
405
406 pcie@0 {
407 reg = <0 0 0 0 0>;
408 #size-cells = <2>;
409 #address-cells = <3>;
410 device_type = "pci";
411 ranges = <0x02000000 0 0xa0000000
412 0x02000000 0 0xa0000000
413 0 0x20000000
414
415 0x01000000 0 0x00000000
416 0x01000000 0 0x00000000
417 0 0x00100000>;
418 };
419 };
420};
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-11 04:13:24 -0500