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Diffstat (limited to 'arch/powerpc/boot/dts/mpc832x_rdb.dts')
-rw-r--r--arch/powerpc/boot/dts/mpc832x_rdb.dts154
1 files changed, 78 insertions, 76 deletions
diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts
index 551fc595075a..94f93d209de8 100644
--- a/arch/powerpc/boot/dts/mpc832x_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts
@@ -9,6 +9,8 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
13
12/ { 14/ {
13 model = "MPC8323ERDB"; 15 model = "MPC8323ERDB";
14 compatible = "MPC8323ERDB", "MPC832xRDB", "MPC83xxRDB"; 16 compatible = "MPC8323ERDB", "MPC832xRDB", "MPC83xxRDB";
@@ -29,11 +31,11 @@
29 31
30 PowerPC,8323@0 { 32 PowerPC,8323@0 {
31 device_type = "cpu"; 33 device_type = "cpu";
32 reg = <0>; 34 reg = <0x0>;
33 d-cache-line-size = <20>; // 32 bytes 35 d-cache-line-size = <0x20>; // 32 bytes
34 i-cache-line-size = <20>; // 32 bytes 36 i-cache-line-size = <0x20>; // 32 bytes
35 d-cache-size = <4000>; // L1, 16K 37 d-cache-size = <16384>; // L1, 16K
36 i-cache-size = <4000>; // L1, 16K 38 i-cache-size = <16384>; // L1, 16K
37 timebase-frequency = <0>; 39 timebase-frequency = <0>;
38 bus-frequency = <0>; 40 bus-frequency = <0>;
39 clock-frequency = <0>; 41 clock-frequency = <0>;
@@ -42,21 +44,21 @@
42 44
43 memory { 45 memory {
44 device_type = "memory"; 46 device_type = "memory";
45 reg = <00000000 04000000>; 47 reg = <0x00000000 0x04000000>;
46 }; 48 };
47 49
48 soc8323@e0000000 { 50 soc8323@e0000000 {
49 #address-cells = <1>; 51 #address-cells = <1>;
50 #size-cells = <1>; 52 #size-cells = <1>;
51 device_type = "soc"; 53 device_type = "soc";
52 ranges = <0 e0000000 00100000>; 54 ranges = <0x0 0xe0000000 0x00100000>;
53 reg = <e0000000 00000200>; 55 reg = <0xe0000000 0x00000200>;
54 bus-frequency = <0>; 56 bus-frequency = <0>;
55 57
56 wdt@200 { 58 wdt@200 {
57 device_type = "watchdog"; 59 device_type = "watchdog";
58 compatible = "mpc83xx_wdt"; 60 compatible = "mpc83xx_wdt";
59 reg = <200 100>; 61 reg = <0x200 0x100>;
60 }; 62 };
61 63
62 i2c@3000 { 64 i2c@3000 {
@@ -64,8 +66,8 @@
64 #size-cells = <0>; 66 #size-cells = <0>;
65 cell-index = <0>; 67 cell-index = <0>;
66 compatible = "fsl-i2c"; 68 compatible = "fsl-i2c";
67 reg = <3000 100>; 69 reg = <0x3000 0x100>;
68 interrupts = <e 8>; 70 interrupts = <14 0x8>;
69 interrupt-parent = <&pic>; 71 interrupt-parent = <&pic>;
70 dfsrr; 72 dfsrr;
71 }; 73 };
@@ -74,9 +76,9 @@
74 cell-index = <0>; 76 cell-index = <0>;
75 device_type = "serial"; 77 device_type = "serial";
76 compatible = "ns16550"; 78 compatible = "ns16550";
77 reg = <4500 100>; 79 reg = <0x4500 0x100>;
78 clock-frequency = <0>; 80 clock-frequency = <0>;
79 interrupts = <9 8>; 81 interrupts = <9 0x8>;
80 interrupt-parent = <&pic>; 82 interrupt-parent = <&pic>;
81 }; 83 };
82 84
@@ -84,9 +86,9 @@
84 cell-index = <1>; 86 cell-index = <1>;
85 device_type = "serial"; 87 device_type = "serial";
86 compatible = "ns16550"; 88 compatible = "ns16550";
87 reg = <4600 100>; 89 reg = <0x4600 0x100>;
88 clock-frequency = <0>; 90 clock-frequency = <0>;
89 interrupts = <a 8>; 91 interrupts = <10 0x8>;
90 interrupt-parent = <&pic>; 92 interrupt-parent = <&pic>;
91 }; 93 };
92 94
@@ -94,26 +96,26 @@
94 device_type = "crypto"; 96 device_type = "crypto";
95 model = "SEC2"; 97 model = "SEC2";
96 compatible = "talitos"; 98 compatible = "talitos";
97 reg = <30000 7000>; 99 reg = <0x30000 0x7000>;
98 interrupts = <b 8>; 100 interrupts = <11 0x8>;
99 interrupt-parent = <&pic>; 101 interrupt-parent = <&pic>;
100 /* Rev. 2.2 */ 102 /* Rev. 2.2 */
101 num-channels = <1>; 103 num-channels = <1>;
102 channel-fifo-len = <18>; 104 channel-fifo-len = <24>;
103 exec-units-mask = <0000004c>; 105 exec-units-mask = <0x0000004c>;
104 descriptor-types-mask = <0122003f>; 106 descriptor-types-mask = <0x0122003f>;
105 }; 107 };
106 108
107 pic:pic@700 { 109 pic:pic@700 {
108 interrupt-controller; 110 interrupt-controller;
109 #address-cells = <0>; 111 #address-cells = <0>;
110 #interrupt-cells = <2>; 112 #interrupt-cells = <2>;
111 reg = <700 100>; 113 reg = <0x700 0x100>;
112 device_type = "ipic"; 114 device_type = "ipic";
113 }; 115 };
114 116
115 par_io@1400 { 117 par_io@1400 {
116 reg = <1400 100>; 118 reg = <0x1400 0x100>;
117 device_type = "par_io"; 119 device_type = "par_io";
118 num-ports = <7>; 120 num-ports = <7>;
119 121
@@ -122,28 +124,28 @@
122 /* port pin dir open_drain assignment has_irq */ 124 /* port pin dir open_drain assignment has_irq */
123 3 4 3 0 2 0 /* MDIO */ 125 3 4 3 0 2 0 /* MDIO */
124 3 5 1 0 2 0 /* MDC */ 126 3 5 1 0 2 0 /* MDC */
125 3 15 2 0 1 0 /* RX_CLK (CLK16) */ 127 3 21 2 0 1 0 /* RX_CLK (CLK16) */
126 3 17 2 0 1 0 /* TX_CLK (CLK3) */ 128 3 23 2 0 1 0 /* TX_CLK (CLK3) */
127 0 12 1 0 1 0 /* TxD0 */ 129 0 18 1 0 1 0 /* TxD0 */
128 0 13 1 0 1 0 /* TxD1 */ 130 0 19 1 0 1 0 /* TxD1 */
129 0 14 1 0 1 0 /* TxD2 */ 131 0 20 1 0 1 0 /* TxD2 */
130 0 15 1 0 1 0 /* TxD3 */ 132 0 21 1 0 1 0 /* TxD3 */
131 0 16 2 0 1 0 /* RxD0 */ 133 0 22 2 0 1 0 /* RxD0 */
132 0 17 2 0 1 0 /* RxD1 */ 134 0 23 2 0 1 0 /* RxD1 */
133 0 18 2 0 1 0 /* RxD2 */ 135 0 24 2 0 1 0 /* RxD2 */
134 0 19 2 0 1 0 /* RxD3 */ 136 0 25 2 0 1 0 /* RxD3 */
135 0 1a 2 0 1 0 /* RX_ER */ 137 0 26 2 0 1 0 /* RX_ER */
136 0 1b 1 0 1 0 /* TX_ER */ 138 0 27 1 0 1 0 /* TX_ER */
137 0 1c 2 0 1 0 /* RX_DV */ 139 0 28 2 0 1 0 /* RX_DV */
138 0 1d 2 0 1 0 /* COL */ 140 0 29 2 0 1 0 /* COL */
139 0 1e 1 0 1 0 /* TX_EN */ 141 0 30 1 0 1 0 /* TX_EN */
140 0 1f 2 0 1 0>; /* CRS */ 142 0 31 2 0 1 0>; /* CRS */
141 }; 143 };
142 ucc3pio:ucc_pin@03 { 144 ucc3pio:ucc_pin@03 {
143 pio-map = < 145 pio-map = <
144 /* port pin dir open_drain assignment has_irq */ 146 /* port pin dir open_drain assignment has_irq */
145 0 d 2 0 1 0 /* RX_CLK (CLK9) */ 147 0 13 2 0 1 0 /* RX_CLK (CLK9) */
146 3 18 2 0 1 0 /* TX_CLK (CLK10) */ 148 3 24 2 0 1 0 /* TX_CLK (CLK10) */
147 1 0 1 0 1 0 /* TxD0 */ 149 1 0 1 0 1 0 /* TxD0 */
148 1 1 1 0 1 0 /* TxD1 */ 150 1 1 1 0 1 0 /* TxD1 */
149 1 2 1 0 1 0 /* TxD2 */ 151 1 2 1 0 1 0 /* TxD2 */
@@ -154,10 +156,10 @@
154 1 7 2 0 1 0 /* RxD3 */ 156 1 7 2 0 1 0 /* RxD3 */
155 1 8 2 0 1 0 /* RX_ER */ 157 1 8 2 0 1 0 /* RX_ER */
156 1 9 1 0 1 0 /* TX_ER */ 158 1 9 1 0 1 0 /* TX_ER */
157 1 a 2 0 1 0 /* RX_DV */ 159 1 10 2 0 1 0 /* RX_DV */
158 1 b 2 0 1 0 /* COL */ 160 1 11 2 0 1 0 /* COL */
159 1 c 1 0 1 0 /* TX_EN */ 161 1 12 1 0 1 0 /* TX_EN */
160 1 d 2 0 1 0>; /* CRS */ 162 1 13 2 0 1 0>; /* CRS */
161 }; 163 };
162 }; 164 };
163 }; 165 };
@@ -167,28 +169,28 @@
167 #size-cells = <1>; 169 #size-cells = <1>;
168 device_type = "qe"; 170 device_type = "qe";
169 compatible = "fsl,qe"; 171 compatible = "fsl,qe";
170 ranges = <0 e0100000 00100000>; 172 ranges = <0x0 0xe0100000 0x00100000>;
171 reg = <e0100000 480>; 173 reg = <0xe0100000 0x480>;
172 brg-frequency = <0>; 174 brg-frequency = <0>;
173 bus-frequency = <BCD3D80>; 175 bus-frequency = <198000000>;
174 176
175 muram@10000 { 177 muram@10000 {
176 #address-cells = <1>; 178 #address-cells = <1>;
177 #size-cells = <1>; 179 #size-cells = <1>;
178 compatible = "fsl,qe-muram", "fsl,cpm-muram"; 180 compatible = "fsl,qe-muram", "fsl,cpm-muram";
179 ranges = <0 00010000 00004000>; 181 ranges = <0x0 0x00010000 0x00004000>;
180 182
181 data-only@0 { 183 data-only@0 {
182 compatible = "fsl,qe-muram-data", 184 compatible = "fsl,qe-muram-data",
183 "fsl,cpm-muram-data"; 185 "fsl,cpm-muram-data";
184 reg = <0 4000>; 186 reg = <0x0 0x4000>;
185 }; 187 };
186 }; 188 };
187 189
188 spi@4c0 { 190 spi@4c0 {
189 cell-index = <0>; 191 cell-index = <0>;
190 compatible = "fsl,spi"; 192 compatible = "fsl,spi";
191 reg = <4c0 40>; 193 reg = <0x4c0 0x40>;
192 interrupts = <2>; 194 interrupts = <2>;
193 interrupt-parent = <&qeic>; 195 interrupt-parent = <&qeic>;
194 mode = "cpu-qe"; 196 mode = "cpu-qe";
@@ -197,7 +199,7 @@
197 spi@500 { 199 spi@500 {
198 cell-index = <1>; 200 cell-index = <1>;
199 compatible = "fsl,spi"; 201 compatible = "fsl,spi";
200 reg = <500 40>; 202 reg = <0x500 0x40>;
201 interrupts = <1>; 203 interrupts = <1>;
202 interrupt-parent = <&qeic>; 204 interrupt-parent = <&qeic>;
203 mode = "cpu"; 205 mode = "cpu";
@@ -209,8 +211,8 @@
209 model = "UCC"; 211 model = "UCC";
210 cell-index = <2>; 212 cell-index = <2>;
211 device-id = <2>; 213 device-id = <2>;
212 reg = <3000 200>; 214 reg = <0x3000 0x200>;
213 interrupts = <21>; 215 interrupts = <33>;
214 interrupt-parent = <&qeic>; 216 interrupt-parent = <&qeic>;
215 local-mac-address = [ 00 00 00 00 00 00 ]; 217 local-mac-address = [ 00 00 00 00 00 00 ];
216 rx-clock-name = "clk16"; 218 rx-clock-name = "clk16";
@@ -225,8 +227,8 @@
225 model = "UCC"; 227 model = "UCC";
226 cell-index = <3>; 228 cell-index = <3>;
227 device-id = <3>; 229 device-id = <3>;
228 reg = <2200 200>; 230 reg = <0x2200 0x200>;
229 interrupts = <22>; 231 interrupts = <34>;
230 interrupt-parent = <&qeic>; 232 interrupt-parent = <&qeic>;
231 local-mac-address = [ 00 00 00 00 00 00 ]; 233 local-mac-address = [ 00 00 00 00 00 00 ];
232 rx-clock-name = "clk9"; 234 rx-clock-name = "clk9";
@@ -238,19 +240,19 @@
238 mdio@3120 { 240 mdio@3120 {
239 #address-cells = <1>; 241 #address-cells = <1>;
240 #size-cells = <0>; 242 #size-cells = <0>;
241 reg = <3120 18>; 243 reg = <0x3120 0x18>;
242 compatible = "fsl,ucc-mdio"; 244 compatible = "fsl,ucc-mdio";
243 245
244 phy00:ethernet-phy@00 { 246 phy00:ethernet-phy@00 {
245 interrupt-parent = <&pic>; 247 interrupt-parent = <&pic>;
246 interrupts = <0>; 248 interrupts = <0>;
247 reg = <0>; 249 reg = <0x0>;
248 device_type = "ethernet-phy"; 250 device_type = "ethernet-phy";
249 }; 251 };
250 phy04:ethernet-phy@04 { 252 phy04:ethernet-phy@04 {
251 interrupt-parent = <&pic>; 253 interrupt-parent = <&pic>;
252 interrupts = <0>; 254 interrupts = <0>;
253 reg = <4>; 255 reg = <0x4>;
254 device_type = "ethernet-phy"; 256 device_type = "ethernet-phy";
255 }; 257 };
256 }; 258 };
@@ -260,43 +262,43 @@
260 compatible = "fsl,qe-ic"; 262 compatible = "fsl,qe-ic";
261 #address-cells = <0>; 263 #address-cells = <0>;
262 #interrupt-cells = <1>; 264 #interrupt-cells = <1>;
263 reg = <80 80>; 265 reg = <0x80 0x80>;
264 big-endian; 266 big-endian;
265 interrupts = <20 8 21 8>; //high:32 low:33 267 interrupts = <32 0x8 33 0x8>; //high:32 low:33
266 interrupt-parent = <&pic>; 268 interrupt-parent = <&pic>;
267 }; 269 };
268 }; 270 };
269 271
270 pci0: pci@e0008500 { 272 pci0: pci@e0008500 {
271 cell-index = <1>; 273 cell-index = <1>;
272 interrupt-map-mask = <f800 0 0 7>; 274 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
273 interrupt-map = < 275 interrupt-map = <
274 /* IDSEL 0x10 AD16 (USB) */ 276 /* IDSEL 0x10 AD16 (USB) */
275 8000 0 0 1 &pic 11 8 277 0x8000 0x0 0x0 0x1 &pic 17 0x8
276 278
277 /* IDSEL 0x11 AD17 (Mini1)*/ 279 /* IDSEL 0x11 AD17 (Mini1)*/
278 8800 0 0 1 &pic 12 8 280 0x8800 0x0 0x0 0x1 &pic 18 0x8
279 8800 0 0 2 &pic 13 8 281 0x8800 0x0 0x0 0x2 &pic 19 0x8
280 8800 0 0 3 &pic 14 8 282 0x8800 0x0 0x0 0x3 &pic 20 0x8
281 8800 0 0 4 &pic 30 8 283 0x8800 0x0 0x0 0x4 &pic 48 0x8
282 284
283 /* IDSEL 0x12 AD18 (PCI/Mini2) */ 285 /* IDSEL 0x12 AD18 (PCI/Mini2) */
284 9000 0 0 1 &pic 13 8 286 0x9000 0x0 0x0 0x1 &pic 19 0x8
285 9000 0 0 2 &pic 14 8 287 0x9000 0x0 0x0 0x2 &pic 20 0x8
286 9000 0 0 3 &pic 30 8 288 0x9000 0x0 0x0 0x3 &pic 48 0x8
287 9000 0 0 4 &pic 11 8>; 289 0x9000 0x0 0x0 0x4 &pic 17 0x8>;
288 290
289 interrupt-parent = <&pic>; 291 interrupt-parent = <&pic>;
290 interrupts = <42 8>; 292 interrupts = <66 0x8>;
291 bus-range = <0 0>; 293 bus-range = <0x0 0x0>;
292 ranges = <42000000 0 80000000 80000000 0 10000000 294 ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
293 02000000 0 90000000 90000000 0 10000000 295 0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
294 01000000 0 d0000000 d0000000 0 04000000>; 296 0x01000000 0x0 0xd0000000 0xd0000000 0x0 0x04000000>;
295 clock-frequency = <0>; 297 clock-frequency = <0>;
296 #interrupt-cells = <1>; 298 #interrupt-cells = <1>;
297 #size-cells = <2>; 299 #size-cells = <2>;
298 #address-cells = <3>; 300 #address-cells = <3>;
299 reg = <e0008500 100>; 301 reg = <0xe0008500 0x100>;
300 compatible = "fsl,mpc8349-pci"; 302 compatible = "fsl,mpc8349-pci";
301 device_type = "pci"; 303 device_type = "pci";
302 }; 304 };
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-21 10:54:09 -0500