aboutsummaryrefslogtreecommitdiffstats
path: root/arch/powerpc/boot/dts/mpc8313erdb.dts
diff options
context:
space:
mode:
Diffstat (limited to 'arch/powerpc/boot/dts/mpc8313erdb.dts')
-rw-r--r--arch/powerpc/boot/dts/mpc8313erdb.dts152
1 files changed, 77 insertions, 75 deletions
diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts
index 20a03f5b5bb7..2d6653fe72ff 100644
--- a/arch/powerpc/boot/dts/mpc8313erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
@@ -9,6 +9,8 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
13
12/ { 14/ {
13 model = "MPC8313ERDB"; 15 model = "MPC8313ERDB";
14 compatible = "MPC8313ERDB", "MPC831xRDB", "MPC83xxRDB"; 16 compatible = "MPC8313ERDB", "MPC831xRDB", "MPC83xxRDB";
@@ -29,11 +31,11 @@
29 31
30 PowerPC,8313@0 { 32 PowerPC,8313@0 {
31 device_type = "cpu"; 33 device_type = "cpu";
32 reg = <0>; 34 reg = <0x0>;
33 d-cache-line-size = <20>; // 32 bytes 35 d-cache-line-size = <32>;
34 i-cache-line-size = <20>; // 32 bytes 36 i-cache-line-size = <32>;
35 d-cache-size = <4000>; // L1, 16K 37 d-cache-size = <16384>;
36 i-cache-size = <4000>; // L1, 16K 38 i-cache-size = <16384>;
37 timebase-frequency = <0>; // from bootloader 39 timebase-frequency = <0>; // from bootloader
38 bus-frequency = <0>; // from bootloader 40 bus-frequency = <0>; // from bootloader
39 clock-frequency = <0>; // from bootloader 41 clock-frequency = <0>; // from bootloader
@@ -42,30 +44,30 @@
42 44
43 memory { 45 memory {
44 device_type = "memory"; 46 device_type = "memory";
45 reg = <00000000 08000000>; // 128MB at 0 47 reg = <0x00000000 0x08000000>; // 128MB at 0
46 }; 48 };
47 49
48 localbus@e0005000 { 50 localbus@e0005000 {
49 #address-cells = <2>; 51 #address-cells = <2>;
50 #size-cells = <1>; 52 #size-cells = <1>;
51 compatible = "fsl,mpc8313-elbc", "fsl,elbc", "simple-bus"; 53 compatible = "fsl,mpc8313-elbc", "fsl,elbc", "simple-bus";
52 reg = <e0005000 1000>; 54 reg = <0xe0005000 0x1000>;
53 interrupts = <d#77 8>; 55 interrupts = <77 0x8>;
54 interrupt-parent = <&ipic>; 56 interrupt-parent = <&ipic>;
55 57
56 // CS0 and CS1 are swapped when 58 // CS0 and CS1 are swapped when
57 // booting from nand, but the 59 // booting from nand, but the
58 // addresses are the same. 60 // addresses are the same.
59 ranges = <0 0 fe000000 00800000 61 ranges = <0x0 0x0 0xfe000000 0x00800000
60 1 0 e2800000 00008000 62 0x1 0x0 0xe2800000 0x00008000
61 2 0 f0000000 00020000 63 0x2 0x0 0xf0000000 0x00020000
62 3 0 fa000000 00008000>; 64 0x3 0x0 0xfa000000 0x00008000>;
63 65
64 flash@0,0 { 66 flash@0,0 {
65 #address-cells = <1>; 67 #address-cells = <1>;
66 #size-cells = <1>; 68 #size-cells = <1>;
67 compatible = "cfi-flash"; 69 compatible = "cfi-flash";
68 reg = <0 0 800000>; 70 reg = <0x0 0x0 0x800000>;
69 bank-width = <2>; 71 bank-width = <2>;
70 device-width = <1>; 72 device-width = <1>;
71 }; 73 };
@@ -75,19 +77,19 @@
75 #size-cells = <1>; 77 #size-cells = <1>;
76 compatible = "fsl,mpc8313-fcm-nand", 78 compatible = "fsl,mpc8313-fcm-nand",
77 "fsl,elbc-fcm-nand"; 79 "fsl,elbc-fcm-nand";
78 reg = <1 0 2000>; 80 reg = <0x1 0x0 0x2000>;
79 81
80 u-boot@0 { 82 u-boot@0 {
81 reg = <0 100000>; 83 reg = <0x0 0x100000>;
82 read-only; 84 read-only;
83 }; 85 };
84 86
85 kernel@100000 { 87 kernel@100000 {
86 reg = <100000 300000>; 88 reg = <0x100000 0x300000>;
87 }; 89 };
88 90
89 fs@400000 { 91 fs@400000 {
90 reg = <400000 1c00000>; 92 reg = <0x400000 0x1c00000>;
91 }; 93 };
92 }; 94 };
93 }; 95 };
@@ -97,14 +99,14 @@
97 #size-cells = <1>; 99 #size-cells = <1>;
98 device_type = "soc"; 100 device_type = "soc";
99 compatible = "simple-bus"; 101 compatible = "simple-bus";
100 ranges = <0 e0000000 00100000>; 102 ranges = <0x0 0xe0000000 0x00100000>;
101 reg = <e0000000 00000200>; 103 reg = <0xe0000000 0x00000200>;
102 bus-frequency = <0>; 104 bus-frequency = <0>;
103 105
104 wdt@200 { 106 wdt@200 {
105 device_type = "watchdog"; 107 device_type = "watchdog";
106 compatible = "mpc83xx_wdt"; 108 compatible = "mpc83xx_wdt";
107 reg = <200 100>; 109 reg = <0x200 0x100>;
108 }; 110 };
109 111
110 i2c@3000 { 112 i2c@3000 {
@@ -112,9 +114,9 @@
112 #size-cells = <0>; 114 #size-cells = <0>;
113 cell-index = <0>; 115 cell-index = <0>;
114 compatible = "fsl-i2c"; 116 compatible = "fsl-i2c";
115 reg = <3000 100>; 117 reg = <0x3000 0x100>;
116 interrupts = <e 8>; 118 interrupts = <14 0x8>;
117 interrupt-parent = < &ipic >; 119 interrupt-parent = <&ipic>;
118 dfsrr; 120 dfsrr;
119 }; 121 };
120 122
@@ -123,29 +125,29 @@
123 #size-cells = <0>; 125 #size-cells = <0>;
124 cell-index = <1>; 126 cell-index = <1>;
125 compatible = "fsl-i2c"; 127 compatible = "fsl-i2c";
126 reg = <3100 100>; 128 reg = <0x3100 0x100>;
127 interrupts = <f 8>; 129 interrupts = <15 0x8>;
128 interrupt-parent = < &ipic >; 130 interrupt-parent = <&ipic>;
129 dfsrr; 131 dfsrr;
130 }; 132 };
131 133
132 spi@7000 { 134 spi@7000 {
133 cell-index = <0>; 135 cell-index = <0>;
134 compatible = "fsl,spi"; 136 compatible = "fsl,spi";
135 reg = <7000 1000>; 137 reg = <0x7000 0x1000>;
136 interrupts = <10 8>; 138 interrupts = <16 0x8>;
137 interrupt-parent = < &ipic >; 139 interrupt-parent = <&ipic>;
138 mode = "cpu"; 140 mode = "cpu";
139 }; 141 };
140 142
141 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */ 143 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
142 usb@23000 { 144 usb@23000 {
143 compatible = "fsl-usb2-dr"; 145 compatible = "fsl-usb2-dr";
144 reg = <23000 1000>; 146 reg = <0x23000 0x1000>;
145 #address-cells = <1>; 147 #address-cells = <1>;
146 #size-cells = <0>; 148 #size-cells = <0>;
147 interrupt-parent = < &ipic >; 149 interrupt-parent = <&ipic>;
148 interrupts = <26 8>; 150 interrupts = <38 0x8>;
149 phy_type = "utmi_wide"; 151 phy_type = "utmi_wide";
150 }; 152 };
151 153
@@ -153,17 +155,17 @@
153 #address-cells = <1>; 155 #address-cells = <1>;
154 #size-cells = <0>; 156 #size-cells = <0>;
155 compatible = "fsl,gianfar-mdio"; 157 compatible = "fsl,gianfar-mdio";
156 reg = <24520 20>; 158 reg = <0x24520 0x20>;
157 phy1: ethernet-phy@1 { 159 phy1: ethernet-phy@1 {
158 interrupt-parent = < &ipic >; 160 interrupt-parent = <&ipic>;
159 interrupts = <13 8>; 161 interrupts = <19 0x8>;
160 reg = <1>; 162 reg = <0x1>;
161 device_type = "ethernet-phy"; 163 device_type = "ethernet-phy";
162 }; 164 };
163 phy4: ethernet-phy@4 { 165 phy4: ethernet-phy@4 {
164 interrupt-parent = < &ipic >; 166 interrupt-parent = <&ipic>;
165 interrupts = <14 8>; 167 interrupts = <20 0x8>;
166 reg = <4>; 168 reg = <0x4>;
167 device_type = "ethernet-phy"; 169 device_type = "ethernet-phy";
168 }; 170 };
169 }; 171 };
@@ -173,10 +175,10 @@
173 device_type = "network"; 175 device_type = "network";
174 model = "eTSEC"; 176 model = "eTSEC";
175 compatible = "gianfar"; 177 compatible = "gianfar";
176 reg = <24000 1000>; 178 reg = <0x24000 0x1000>;
177 local-mac-address = [ 00 00 00 00 00 00 ]; 179 local-mac-address = [ 00 00 00 00 00 00 ];
178 interrupts = <25 8 24 8 23 8>; 180 interrupts = <37 0x8 36 0x8 35 0x8>;
179 interrupt-parent = < &ipic >; 181 interrupt-parent = <&ipic>;
180 phy-handle = < &phy1 >; 182 phy-handle = < &phy1 >;
181 }; 183 };
182 184
@@ -185,10 +187,10 @@
185 device_type = "network"; 187 device_type = "network";
186 model = "eTSEC"; 188 model = "eTSEC";
187 compatible = "gianfar"; 189 compatible = "gianfar";
188 reg = <25000 1000>; 190 reg = <0x25000 0x1000>;
189 local-mac-address = [ 00 00 00 00 00 00 ]; 191 local-mac-address = [ 00 00 00 00 00 00 ];
190 interrupts = <22 8 21 8 20 8>; 192 interrupts = <34 0x8 33 0x8 32 0x8>;
191 interrupt-parent = < &ipic >; 193 interrupt-parent = <&ipic>;
192 phy-handle = < &phy4 >; 194 phy-handle = < &phy4 >;
193 }; 195 };
194 196
@@ -196,34 +198,34 @@
196 cell-index = <0>; 198 cell-index = <0>;
197 device_type = "serial"; 199 device_type = "serial";
198 compatible = "ns16550"; 200 compatible = "ns16550";
199 reg = <4500 100>; 201 reg = <0x4500 0x100>;
200 clock-frequency = <0>; 202 clock-frequency = <0>;
201 interrupts = <9 8>; 203 interrupts = <9 0x8>;
202 interrupt-parent = < &ipic >; 204 interrupt-parent = <&ipic>;
203 }; 205 };
204 206
205 serial1: serial@4600 { 207 serial1: serial@4600 {
206 cell-index = <1>; 208 cell-index = <1>;
207 device_type = "serial"; 209 device_type = "serial";
208 compatible = "ns16550"; 210 compatible = "ns16550";
209 reg = <4600 100>; 211 reg = <0x4600 0x100>;
210 clock-frequency = <0>; 212 clock-frequency = <0>;
211 interrupts = <a 8>; 213 interrupts = <10 0x8>;
212 interrupt-parent = < &ipic >; 214 interrupt-parent = <&ipic>;
213 }; 215 };
214 216
215 crypto@30000 { 217 crypto@30000 {
216 device_type = "crypto"; 218 device_type = "crypto";
217 model = "SEC2"; 219 model = "SEC2";
218 compatible = "talitos"; 220 compatible = "talitos";
219 reg = <30000 7000>; 221 reg = <0x30000 0x7000>;
220 interrupts = <b 8>; 222 interrupts = <11 0x8>;
221 interrupt-parent = < &ipic >; 223 interrupt-parent = <&ipic>;
222 /* Rev. 2.2 */ 224 /* Rev. 2.2 */
223 num-channels = <1>; 225 num-channels = <1>;
224 channel-fifo-len = <18>; 226 channel-fifo-len = <24>;
225 exec-units-mask = <0000004c>; 227 exec-units-mask = <0x0000004c>;
226 descriptor-types-mask = <0122003f>; 228 descriptor-types-mask = <0x0122003f>;
227 }; 229 };
228 230
229 /* IPIC 231 /* IPIC
@@ -236,38 +238,38 @@
236 interrupt-controller; 238 interrupt-controller;
237 #address-cells = <0>; 239 #address-cells = <0>;
238 #interrupt-cells = <2>; 240 #interrupt-cells = <2>;
239 reg = <700 100>; 241 reg = <0x700 0x100>;
240 device_type = "ipic"; 242 device_type = "ipic";
241 }; 243 };
242 }; 244 };
243 245
244 pci0: pci@e0008500 { 246 pci0: pci@e0008500 {
245 cell-index = <1>; 247 cell-index = <1>;
246 interrupt-map-mask = <f800 0 0 7>; 248 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
247 interrupt-map = < 249 interrupt-map = <
248 250
249 /* IDSEL 0x0E -mini PCI */ 251 /* IDSEL 0x0E -mini PCI */
250 7000 0 0 1 &ipic 12 8 252 0x7000 0x0 0x0 0x1 &ipic 18 0x8
251 7000 0 0 2 &ipic 12 8 253 0x7000 0x0 0x0 0x2 &ipic 18 0x8
252 7000 0 0 3 &ipic 12 8 254 0x7000 0x0 0x0 0x3 &ipic 18 0x8
253 7000 0 0 4 &ipic 12 8 255 0x7000 0x0 0x0 0x4 &ipic 18 0x8
254 256
255 /* IDSEL 0x0F - PCI slot */ 257 /* IDSEL 0x0F - PCI slot */
256 7800 0 0 1 &ipic 11 8 258 0x7800 0x0 0x0 0x1 &ipic 17 0x8
257 7800 0 0 2 &ipic 12 8 259 0x7800 0x0 0x0 0x2 &ipic 18 0x8
258 7800 0 0 3 &ipic 11 8 260 0x7800 0x0 0x0 0x3 &ipic 17 0x8
259 7800 0 0 4 &ipic 12 8>; 261 0x7800 0x0 0x0 0x4 &ipic 18 0x8>;
260 interrupt-parent = < &ipic >; 262 interrupt-parent = <&ipic>;
261 interrupts = <42 8>; 263 interrupts = <66 0x8>;
262 bus-range = <0 0>; 264 bus-range = <0x0 0x0>;
263 ranges = <02000000 0 90000000 90000000 0 10000000 265 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
264 42000000 0 80000000 80000000 0 10000000 266 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
265 01000000 0 00000000 e2000000 0 00100000>; 267 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
266 clock-frequency = <3f940aa>; 268 clock-frequency = <66666666>;
267 #interrupt-cells = <1>; 269 #interrupt-cells = <1>;
268 #size-cells = <2>; 270 #size-cells = <2>;
269 #address-cells = <3>; 271 #address-cells = <3>;
270 reg = <e0008500 100>; 272 reg = <0xe0008500 0x100>;
271 compatible = "fsl,mpc8349-pci"; 273 compatible = "fsl,mpc8349-pci";
272 device_type = "pci"; 274 device_type = "pci";
273 }; 275 };
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-23 08:47:47 -0500