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Diffstat (limited to 'arch/powerpc/boot/dts/mpc8313erdb.dts')
-rw-r--r--arch/powerpc/boot/dts/mpc8313erdb.dts67
1 files changed, 32 insertions, 35 deletions
diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts
index c5adbe40364e..9e7eba973262 100644
--- a/arch/powerpc/boot/dts/mpc8313erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
@@ -29,7 +29,6 @@
29 timebase-frequency = <0>; // from bootloader 29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; // from bootloader 30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; // from bootloader 31 clock-frequency = <0>; // from bootloader
32 32-bit;
33 }; 32 };
34 }; 33 };
35 34
@@ -41,7 +40,6 @@
41 soc8313@e0000000 { 40 soc8313@e0000000 {
42 #address-cells = <1>; 41 #address-cells = <1>;
43 #size-cells = <1>; 42 #size-cells = <1>;
44 #interrupt-cells = <2>;
45 device_type = "soc"; 43 device_type = "soc";
46 ranges = <0 e0000000 00100000>; 44 ranges = <0 e0000000 00100000>;
47 reg = <e0000000 00000200>; 45 reg = <e0000000 00000200>;
@@ -73,11 +71,11 @@
73 71
74 spi@7000 { 72 spi@7000 {
75 device_type = "spi"; 73 device_type = "spi";
76 compatible = "mpc83xx_spi"; 74 compatible = "fsl_spi";
77 reg = <7000 1000>; 75 reg = <7000 1000>;
78 interrupts = <10 8>; 76 interrupts = <10 8>;
79 interrupt-parent = < &ipic >; 77 interrupt-parent = < &ipic >;
80 mode = <0>; 78 mode = "cpu";
81 }; 79 };
82 80
83 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */ 81 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
@@ -152,36 +150,6 @@
152 interrupt-parent = < &ipic >; 150 interrupt-parent = < &ipic >;
153 }; 151 };
154 152
155 pci@8500 {
156 interrupt-map-mask = <f800 0 0 7>;
157 interrupt-map = <
158
159 /* IDSEL 0x0E -mini PCI */
160 7000 0 0 1 &ipic 12 8
161 7000 0 0 2 &ipic 12 8
162 7000 0 0 3 &ipic 12 8
163 7000 0 0 4 &ipic 12 8
164
165 /* IDSEL 0x0F - PCI slot */
166 7800 0 0 1 &ipic 11 8
167 7800 0 0 2 &ipic 12 8
168 7800 0 0 3 &ipic 11 8
169 7800 0 0 4 &ipic 12 8>;
170 interrupt-parent = < &ipic >;
171 interrupts = <42 8>;
172 bus-range = <0 0>;
173 ranges = <02000000 0 90000000 90000000 0 10000000
174 42000000 0 80000000 80000000 0 10000000
175 01000000 0 00000000 e2000000 0 00100000>;
176 clock-frequency = <3f940aa>;
177 #interrupt-cells = <1>;
178 #size-cells = <2>;
179 #address-cells = <3>;
180 reg = <8500 100>;
181 compatible = "fsl,mpc8349-pci";
182 device_type = "pci";
183 };
184
185 crypto@30000 { 153 crypto@30000 {
186 device_type = "crypto"; 154 device_type = "crypto";
187 model = "SEC2"; 155 model = "SEC2";
@@ -207,8 +175,37 @@
207 #address-cells = <0>; 175 #address-cells = <0>;
208 #interrupt-cells = <2>; 176 #interrupt-cells = <2>;
209 reg = <700 100>; 177 reg = <700 100>;
210 built-in;
211 device_type = "ipic"; 178 device_type = "ipic";
212 }; 179 };
213 }; 180 };
181
182 pci@e0008500 {
183 interrupt-map-mask = <f800 0 0 7>;
184 interrupt-map = <
185
186 /* IDSEL 0x0E -mini PCI */
187 7000 0 0 1 &ipic 12 8
188 7000 0 0 2 &ipic 12 8
189 7000 0 0 3 &ipic 12 8
190 7000 0 0 4 &ipic 12 8
191
192 /* IDSEL 0x0F - PCI slot */
193 7800 0 0 1 &ipic 11 8
194 7800 0 0 2 &ipic 12 8
195 7800 0 0 3 &ipic 11 8
196 7800 0 0 4 &ipic 12 8>;
197 interrupt-parent = < &ipic >;
198 interrupts = <42 8>;
199 bus-range = <0 0>;
200 ranges = <02000000 0 90000000 90000000 0 10000000
201 42000000 0 80000000 80000000 0 10000000
202 01000000 0 00000000 e2000000 0 00100000>;
203 clock-frequency = <3f940aa>;
204 #interrupt-cells = <1>;
205 #size-cells = <2>;
206 #address-cells = <3>;
207 reg = <e0008500 100>;
208 compatible = "fsl,mpc8349-pci";
209 device_type = "pci";
210 };
214}; 211};