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-rw-r--r--arch/powerpc/boot/dts/mpc8272ads.dts132
1 files changed, 67 insertions, 65 deletions
diff --git a/arch/powerpc/boot/dts/mpc8272ads.dts b/arch/powerpc/boot/dts/mpc8272ads.dts
index 7285ca1325fd..46e2da30c3dd 100644
--- a/arch/powerpc/boot/dts/mpc8272ads.dts
+++ b/arch/powerpc/boot/dts/mpc8272ads.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8272 ADS Device Tree Source 2 * MPC8272 ADS Device Tree Source
3 * 3 *
4 * Copyright 2005 Freescale Semiconductor Inc. 4 * Copyright 2005,2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,6 +9,8 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
13
12/ { 14/ {
13 model = "MPC8272ADS"; 15 model = "MPC8272ADS";
14 compatible = "fsl,mpc8272ads"; 16 compatible = "fsl,mpc8272ads";
@@ -21,11 +23,11 @@
21 23
22 PowerPC,8272@0 { 24 PowerPC,8272@0 {
23 device_type = "cpu"; 25 device_type = "cpu";
24 reg = <0>; 26 reg = <0x0>;
25 d-cache-line-size = <d#32>; 27 d-cache-line-size = <32>;
26 i-cache-line-size = <d#32>; 28 i-cache-line-size = <32>;
27 d-cache-size = <d#16384>; 29 d-cache-size = <16384>;
28 i-cache-size = <d#16384>; 30 i-cache-size = <16384>;
29 timebase-frequency = <0>; 31 timebase-frequency = <0>;
30 bus-frequency = <0>; 32 bus-frequency = <0>;
31 clock-frequency = <0>; 33 clock-frequency = <0>;
@@ -34,7 +36,7 @@
34 36
35 memory { 37 memory {
36 device_type = "memory"; 38 device_type = "memory";
37 reg = <0 0>; 39 reg = <0x0 0x0>;
38 }; 40 };
39 41
40 localbus@f0010100 { 42 localbus@f0010100 {
@@ -42,21 +44,21 @@
42 "fsl,pq2-localbus"; 44 "fsl,pq2-localbus";
43 #address-cells = <2>; 45 #address-cells = <2>;
44 #size-cells = <1>; 46 #size-cells = <1>;
45 reg = <f0010100 40>; 47 reg = <0xf0010100 0x40>;
46 48
47 ranges = <0 0 fe000000 02000000 49 ranges = <0x0 0x0 0xfe000000 0x2000000
48 1 0 f4500000 00008000 50 0x1 0x0 0xf4500000 0x8000
49 3 0 f8200000 00008000>; 51 0x3 0x0 0xf8200000 0x8000>;
50 52
51 flash@0,0 { 53 flash@0,0 {
52 compatible = "jedec-flash"; 54 compatible = "jedec-flash";
53 reg = <0 0 2000000>; 55 reg = <0x0 0x0 0x2000000>;
54 bank-width = <4>; 56 bank-width = <4>;
55 device-width = <1>; 57 device-width = <1>;
56 }; 58 };
57 59
58 board-control@1,0 { 60 board-control@1,0 {
59 reg = <1 0 20>; 61 reg = <0x1 0x0 0x20>;
60 compatible = "fsl,mpc8272ads-bcsr"; 62 compatible = "fsl,mpc8272ads-bcsr";
61 }; 63 };
62 64
@@ -65,46 +67,46 @@
65 "fsl,pq2ads-pci-pic"; 67 "fsl,pq2ads-pci-pic";
66 #interrupt-cells = <1>; 68 #interrupt-cells = <1>;
67 interrupt-controller; 69 interrupt-controller;
68 reg = <3 0 8>; 70 reg = <0x3 0x0 0x8>;
69 interrupt-parent = <&PIC>; 71 interrupt-parent = <&PIC>;
70 interrupts = <14 8>; 72 interrupts = <20 8>;
71 }; 73 };
72 }; 74 };
73 75
74 76
75 pci@f0010800 { 77 pci@f0010800 {
76 device_type = "pci"; 78 device_type = "pci";
77 reg = <f0010800 10c f00101ac 8 f00101c4 8>; 79 reg = <0xf0010800 0x10c 0xf00101ac 0x8 0xf00101c4 0x8>;
78 compatible = "fsl,mpc8272-pci", "fsl,pq2-pci"; 80 compatible = "fsl,mpc8272-pci", "fsl,pq2-pci";
79 #interrupt-cells = <1>; 81 #interrupt-cells = <1>;
80 #size-cells = <2>; 82 #size-cells = <2>;
81 #address-cells = <3>; 83 #address-cells = <3>;
82 clock-frequency = <d#66666666>; 84 clock-frequency = <66666666>;
83 interrupt-map-mask = <f800 0 0 7>; 85 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
84 interrupt-map = < 86 interrupt-map = <
85 /* IDSEL 0x16 */ 87 /* IDSEL 0x16 */
86 b000 0 0 1 &PCI_PIC 0 88 0xb000 0x0 0x0 0x1 &PCI_PIC 0
87 b000 0 0 2 &PCI_PIC 1 89 0xb000 0x0 0x0 0x2 &PCI_PIC 1
88 b000 0 0 3 &PCI_PIC 2 90 0xb000 0x0 0x0 0x3 &PCI_PIC 2
89 b000 0 0 4 &PCI_PIC 3 91 0xb000 0x0 0x0 0x4 &PCI_PIC 3
90 92
91 /* IDSEL 0x17 */ 93 /* IDSEL 0x17 */
92 b800 0 0 1 &PCI_PIC 4 94 0xb800 0x0 0x0 0x1 &PCI_PIC 4
93 b800 0 0 2 &PCI_PIC 5 95 0xb800 0x0 0x0 0x2 &PCI_PIC 5
94 b800 0 0 3 &PCI_PIC 6 96 0xb800 0x0 0x0 0x3 &PCI_PIC 6
95 b800 0 0 4 &PCI_PIC 7 97 0xb800 0x0 0x0 0x4 &PCI_PIC 7
96 98
97 /* IDSEL 0x18 */ 99 /* IDSEL 0x18 */
98 c000 0 0 1 &PCI_PIC 8 100 0xc000 0x0 0x0 0x1 &PCI_PIC 8
99 c000 0 0 2 &PCI_PIC 9 101 0xc000 0x0 0x0 0x2 &PCI_PIC 9
100 c000 0 0 3 &PCI_PIC a 102 0xc000 0x0 0x0 0x3 &PCI_PIC 10
101 c000 0 0 4 &PCI_PIC b>; 103 0xc000 0x0 0x0 0x4 &PCI_PIC 11>;
102 104
103 interrupt-parent = <&PIC>; 105 interrupt-parent = <&PIC>;
104 interrupts = <12 8>; 106 interrupts = <18 8>;
105 ranges = <42000000 0 80000000 80000000 0 20000000 107 ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000
106 02000000 0 a0000000 a0000000 0 20000000 108 0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
107 01000000 0 00000000 f6000000 0 02000000>; 109 0x1000000 0x0 0x0 0xf6000000 0x0 0x2000000>;
108 }; 110 };
109 111
110 soc@f0000000 { 112 soc@f0000000 {
@@ -112,26 +114,26 @@
112 #size-cells = <1>; 114 #size-cells = <1>;
113 device_type = "soc"; 115 device_type = "soc";
114 compatible = "fsl,mpc8272", "fsl,pq2-soc"; 116 compatible = "fsl,mpc8272", "fsl,pq2-soc";
115 ranges = <00000000 f0000000 00053000>; 117 ranges = <0x0 0xf0000000 0x53000>;
116 118
117 // Temporary -- will go away once kernel uses ranges for get_immrbase(). 119 // Temporary -- will go away once kernel uses ranges for get_immrbase().
118 reg = <f0000000 00053000>; 120 reg = <0xf0000000 0x53000>;
119 121
120 cpm@119c0 { 122 cpm@119c0 {
121 #address-cells = <1>; 123 #address-cells = <1>;
122 #size-cells = <1>; 124 #size-cells = <1>;
123 compatible = "fsl,mpc8272-cpm", "fsl,cpm2"; 125 compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
124 reg = <119c0 30>; 126 reg = <0x119c0 0x30>;
125 ranges; 127 ranges;
126 128
127 muram@0 { 129 muram@0 {
128 #address-cells = <1>; 130 #address-cells = <1>;
129 #size-cells = <1>; 131 #size-cells = <1>;
130 ranges = <0 0 10000>; 132 ranges = <0x0 0x0 0x10000>;
131 133
132 data@0 { 134 data@0 {
133 compatible = "fsl,cpm-muram-data"; 135 compatible = "fsl,cpm-muram-data";
134 reg = <0 2000 9800 800>; 136 reg = <0x0 0x2000 0x9800 0x800>;
135 }; 137 };
136 }; 138 };
137 139
@@ -139,29 +141,29 @@
139 compatible = "fsl,mpc8272-brg", 141 compatible = "fsl,mpc8272-brg",
140 "fsl,cpm2-brg", 142 "fsl,cpm2-brg",
141 "fsl,cpm-brg"; 143 "fsl,cpm-brg";
142 reg = <119f0 10 115f0 10>; 144 reg = <0x119f0 0x10 0x115f0 0x10>;
143 }; 145 };
144 146
145 serial@11a00 { 147 serial@11a00 {
146 device_type = "serial"; 148 device_type = "serial";
147 compatible = "fsl,mpc8272-scc-uart", 149 compatible = "fsl,mpc8272-scc-uart",
148 "fsl,cpm2-scc-uart"; 150 "fsl,cpm2-scc-uart";
149 reg = <11a00 20 8000 100>; 151 reg = <0x11a00 0x20 0x8000 0x100>;
150 interrupts = <28 8>; 152 interrupts = <40 8>;
151 interrupt-parent = <&PIC>; 153 interrupt-parent = <&PIC>;
152 fsl,cpm-brg = <1>; 154 fsl,cpm-brg = <1>;
153 fsl,cpm-command = <00800000>; 155 fsl,cpm-command = <0x800000>;
154 }; 156 };
155 157
156 serial@11a60 { 158 serial@11a60 {
157 device_type = "serial"; 159 device_type = "serial";
158 compatible = "fsl,mpc8272-scc-uart", 160 compatible = "fsl,mpc8272-scc-uart",
159 "fsl,cpm2-scc-uart"; 161 "fsl,cpm2-scc-uart";
160 reg = <11a60 20 8300 100>; 162 reg = <0x11a60 0x20 0x8300 0x100>;
161 interrupts = <2b 8>; 163 interrupts = <43 8>;
162 interrupt-parent = <&PIC>; 164 interrupt-parent = <&PIC>;
163 fsl,cpm-brg = <4>; 165 fsl,cpm-brg = <4>;
164 fsl,cpm-command = <0ce00000>; 166 fsl,cpm-command = <0xce00000>;
165 }; 167 };
166 168
167 mdio@10d40 { 169 mdio@10d40 {
@@ -169,23 +171,23 @@
169 compatible = "fsl,mpc8272ads-mdio-bitbang", 171 compatible = "fsl,mpc8272ads-mdio-bitbang",
170 "fsl,mpc8272-mdio-bitbang", 172 "fsl,mpc8272-mdio-bitbang",
171 "fsl,cpm2-mdio-bitbang"; 173 "fsl,cpm2-mdio-bitbang";
172 reg = <10d40 14>; 174 reg = <0x10d40 0x14>;
173 #address-cells = <1>; 175 #address-cells = <1>;
174 #size-cells = <0>; 176 #size-cells = <0>;
175 fsl,mdio-pin = <12>; 177 fsl,mdio-pin = <18>;
176 fsl,mdc-pin = <13>; 178 fsl,mdc-pin = <19>;
177 179
178 PHY0: ethernet-phy@0 { 180 PHY0: ethernet-phy@0 {
179 interrupt-parent = <&PIC>; 181 interrupt-parent = <&PIC>;
180 interrupts = <17 8>; 182 interrupts = <23 8>;
181 reg = <0>; 183 reg = <0x0>;
182 device_type = "ethernet-phy"; 184 device_type = "ethernet-phy";
183 }; 185 };
184 186
185 PHY1: ethernet-phy@1 { 187 PHY1: ethernet-phy@1 {
186 interrupt-parent = <&PIC>; 188 interrupt-parent = <&PIC>;
187 interrupts = <17 8>; 189 interrupts = <23 8>;
188 reg = <3>; 190 reg = <0x3>;
189 device_type = "ethernet-phy"; 191 device_type = "ethernet-phy";
190 }; 192 };
191 }; 193 };
@@ -194,33 +196,33 @@
194 device_type = "network"; 196 device_type = "network";
195 compatible = "fsl,mpc8272-fcc-enet", 197 compatible = "fsl,mpc8272-fcc-enet",
196 "fsl,cpm2-fcc-enet"; 198 "fsl,cpm2-fcc-enet";
197 reg = <11300 20 8400 100 11390 1>; 199 reg = <0x11300 0x20 0x8400 0x100 0x11390 0x1>;
198 local-mac-address = [ 00 00 00 00 00 00 ]; 200 local-mac-address = [ 00 00 00 00 00 00 ];
199 interrupts = <20 8>; 201 interrupts = <32 8>;
200 interrupt-parent = <&PIC>; 202 interrupt-parent = <&PIC>;
201 phy-handle = <&PHY0>; 203 phy-handle = <&PHY0>;
202 linux,network-index = <0>; 204 linux,network-index = <0>;
203 fsl,cpm-command = <12000300>; 205 fsl,cpm-command = <0x12000300>;
204 }; 206 };
205 207
206 ethernet@11320 { 208 ethernet@11320 {
207 device_type = "network"; 209 device_type = "network";
208 compatible = "fsl,mpc8272-fcc-enet", 210 compatible = "fsl,mpc8272-fcc-enet",
209 "fsl,cpm2-fcc-enet"; 211 "fsl,cpm2-fcc-enet";
210 reg = <11320 20 8500 100 113b0 1>; 212 reg = <0x11320 0x20 0x8500 0x100 0x113b0 0x1>;
211 local-mac-address = [ 00 00 00 00 00 00 ]; 213 local-mac-address = [ 00 00 00 00 00 00 ];
212 interrupts = <21 8>; 214 interrupts = <33 8>;
213 interrupt-parent = <&PIC>; 215 interrupt-parent = <&PIC>;
214 phy-handle = <&PHY1>; 216 phy-handle = <&PHY1>;
215 linux,network-index = <1>; 217 linux,network-index = <1>;
216 fsl,cpm-command = <16200300>; 218 fsl,cpm-command = <0x16200300>;
217 }; 219 };
218 }; 220 };
219 221
220 PIC: interrupt-controller@10c00 { 222 PIC: interrupt-controller@10c00 {
221 #interrupt-cells = <2>; 223 #interrupt-cells = <2>;
222 interrupt-controller; 224 interrupt-controller;
223 reg = <10c00 80>; 225 reg = <0x10c00 0x80>;
224 compatible = "fsl,mpc8272-pic", "fsl,cpm2-pic"; 226 compatible = "fsl,mpc8272-pic", "fsl,cpm2-pic";
225 }; 227 };
226 228
@@ -232,14 +234,14 @@
232 "fsl,talitos-sec2", 234 "fsl,talitos-sec2",
233 "fsl,talitos", 235 "fsl,talitos",
234 "talitos"; 236 "talitos";
235 reg = <30000 10000>; 237 reg = <0x30000 0x10000>;
236 interrupts = <b 8>; 238 interrupts = <11 8>;
237 interrupt-parent = <&PIC>; 239 interrupt-parent = <&PIC>;
238 num-channels = <4>; 240 num-channels = <4>;
239 channel-fifo-len = <18>; 241 channel-fifo-len = <24>;
240 exec-units-mask = <0000007e>; 242 exec-units-mask = <0x7e>;
241/* desc mask is for rev1.x, we need runtime fixup for >=2.x */ 243/* desc mask is for rev1.x, we need runtime fixup for >=2.x */
242 descriptor-types-mask = <01010ebf>; 244 descriptor-types-mask = <0x1010ebf>;
243 }; 245 };
244 }; 246 };
245 247
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-06 03:35:11 -0500