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-rw-r--r--arch/powerpc/boot/dts/motionpro.dts68
1 files changed, 30 insertions, 38 deletions
diff --git a/arch/powerpc/boot/dts/motionpro.dts b/arch/powerpc/boot/dts/motionpro.dts
index d8c316ae0a47..76951ab038ee 100644
--- a/arch/powerpc/boot/dts/motionpro.dts
+++ b/arch/powerpc/boot/dts/motionpro.dts
@@ -10,12 +10,6 @@
10 * option) any later version. 10 * option) any later version.
11 */ 11 */
12 12
13/*
14 * WARNING: Do not depend on this tree layout remaining static just yet.
15 * The MPC5200 device tree conventions are still in flux
16 * Keep an eye on the linuxppc-dev mailing list for more details
17 */
18
19/ { 13/ {
20 model = "promess,motionpro"; 14 model = "promess,motionpro";
21 compatible = "promess,motionpro"; 15 compatible = "promess,motionpro";
@@ -45,29 +39,28 @@
45 }; 39 };
46 40
47 soc5200@f0000000 { 41 soc5200@f0000000 {
48 model = "fsl,mpc5200b"; 42 #address-cells = <1>;
49 compatible = "fsl,mpc5200b"; 43 #size-cells = <1>;
50 revision = ""; // from bootloader 44 compatible = "fsl,mpc5200b-immr";
51 device_type = "soc";
52 ranges = <0 f0000000 0000c000>; 45 ranges = <0 f0000000 0000c000>;
53 reg = <f0000000 00000100>; 46 reg = <f0000000 00000100>;
54 bus-frequency = <0>; // from bootloader 47 bus-frequency = <0>; // from bootloader
55 system-frequency = <0>; // from bootloader 48 system-frequency = <0>; // from bootloader
56 49
57 cdm@200 { 50 cdm@200 {
58 compatible = "mpc5200b-cdm","mpc5200-cdm"; 51 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
59 reg = <200 38>; 52 reg = <200 38>;
60 }; 53 };
61 54
62 mpc5200_pic: pic@500 { 55 mpc5200_pic: interrupt-controller@500 {
63 // 5200 interrupts are encoded into two levels; 56 // 5200 interrupts are encoded into two levels;
64 interrupt-controller; 57 interrupt-controller;
65 #interrupt-cells = <3>; 58 #interrupt-cells = <3>;
66 compatible = "mpc5200b-pic","mpc5200-pic"; 59 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
67 reg = <500 80>; 60 reg = <500 80>;
68 }; 61 };
69 62
70 gpt@600 { // General Purpose Timer 63 timer@600 { // General Purpose Timer
71 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 64 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
72 reg = <600 10>; 65 reg = <600 10>;
73 interrupts = <1 9 0>; 66 interrupts = <1 9 0>;
@@ -75,35 +68,35 @@
75 fsl,has-wdt; 68 fsl,has-wdt;
76 }; 69 };
77 70
78 gpt@610 { // General Purpose Timer 71 timer@610 { // General Purpose Timer
79 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 72 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
80 reg = <610 10>; 73 reg = <610 10>;
81 interrupts = <1 a 0>; 74 interrupts = <1 a 0>;
82 interrupt-parent = <&mpc5200_pic>; 75 interrupt-parent = <&mpc5200_pic>;
83 }; 76 };
84 77
85 gpt@620 { // General Purpose Timer 78 timer@620 { // General Purpose Timer
86 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 79 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
87 reg = <620 10>; 80 reg = <620 10>;
88 interrupts = <1 b 0>; 81 interrupts = <1 b 0>;
89 interrupt-parent = <&mpc5200_pic>; 82 interrupt-parent = <&mpc5200_pic>;
90 }; 83 };
91 84
92 gpt@630 { // General Purpose Timer 85 timer@630 { // General Purpose Timer
93 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 86 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
94 reg = <630 10>; 87 reg = <630 10>;
95 interrupts = <1 c 0>; 88 interrupts = <1 c 0>;
96 interrupt-parent = <&mpc5200_pic>; 89 interrupt-parent = <&mpc5200_pic>;
97 }; 90 };
98 91
99 gpt@640 { // General Purpose Timer 92 timer@640 { // General Purpose Timer
100 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 93 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
101 reg = <640 10>; 94 reg = <640 10>;
102 interrupts = <1 d 0>; 95 interrupts = <1 d 0>;
103 interrupt-parent = <&mpc5200_pic>; 96 interrupt-parent = <&mpc5200_pic>;
104 }; 97 };
105 98
106 gpt@650 { // General Purpose Timer 99 timer@650 { // General Purpose Timer
107 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 100 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
108 reg = <650 10>; 101 reg = <650 10>;
109 interrupts = <1 e 0>; 102 interrupts = <1 e 0>;
@@ -128,28 +121,28 @@
128 }; 121 };
129 122
130 rtc@800 { // Real time clock 123 rtc@800 { // Real time clock
131 compatible = "mpc5200b-rtc","mpc5200-rtc"; 124 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
132 reg = <800 100>; 125 reg = <800 100>;
133 interrupts = <1 5 0 1 6 0>; 126 interrupts = <1 5 0 1 6 0>;
134 interrupt-parent = <&mpc5200_pic>; 127 interrupt-parent = <&mpc5200_pic>;
135 }; 128 };
136 129
137 mscan@980 { 130 mscan@980 {
138 compatible = "mpc5200b-mscan","mpc5200-mscan"; 131 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
139 interrupts = <2 12 0>; 132 interrupts = <2 12 0>;
140 interrupt-parent = <&mpc5200_pic>; 133 interrupt-parent = <&mpc5200_pic>;
141 reg = <980 80>; 134 reg = <980 80>;
142 }; 135 };
143 136
144 gpio@b00 { 137 gpio@b00 {
145 compatible = "mpc5200b-gpio","mpc5200-gpio"; 138 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
146 reg = <b00 40>; 139 reg = <b00 40>;
147 interrupts = <1 7 0>; 140 interrupts = <1 7 0>;
148 interrupt-parent = <&mpc5200_pic>; 141 interrupt-parent = <&mpc5200_pic>;
149 }; 142 };
150 143
151 gpio-wkup@c00 { 144 gpio@c00 {
152 compatible = "mpc5200b-gpio-wkup","mpc5200-gpio-wkup"; 145 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
153 reg = <c00 40>; 146 reg = <c00 40>;
154 interrupts = <1 8 0 0 3 0>; 147 interrupts = <1 8 0 0 3 0>;
155 interrupt-parent = <&mpc5200_pic>; 148 interrupt-parent = <&mpc5200_pic>;
@@ -157,21 +150,21 @@
157 150
158 151
159 spi@f00 { 152 spi@f00 {
160 compatible = "mpc5200b-spi","mpc5200-spi"; 153 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
161 reg = <f00 20>; 154 reg = <f00 20>;
162 interrupts = <2 d 0 2 e 0>; 155 interrupts = <2 d 0 2 e 0>;
163 interrupt-parent = <&mpc5200_pic>; 156 interrupt-parent = <&mpc5200_pic>;
164 }; 157 };
165 158
166 usb@1000 { 159 usb@1000 {
167 compatible = "mpc5200b-ohci","mpc5200-ohci","ohci-be"; 160 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
168 reg = <1000 ff>; 161 reg = <1000 ff>;
169 interrupts = <2 6 0>; 162 interrupts = <2 6 0>;
170 interrupt-parent = <&mpc5200_pic>; 163 interrupt-parent = <&mpc5200_pic>;
171 }; 164 };
172 165
173 dma-controller@1200 { 166 dma-controller@1200 {
174 compatible = "mpc5200b-bestcomm","mpc5200-bestcomm"; 167 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
175 reg = <1200 80>; 168 reg = <1200 80>;
176 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 169 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
177 3 4 0 3 5 0 3 6 0 3 7 0 170 3 4 0 3 5 0 3 6 0 3 7 0
@@ -181,13 +174,13 @@
181 }; 174 };
182 175
183 xlb@1f00 { 176 xlb@1f00 {
184 compatible = "mpc5200b-xlb","mpc5200-xlb"; 177 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
185 reg = <1f00 100>; 178 reg = <1f00 100>;
186 }; 179 };
187 180
188 serial@2000 { // PSC1 181 serial@2000 { // PSC1
189 device_type = "serial"; 182 device_type = "serial";
190 compatible = "mpc5200b-psc-uart","mpc5200-psc-uart"; 183 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
191 port-number = <0>; // Logical port assignment 184 port-number = <0>; // Logical port assignment
192 reg = <2000 100>; 185 reg = <2000 100>;
193 interrupts = <2 1 0>; 186 interrupts = <2 1 0>;
@@ -196,7 +189,7 @@
196 189
197 // PSC2 in spi master mode 190 // PSC2 in spi master mode
198 spi@2200 { // PSC2 191 spi@2200 { // PSC2
199 compatible = "mpc5200b-psc-spi","mpc5200-psc-spi"; 192 compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
200 cell-index = <1>; 193 cell-index = <1>;
201 reg = <2200 100>; 194 reg = <2200 100>;
202 interrupts = <2 2 0>; 195 interrupts = <2 2 0>;
@@ -206,7 +199,7 @@
206 // PSC5 in uart mode 199 // PSC5 in uart mode
207 serial@2800 { // PSC5 200 serial@2800 { // PSC5
208 device_type = "serial"; 201 device_type = "serial";
209 compatible = "mpc5200b-psc-uart","mpc5200-psc-uart"; 202 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
210 port-number = <4>; // Logical port assignment 203 port-number = <4>; // Logical port assignment
211 reg = <2800 100>; 204 reg = <2800 100>;
212 interrupts = <2 c 0>; 205 interrupts = <2 c 0>;
@@ -215,22 +208,22 @@
215 208
216 ethernet@3000 { 209 ethernet@3000 {
217 device_type = "network"; 210 device_type = "network";
218 compatible = "mpc5200b-fec","mpc5200-fec"; 211 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
219 reg = <3000 800>; 212 reg = <3000 800>;
220 local-mac-address = [ 00 00 00 00 00 00 ]; /* Filled in by U-Boot */ 213 local-mac-address = [ 00 00 00 00 00 00 ];
221 interrupts = <2 5 0>; 214 interrupts = <2 5 0>;
222 interrupt-parent = <&mpc5200_pic>; 215 interrupt-parent = <&mpc5200_pic>;
223 }; 216 };
224 217
225 ata@3a00 { 218 ata@3a00 {
226 compatible = "mpc5200b-ata","mpc5200-ata"; 219 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
227 reg = <3a00 100>; 220 reg = <3a00 100>;
228 interrupts = <2 7 0>; 221 interrupts = <2 7 0>;
229 interrupt-parent = <&mpc5200_pic>; 222 interrupt-parent = <&mpc5200_pic>;
230 }; 223 };
231 224
232 i2c@3d40 { 225 i2c@3d40 {
233 compatible = "mpc5200b-i2c","mpc5200-i2c","fsl-i2c"; 226 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
234 reg = <3d40 40>; 227 reg = <3d40 40>;
235 interrupts = <2 10 0>; 228 interrupts = <2 10 0>;
236 interrupt-parent = <&mpc5200_pic>; 229 interrupt-parent = <&mpc5200_pic>;
@@ -238,13 +231,12 @@
238 }; 231 };
239 232
240 sram@8000 { 233 sram@8000 {
241 compatible = "mpc5200b-sram","mpc5200-sram"; 234 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
242 reg = <8000 4000>; 235 reg = <8000 4000>;
243 }; 236 };
244 }; 237 };
245 238
246 lpb { 239 lpb {
247 model = "fsl,lpb";
248 compatible = "fsl,lpb"; 240 compatible = "fsl,lpb";
249 #address-cells = <2>; 241 #address-cells = <2>;
250 #size-cells = <1>; 242 #size-cells = <1>;
@@ -286,7 +278,7 @@
286 #size-cells = <2>; 278 #size-cells = <2>;
287 #address-cells = <3>; 279 #address-cells = <3>;
288 device_type = "pci"; 280 device_type = "pci";
289 compatible = "mpc5200b-pci","mpc5200-pci"; 281 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
290 reg = <f0000d00 100>; 282 reg = <f0000d00 100>;
291 interrupt-map-mask = <f800 0 0 7>; 283 interrupt-map-mask = <f800 0 0 7>;
292 interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot 284 interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-30 22:34:47 -0500