diff options
Diffstat (limited to 'arch/powerpc/boot/dts/lite5200b.dts')
-rw-r--r-- | arch/powerpc/boot/dts/lite5200b.dts | 93 |
1 files changed, 41 insertions, 52 deletions
diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts index 3e06f58a0a71..571ba02accac 100644 --- a/arch/powerpc/boot/dts/lite5200b.dts +++ b/arch/powerpc/boot/dts/lite5200b.dts | |||
@@ -18,7 +18,6 @@ | |||
18 | 18 | ||
19 | / { | 19 | / { |
20 | model = "fsl,lite5200b"; | 20 | model = "fsl,lite5200b"; |
21 | // revision = "1.0"; | ||
22 | compatible = "fsl,lite5200b"; | 21 | compatible = "fsl,lite5200b"; |
23 | #address-cells = <1>; | 22 | #address-cells = <1>; |
24 | #size-cells = <1>; | 23 | #size-cells = <1>; |
@@ -46,30 +45,29 @@ | |||
46 | }; | 45 | }; |
47 | 46 | ||
48 | soc5200@f0000000 { | 47 | soc5200@f0000000 { |
49 | model = "fsl,mpc5200b"; | 48 | #address-cells = <1>; |
50 | compatible = "mpc5200"; | 49 | #size-cells = <1>; |
51 | revision = ""; // from bootloader | 50 | compatible = "fsl,mpc5200b-immr"; |
52 | device_type = "soc"; | ||
53 | ranges = <0 f0000000 0000c000>; | 51 | ranges = <0 f0000000 0000c000>; |
54 | reg = <f0000000 00000100>; | 52 | reg = <f0000000 00000100>; |
55 | bus-frequency = <0>; // from bootloader | 53 | bus-frequency = <0>; // from bootloader |
56 | system-frequency = <0>; // from bootloader | 54 | system-frequency = <0>; // from bootloader |
57 | 55 | ||
58 | cdm@200 { | 56 | cdm@200 { |
59 | compatible = "mpc5200b-cdm","mpc5200-cdm"; | 57 | compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; |
60 | reg = <200 38>; | 58 | reg = <200 38>; |
61 | }; | 59 | }; |
62 | 60 | ||
63 | mpc5200_pic: pic@500 { | 61 | mpc5200_pic: interrupt-controller@500 { |
64 | // 5200 interrupts are encoded into two levels; | 62 | // 5200 interrupts are encoded into two levels; |
65 | interrupt-controller; | 63 | interrupt-controller; |
66 | #interrupt-cells = <3>; | 64 | #interrupt-cells = <3>; |
67 | device_type = "interrupt-controller"; | 65 | device_type = "interrupt-controller"; |
68 | compatible = "mpc5200b-pic","mpc5200-pic"; | 66 | compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; |
69 | reg = <500 80>; | 67 | reg = <500 80>; |
70 | }; | 68 | }; |
71 | 69 | ||
72 | gpt@600 { // General Purpose Timer | 70 | timer@600 { // General Purpose Timer |
73 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 71 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
74 | cell-index = <0>; | 72 | cell-index = <0>; |
75 | reg = <600 10>; | 73 | reg = <600 10>; |
@@ -78,7 +76,7 @@ | |||
78 | fsl,has-wdt; | 76 | fsl,has-wdt; |
79 | }; | 77 | }; |
80 | 78 | ||
81 | gpt@610 { // General Purpose Timer | 79 | timer@610 { // General Purpose Timer |
82 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 80 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
83 | cell-index = <1>; | 81 | cell-index = <1>; |
84 | reg = <610 10>; | 82 | reg = <610 10>; |
@@ -86,7 +84,7 @@ | |||
86 | interrupt-parent = <&mpc5200_pic>; | 84 | interrupt-parent = <&mpc5200_pic>; |
87 | }; | 85 | }; |
88 | 86 | ||
89 | gpt@620 { // General Purpose Timer | 87 | timer@620 { // General Purpose Timer |
90 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 88 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
91 | cell-index = <2>; | 89 | cell-index = <2>; |
92 | reg = <620 10>; | 90 | reg = <620 10>; |
@@ -94,7 +92,7 @@ | |||
94 | interrupt-parent = <&mpc5200_pic>; | 92 | interrupt-parent = <&mpc5200_pic>; |
95 | }; | 93 | }; |
96 | 94 | ||
97 | gpt@630 { // General Purpose Timer | 95 | timer@630 { // General Purpose Timer |
98 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 96 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
99 | cell-index = <3>; | 97 | cell-index = <3>; |
100 | reg = <630 10>; | 98 | reg = <630 10>; |
@@ -102,7 +100,7 @@ | |||
102 | interrupt-parent = <&mpc5200_pic>; | 100 | interrupt-parent = <&mpc5200_pic>; |
103 | }; | 101 | }; |
104 | 102 | ||
105 | gpt@640 { // General Purpose Timer | 103 | timer@640 { // General Purpose Timer |
106 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 104 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
107 | cell-index = <4>; | 105 | cell-index = <4>; |
108 | reg = <640 10>; | 106 | reg = <640 10>; |
@@ -110,7 +108,7 @@ | |||
110 | interrupt-parent = <&mpc5200_pic>; | 108 | interrupt-parent = <&mpc5200_pic>; |
111 | }; | 109 | }; |
112 | 110 | ||
113 | gpt@650 { // General Purpose Timer | 111 | timer@650 { // General Purpose Timer |
114 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 112 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
115 | cell-index = <5>; | 113 | cell-index = <5>; |
116 | reg = <650 10>; | 114 | reg = <650 10>; |
@@ -118,7 +116,7 @@ | |||
118 | interrupt-parent = <&mpc5200_pic>; | 116 | interrupt-parent = <&mpc5200_pic>; |
119 | }; | 117 | }; |
120 | 118 | ||
121 | gpt@660 { // General Purpose Timer | 119 | timer@660 { // General Purpose Timer |
122 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 120 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
123 | cell-index = <6>; | 121 | cell-index = <6>; |
124 | reg = <660 10>; | 122 | reg = <660 10>; |
@@ -126,7 +124,7 @@ | |||
126 | interrupt-parent = <&mpc5200_pic>; | 124 | interrupt-parent = <&mpc5200_pic>; |
127 | }; | 125 | }; |
128 | 126 | ||
129 | gpt@670 { // General Purpose Timer | 127 | timer@670 { // General Purpose Timer |
130 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 128 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
131 | cell-index = <7>; | 129 | cell-index = <7>; |
132 | reg = <670 10>; | 130 | reg = <670 10>; |
@@ -135,25 +133,23 @@ | |||
135 | }; | 133 | }; |
136 | 134 | ||
137 | rtc@800 { // Real time clock | 135 | rtc@800 { // Real time clock |
138 | compatible = "mpc5200b-rtc","mpc5200-rtc"; | 136 | compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; |
139 | device_type = "rtc"; | 137 | device_type = "rtc"; |
140 | reg = <800 100>; | 138 | reg = <800 100>; |
141 | interrupts = <1 5 0 1 6 0>; | 139 | interrupts = <1 5 0 1 6 0>; |
142 | interrupt-parent = <&mpc5200_pic>; | 140 | interrupt-parent = <&mpc5200_pic>; |
143 | }; | 141 | }; |
144 | 142 | ||
145 | mscan@900 { | 143 | can@900 { |
146 | device_type = "mscan"; | 144 | compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; |
147 | compatible = "mpc5200b-mscan","mpc5200-mscan"; | ||
148 | cell-index = <0>; | 145 | cell-index = <0>; |
149 | interrupts = <2 11 0>; | 146 | interrupts = <2 11 0>; |
150 | interrupt-parent = <&mpc5200_pic>; | 147 | interrupt-parent = <&mpc5200_pic>; |
151 | reg = <900 80>; | 148 | reg = <900 80>; |
152 | }; | 149 | }; |
153 | 150 | ||
154 | mscan@980 { | 151 | can@980 { |
155 | device_type = "mscan"; | 152 | compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; |
156 | compatible = "mpc5200b-mscan","mpc5200-mscan"; | ||
157 | cell-index = <1>; | 153 | cell-index = <1>; |
158 | interrupts = <2 12 0>; | 154 | interrupts = <2 12 0>; |
159 | interrupt-parent = <&mpc5200_pic>; | 155 | interrupt-parent = <&mpc5200_pic>; |
@@ -161,38 +157,36 @@ | |||
161 | }; | 157 | }; |
162 | 158 | ||
163 | gpio@b00 { | 159 | gpio@b00 { |
164 | compatible = "mpc5200b-gpio","mpc5200-gpio"; | 160 | compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; |
165 | reg = <b00 40>; | 161 | reg = <b00 40>; |
166 | interrupts = <1 7 0>; | 162 | interrupts = <1 7 0>; |
167 | interrupt-parent = <&mpc5200_pic>; | 163 | interrupt-parent = <&mpc5200_pic>; |
168 | }; | 164 | }; |
169 | 165 | ||
170 | gpio-wkup@c00 { | 166 | gpio@c00 { |
171 | compatible = "mpc5200b-gpio-wkup","mpc5200-gpio-wkup"; | 167 | compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; |
172 | reg = <c00 40>; | 168 | reg = <c00 40>; |
173 | interrupts = <1 8 0 0 3 0>; | 169 | interrupts = <1 8 0 0 3 0>; |
174 | interrupt-parent = <&mpc5200_pic>; | 170 | interrupt-parent = <&mpc5200_pic>; |
175 | }; | 171 | }; |
176 | 172 | ||
177 | spi@f00 { | 173 | spi@f00 { |
178 | device_type = "spi"; | 174 | compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; |
179 | compatible = "mpc5200b-spi","mpc5200-spi"; | ||
180 | reg = <f00 20>; | 175 | reg = <f00 20>; |
181 | interrupts = <2 d 0 2 e 0>; | 176 | interrupts = <2 d 0 2 e 0>; |
182 | interrupt-parent = <&mpc5200_pic>; | 177 | interrupt-parent = <&mpc5200_pic>; |
183 | }; | 178 | }; |
184 | 179 | ||
185 | usb@1000 { | 180 | usb@1000 { |
186 | device_type = "usb-ohci-be"; | 181 | compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; |
187 | compatible = "mpc5200b-ohci","mpc5200-ohci","ohci-be"; | ||
188 | reg = <1000 ff>; | 182 | reg = <1000 ff>; |
189 | interrupts = <2 6 0>; | 183 | interrupts = <2 6 0>; |
190 | interrupt-parent = <&mpc5200_pic>; | 184 | interrupt-parent = <&mpc5200_pic>; |
191 | }; | 185 | }; |
192 | 186 | ||
193 | bestcomm@1200 { | 187 | dma-controller@1200 { |
194 | device_type = "dma-controller"; | 188 | device_type = "dma-controller"; |
195 | compatible = "mpc5200b-bestcomm","mpc5200-bestcomm"; | 189 | compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; |
196 | reg = <1200 80>; | 190 | reg = <1200 80>; |
197 | interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 | 191 | interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 |
198 | 3 4 0 3 5 0 3 6 0 3 7 0 | 192 | 3 4 0 3 5 0 3 6 0 3 7 0 |
@@ -202,13 +196,13 @@ | |||
202 | }; | 196 | }; |
203 | 197 | ||
204 | xlb@1f00 { | 198 | xlb@1f00 { |
205 | compatible = "mpc5200b-xlb","mpc5200-xlb"; | 199 | compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; |
206 | reg = <1f00 100>; | 200 | reg = <1f00 100>; |
207 | }; | 201 | }; |
208 | 202 | ||
209 | serial@2000 { // PSC1 | 203 | serial@2000 { // PSC1 |
210 | device_type = "serial"; | 204 | device_type = "serial"; |
211 | compatible = "mpc5200b-psc-uart","mpc5200-psc-uart"; | 205 | compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; |
212 | port-number = <0>; // Logical port assignment | 206 | port-number = <0>; // Logical port assignment |
213 | cell-index = <0>; | 207 | cell-index = <0>; |
214 | reg = <2000 100>; | 208 | reg = <2000 100>; |
@@ -218,8 +212,7 @@ | |||
218 | 212 | ||
219 | // PSC2 in ac97 mode example | 213 | // PSC2 in ac97 mode example |
220 | //ac97@2200 { // PSC2 | 214 | //ac97@2200 { // PSC2 |
221 | // device_type = "sound"; | 215 | // compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97"; |
222 | // compatible = "mpc5200b-psc-ac97","mpc5200-psc-ac97"; | ||
223 | // cell-index = <1>; | 216 | // cell-index = <1>; |
224 | // reg = <2200 100>; | 217 | // reg = <2200 100>; |
225 | // interrupts = <2 2 0>; | 218 | // interrupts = <2 2 0>; |
@@ -228,8 +221,7 @@ | |||
228 | 221 | ||
229 | // PSC3 in CODEC mode example | 222 | // PSC3 in CODEC mode example |
230 | //i2s@2400 { // PSC3 | 223 | //i2s@2400 { // PSC3 |
231 | // device_type = "sound"; | 224 | // compatible = "fsl,mpc5200b-psc-i2s"; //not 5200 compatible |
232 | // compatible = "mpc5200b-psc-i2s"; //not 5200 compatible | ||
233 | // cell-index = <2>; | 225 | // cell-index = <2>; |
234 | // reg = <2400 100>; | 226 | // reg = <2400 100>; |
235 | // interrupts = <2 3 0>; | 227 | // interrupts = <2 3 0>; |
@@ -239,7 +231,7 @@ | |||
239 | // PSC4 in uart mode example | 231 | // PSC4 in uart mode example |
240 | //serial@2600 { // PSC4 | 232 | //serial@2600 { // PSC4 |
241 | // device_type = "serial"; | 233 | // device_type = "serial"; |
242 | // compatible = "mpc5200b-psc-uart","mpc5200-psc-uart"; | 234 | // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; |
243 | // cell-index = <3>; | 235 | // cell-index = <3>; |
244 | // reg = <2600 100>; | 236 | // reg = <2600 100>; |
245 | // interrupts = <2 b 0>; | 237 | // interrupts = <2 b 0>; |
@@ -249,7 +241,7 @@ | |||
249 | // PSC5 in uart mode example | 241 | // PSC5 in uart mode example |
250 | //serial@2800 { // PSC5 | 242 | //serial@2800 { // PSC5 |
251 | // device_type = "serial"; | 243 | // device_type = "serial"; |
252 | // compatible = "mpc5200b-psc-uart","mpc5200-psc-uart"; | 244 | // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; |
253 | // cell-index = <4>; | 245 | // cell-index = <4>; |
254 | // reg = <2800 100>; | 246 | // reg = <2800 100>; |
255 | // interrupts = <2 c 0>; | 247 | // interrupts = <2 c 0>; |
@@ -258,8 +250,7 @@ | |||
258 | 250 | ||
259 | // PSC6 in spi mode example | 251 | // PSC6 in spi mode example |
260 | //spi@2c00 { // PSC6 | 252 | //spi@2c00 { // PSC6 |
261 | // device_type = "spi"; | 253 | // compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi"; |
262 | // compatible = "mpc5200b-psc-spi","mpc5200-psc-spi"; | ||
263 | // cell-index = <5>; | 254 | // cell-index = <5>; |
264 | // reg = <2c00 100>; | 255 | // reg = <2c00 100>; |
265 | // interrupts = <2 4 0>; | 256 | // interrupts = <2 4 0>; |
@@ -268,9 +259,9 @@ | |||
268 | 259 | ||
269 | ethernet@3000 { | 260 | ethernet@3000 { |
270 | device_type = "network"; | 261 | device_type = "network"; |
271 | compatible = "mpc5200b-fec","mpc5200-fec"; | 262 | compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; |
272 | reg = <3000 400>; | 263 | reg = <3000 400>; |
273 | mac-address = [ 02 03 04 05 06 07 ]; // Bad! | 264 | local-mac-address = [ 00 00 00 00 00 00 ]; |
274 | interrupts = <2 5 0>; | 265 | interrupts = <2 5 0>; |
275 | interrupt-parent = <&mpc5200_pic>; | 266 | interrupt-parent = <&mpc5200_pic>; |
276 | phy-handle = <&phy0>; | 267 | phy-handle = <&phy0>; |
@@ -279,8 +270,7 @@ | |||
279 | mdio@3000 { | 270 | mdio@3000 { |
280 | #address-cells = <1>; | 271 | #address-cells = <1>; |
281 | #size-cells = <0>; | 272 | #size-cells = <0>; |
282 | device_type = "mdio"; | 273 | compatible = "fsl,mpc5200b-mdio"; |
283 | compatible = "mpc5200b-fec-phy"; | ||
284 | reg = <3000 400>; // fec range, since we need to setup fec interrupts | 274 | reg = <3000 400>; // fec range, since we need to setup fec interrupts |
285 | interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. | 275 | interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. |
286 | interrupt-parent = <&mpc5200_pic>; | 276 | interrupt-parent = <&mpc5200_pic>; |
@@ -293,7 +283,7 @@ | |||
293 | 283 | ||
294 | ata@3a00 { | 284 | ata@3a00 { |
295 | device_type = "ata"; | 285 | device_type = "ata"; |
296 | compatible = "mpc5200b-ata","mpc5200-ata"; | 286 | compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; |
297 | reg = <3a00 100>; | 287 | reg = <3a00 100>; |
298 | interrupts = <2 7 0>; | 288 | interrupts = <2 7 0>; |
299 | interrupt-parent = <&mpc5200_pic>; | 289 | interrupt-parent = <&mpc5200_pic>; |
@@ -302,7 +292,7 @@ | |||
302 | i2c@3d00 { | 292 | i2c@3d00 { |
303 | #address-cells = <1>; | 293 | #address-cells = <1>; |
304 | #size-cells = <0>; | 294 | #size-cells = <0>; |
305 | compatible = "mpc5200b-i2c","mpc5200-i2c","fsl-i2c"; | 295 | compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; |
306 | cell-index = <0>; | 296 | cell-index = <0>; |
307 | reg = <3d00 40>; | 297 | reg = <3d00 40>; |
308 | interrupts = <2 f 0>; | 298 | interrupts = <2 f 0>; |
@@ -313,7 +303,7 @@ | |||
313 | i2c@3d40 { | 303 | i2c@3d40 { |
314 | #address-cells = <1>; | 304 | #address-cells = <1>; |
315 | #size-cells = <0>; | 305 | #size-cells = <0>; |
316 | compatible = "mpc5200b-i2c","mpc5200-i2c","fsl-i2c"; | 306 | compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; |
317 | cell-index = <1>; | 307 | cell-index = <1>; |
318 | reg = <3d40 40>; | 308 | reg = <3d40 40>; |
319 | interrupts = <2 10 0>; | 309 | interrupts = <2 10 0>; |
@@ -321,8 +311,7 @@ | |||
321 | fsl5200-clocking; | 311 | fsl5200-clocking; |
322 | }; | 312 | }; |
323 | sram@8000 { | 313 | sram@8000 { |
324 | device_type = "sram"; | 314 | compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram"; |
325 | compatible = "mpc5200b-sram","mpc5200-sram","sram"; | ||
326 | reg = <8000 4000>; | 315 | reg = <8000 4000>; |
327 | }; | 316 | }; |
328 | }; | 317 | }; |
@@ -332,7 +321,7 @@ | |||
332 | #size-cells = <2>; | 321 | #size-cells = <2>; |
333 | #address-cells = <3>; | 322 | #address-cells = <3>; |
334 | device_type = "pci"; | 323 | device_type = "pci"; |
335 | compatible = "mpc5200b-pci","mpc5200-pci"; | 324 | compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci"; |
336 | reg = <f0000d00 100>; | 325 | reg = <f0000d00 100>; |
337 | interrupt-map-mask = <f800 0 0 7>; | 326 | interrupt-map-mask = <f800 0 0 7>; |
338 | interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot | 327 | interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot |