diff options
Diffstat (limited to 'arch/powerpc/boot/dts/lite5200.dts')
| -rw-r--r-- | arch/powerpc/boot/dts/lite5200.dts | 59 |
1 files changed, 28 insertions, 31 deletions
diff --git a/arch/powerpc/boot/dts/lite5200.dts b/arch/powerpc/boot/dts/lite5200.dts index d29308fe4c24..bc45f5fbb060 100644 --- a/arch/powerpc/boot/dts/lite5200.dts +++ b/arch/powerpc/boot/dts/lite5200.dts | |||
| @@ -19,7 +19,7 @@ | |||
| 19 | / { | 19 | / { |
| 20 | model = "fsl,lite5200"; | 20 | model = "fsl,lite5200"; |
| 21 | // revision = "1.0"; | 21 | // revision = "1.0"; |
| 22 | compatible = "fsl,lite5200\0generic-mpc5200"; | 22 | compatible = "fsl,lite5200","generic-mpc5200"; |
| 23 | #address-cells = <1>; | 23 | #address-cells = <1>; |
| 24 | #size-cells = <1>; | 24 | #size-cells = <1>; |
| 25 | 25 | ||
| @@ -37,7 +37,6 @@ | |||
| 37 | timebase-frequency = <0>; // from bootloader | 37 | timebase-frequency = <0>; // from bootloader |
| 38 | bus-frequency = <0>; // from bootloader | 38 | bus-frequency = <0>; // from bootloader |
| 39 | clock-frequency = <0>; // from bootloader | 39 | clock-frequency = <0>; // from bootloader |
| 40 | 32-bit; | ||
| 41 | }; | 40 | }; |
| 42 | }; | 41 | }; |
| 43 | 42 | ||
| @@ -50,10 +49,9 @@ | |||
| 50 | model = "fsl,mpc5200"; | 49 | model = "fsl,mpc5200"; |
| 51 | compatible = "mpc5200"; | 50 | compatible = "mpc5200"; |
| 52 | revision = ""; // from bootloader | 51 | revision = ""; // from bootloader |
| 53 | #interrupt-cells = <3>; | ||
| 54 | device_type = "soc"; | 52 | device_type = "soc"; |
| 55 | ranges = <0 f0000000 f0010000>; | 53 | ranges = <0 f0000000 0000c000>; |
| 56 | reg = <f0000000 00010000>; | 54 | reg = <f0000000 00000100>; |
| 57 | bus-frequency = <0>; // from bootloader | 55 | bus-frequency = <0>; // from bootloader |
| 58 | system-frequency = <0>; // from bootloader | 56 | system-frequency = <0>; // from bootloader |
| 59 | 57 | ||
| @@ -69,7 +67,6 @@ | |||
| 69 | device_type = "interrupt-controller"; | 67 | device_type = "interrupt-controller"; |
| 70 | compatible = "mpc5200-pic"; | 68 | compatible = "mpc5200-pic"; |
| 71 | reg = <500 80>; | 69 | reg = <500 80>; |
| 72 | built-in; | ||
| 73 | }; | 70 | }; |
| 74 | 71 | ||
| 75 | gpt@600 { // General Purpose Timer | 72 | gpt@600 { // General Purpose Timer |
| @@ -185,27 +182,6 @@ | |||
| 185 | interrupt-parent = <&mpc5200_pic>; | 182 | interrupt-parent = <&mpc5200_pic>; |
| 186 | }; | 183 | }; |
| 187 | 184 | ||
| 188 | pci@0d00 { | ||
| 189 | #interrupt-cells = <1>; | ||
| 190 | #size-cells = <2>; | ||
| 191 | #address-cells = <3>; | ||
| 192 | device_type = "pci"; | ||
| 193 | compatible = "mpc5200-pci"; | ||
| 194 | reg = <d00 100>; | ||
| 195 | interrupt-map-mask = <f800 0 0 7>; | ||
| 196 | interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 | ||
| 197 | c000 0 0 2 &mpc5200_pic 0 0 3 | ||
| 198 | c000 0 0 3 &mpc5200_pic 0 0 3 | ||
| 199 | c000 0 0 4 &mpc5200_pic 0 0 3>; | ||
| 200 | clock-frequency = <0>; // From boot loader | ||
| 201 | interrupts = <2 8 0 2 9 0 2 a 0>; | ||
| 202 | interrupt-parent = <&mpc5200_pic>; | ||
| 203 | bus-range = <0 0>; | ||
| 204 | ranges = <42000000 0 80000000 80000000 0 20000000 | ||
| 205 | 02000000 0 a0000000 a0000000 0 10000000 | ||
| 206 | 01000000 0 00000000 b0000000 0 01000000>; | ||
| 207 | }; | ||
| 208 | |||
| 209 | spi@f00 { | 185 | spi@f00 { |
| 210 | device_type = "spi"; | 186 | device_type = "spi"; |
| 211 | compatible = "mpc5200-spi"; | 187 | compatible = "mpc5200-spi"; |
| @@ -216,7 +192,7 @@ | |||
| 216 | 192 | ||
| 217 | usb@1000 { | 193 | usb@1000 { |
| 218 | device_type = "usb-ohci-be"; | 194 | device_type = "usb-ohci-be"; |
| 219 | compatible = "mpc5200-ohci\0ohci-be"; | 195 | compatible = "mpc5200-ohci","ohci-be"; |
| 220 | reg = <1000 ff>; | 196 | reg = <1000 ff>; |
| 221 | interrupts = <2 6 0>; | 197 | interrupts = <2 6 0>; |
| 222 | interrupt-parent = <&mpc5200_pic>; | 198 | interrupt-parent = <&mpc5200_pic>; |
| @@ -317,7 +293,7 @@ | |||
| 317 | 293 | ||
| 318 | i2c@3d00 { | 294 | i2c@3d00 { |
| 319 | device_type = "i2c"; | 295 | device_type = "i2c"; |
| 320 | compatible = "mpc5200-i2c\0fsl-i2c"; | 296 | compatible = "mpc5200-i2c","fsl-i2c"; |
| 321 | cell-index = <0>; | 297 | cell-index = <0>; |
| 322 | reg = <3d00 40>; | 298 | reg = <3d00 40>; |
| 323 | interrupts = <2 f 0>; | 299 | interrupts = <2 f 0>; |
| @@ -327,7 +303,7 @@ | |||
| 327 | 303 | ||
| 328 | i2c@3d40 { | 304 | i2c@3d40 { |
| 329 | device_type = "i2c"; | 305 | device_type = "i2c"; |
| 330 | compatible = "mpc5200-i2c\0fsl-i2c"; | 306 | compatible = "mpc5200-i2c","fsl-i2c"; |
| 331 | cell-index = <1>; | 307 | cell-index = <1>; |
| 332 | reg = <3d40 40>; | 308 | reg = <3d40 40>; |
| 333 | interrupts = <2 10 0>; | 309 | interrupts = <2 10 0>; |
| @@ -336,8 +312,29 @@ | |||
| 336 | }; | 312 | }; |
| 337 | sram@8000 { | 313 | sram@8000 { |
| 338 | device_type = "sram"; | 314 | device_type = "sram"; |
| 339 | compatible = "mpc5200-sram\0sram"; | 315 | compatible = "mpc5200-sram","sram"; |
| 340 | reg = <8000 4000>; | 316 | reg = <8000 4000>; |
| 341 | }; | 317 | }; |
| 342 | }; | 318 | }; |
| 319 | |||
| 320 | pci@f0000d00 { | ||
| 321 | #interrupt-cells = <1>; | ||
| 322 | #size-cells = <2>; | ||
| 323 | #address-cells = <3>; | ||
| 324 | device_type = "pci"; | ||
| 325 | compatible = "mpc5200-pci"; | ||
| 326 | reg = <f0000d00 100>; | ||
| 327 | interrupt-map-mask = <f800 0 0 7>; | ||
| 328 | interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 | ||
| 329 | c000 0 0 2 &mpc5200_pic 0 0 3 | ||
| 330 | c000 0 0 3 &mpc5200_pic 0 0 3 | ||
| 331 | c000 0 0 4 &mpc5200_pic 0 0 3>; | ||
| 332 | clock-frequency = <0>; // From boot loader | ||
| 333 | interrupts = <2 8 0 2 9 0 2 a 0>; | ||
| 334 | interrupt-parent = <&mpc5200_pic>; | ||
| 335 | bus-range = <0 0>; | ||
| 336 | ranges = <42000000 0 80000000 80000000 0 20000000 | ||
| 337 | 02000000 0 a0000000 a0000000 0 10000000 | ||
| 338 | 01000000 0 00000000 b0000000 0 01000000>; | ||
| 339 | }; | ||
| 343 | }; | 340 | }; |