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diff --git a/arch/powerpc/boot/dts/lite5200.dts b/arch/powerpc/boot/dts/lite5200.dts
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1/*
2 * Lite5200 board Device Tree Source
3 *
4 * Copyright 2006 Secret Lab Technologies Ltd.
5 * Grant Likely <grant.likely@secretlab.ca>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13/ {
14 model = "Lite5200";
15 compatible = "lite5200\0lite52xx\0mpc5200\0mpc52xx";
16 #address-cells = <1>;
17 #size-cells = <1>;
18
19 cpus {
20 #cpus = <1>;
21 #address-cells = <1>;
22 #size-cells = <0>;
23
24 PowerPC,5200@0 {
25 device_type = "cpu";
26 reg = <0>;
27 d-cache-line-size = <20>;
28 i-cache-line-size = <20>;
29 d-cache-size = <4000>; // L1, 16K
30 i-cache-size = <4000>; // L1, 16K
31 timebase-frequency = <0>; // from bootloader
32 bus-frequency = <0>; // from bootloader
33 clock-frequency = <0>; // from bootloader
34 32-bit;
35 };
36 };
37
38 memory {
39 device_type = "memory";
40 reg = <00000000 04000000>; // 64MB
41 };
42
43 soc5200@f0000000 {
44 #interrupt-cells = <3>;
45 device_type = "soc";
46 ranges = <0 f0000000 f0010000>;
47 reg = <f0000000 00010000>;
48 bus-frequency = <0>; // from bootloader
49
50 cdm@200 {
51 compatible = "mpc5200-cdm\0mpc52xx-cdm";
52 reg = <200 38>;
53 };
54
55 pic@500 {
56 // 5200 interrupts are encoded into two levels;
57 linux,phandle = <500>;
58 interrupt-controller;
59 #interrupt-cells = <3>;
60 device_type = "interrupt-controller";
61 compatible = "mpc5200-pic\0mpc52xx-pic";
62 reg = <500 80>;
63 built-in;
64 };
65
66 gpt@600 { // General Purpose Timer
67 compatible = "mpc5200-gpt\0mpc52xx-gpt";
68 device_type = "gpt";
69 reg = <600 10>;
70 interrupts = <1 9 0>;
71 interrupt-parent = <500>;
72 };
73
74 gpt@610 { // General Purpose Timer
75 compatible = "mpc5200-gpt\0mpc52xx-gpt";
76 device_type = "gpt";
77 reg = <610 10>;
78 interrupts = <1 a 0>;
79 interrupt-parent = <500>;
80 };
81
82 gpt@620 { // General Purpose Timer
83 compatible = "mpc5200-gpt\0mpc52xx-gpt";
84 device_type = "gpt";
85 reg = <620 10>;
86 interrupts = <1 b 0>;
87 interrupt-parent = <500>;
88 };
89
90 gpt@630 { // General Purpose Timer
91 compatible = "mpc5200-gpt\0mpc52xx-gpt";
92 device_type = "gpt";
93 reg = <630 10>;
94 interrupts = <1 c 0>;
95 interrupt-parent = <500>;
96 };
97
98 gpt@640 { // General Purpose Timer
99 compatible = "mpc5200-gpt\0mpc52xx-gpt";
100 device_type = "gpt";
101 reg = <640 10>;
102 interrupts = <1 d 0>;
103 interrupt-parent = <500>;
104 };
105
106 gpt@650 { // General Purpose Timer
107 compatible = "mpc5200-gpt\0mpc52xx-gpt";
108 device_type = "gpt";
109 reg = <650 10>;
110 interrupts = <1 e 0>;
111 interrupt-parent = <500>;
112 };
113
114 gpt@660 { // General Purpose Timer
115 compatible = "mpc5200-gpt\0mpc52xx-gpt";
116 device_type = "gpt";
117 reg = <660 10>;
118 interrupts = <1 f 0>;
119 interrupt-parent = <500>;
120 };
121
122 gpt@670 { // General Purpose Timer
123 compatible = "mpc5200-gpt\0mpc52xx-gpt";
124 device_type = "gpt";
125 reg = <670 10>;
126 interrupts = <1 10 0>;
127 interrupt-parent = <500>;
128 };
129
130 rtc@800 { // Real time clock
131 compatible = "mpc5200-rtc\0mpc52xx-rtc";
132 device_type = "rtc";
133 reg = <800 100>;
134 interrupts = <1 5 0 1 6 0>;
135 interrupt-parent = <500>;
136 };
137
138 mscan@900 {
139 device_type = "mscan";
140 compatible = "mpc5200-mscan\0mpc52xx-mscan";
141 interrupts = <2 11 0>;
142 interrupt-parent = <500>;
143 reg = <900 80>;
144 };
145
146 mscan@980 {
147 device_type = "mscan";
148 compatible = "mpc5200-mscan\0mpc52xx-mscan";
149 interrupts = <1 12 0>;
150 interrupt-parent = <500>;
151 reg = <980 80>;
152 };
153
154 gpio@b00 {
155 compatible = "mpc5200-gpio\0mpc52xx-gpio";
156 reg = <b00 40>;
157 interrupts = <1 7 0>;
158 interrupt-parent = <500>;
159 };
160
161 gpio-wkup@b00 {
162 compatible = "mpc5200-gpio-wkup\0mpc52xx-gpio-wkup";
163 reg = <c00 40>;
164 interrupts = <1 8 0 0 3 0>;
165 interrupt-parent = <500>;
166 };
167
168 pci@0d00 {
169 #interrupt-cells = <1>;
170 #size-cells = <2>;
171 #address-cells = <3>;
172 device_type = "pci";
173 compatible = "mpc5200-pci\0mpc52xx-pci";
174 reg = <d00 100>;
175 interrupt-map-mask = <f800 0 0 7>;
176 interrupt-map = <c000 0 0 1 500 0 0 3
177 c000 0 0 2 500 0 0 3
178 c000 0 0 3 500 0 0 3
179 c000 0 0 4 500 0 0 3>;
180 clock-frequency = <0>; // From boot loader
181 interrupts = <2 8 0 2 9 0 2 a 0>;
182 interrupt-parent = <500>;
183 bus-range = <0 0>;
184 ranges = <42000000 0 80000000 80000000 0 20000000
185 02000000 0 a0000000 a0000000 0 10000000
186 01000000 0 00000000 b0000000 0 01000000>;
187 };
188
189 spi@f00 {
190 device_type = "spi";
191 compatible = "mpc5200-spi\0mpc52xx-spi";
192 reg = <f00 20>;
193 interrupts = <2 d 0 2 e 0>;
194 interrupt-parent = <500>;
195 };
196
197 usb@1000 {
198 device_type = "usb-ohci-be";
199 compatible = "mpc5200-ohci\0mpc52xx-ohci\0ohci-be";
200 reg = <1000 ff>;
201 interrupts = <2 6 0>;
202 interrupt-parent = <500>;
203 };
204
205 bestcomm@1200 {
206 device_type = "dma-controller";
207 compatible = "mpc5200-bestcomm\0mpc52xx-bestcomm";
208 reg = <1200 80>;
209 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
210 3 4 0 3 5 0 3 6 0 3 7 0
211 3 8 0 3 9 0 3 a 0 3 b 0
212 3 c 0 3 d 0 3 e 0 3 f 0>;
213 interrupt-parent = <500>;
214 };
215
216 xlb@1f00 {
217 compatible = "mpc5200-xlb\0mpc52xx-xlb";
218 reg = <1f00 100>;
219 };
220
221 serial@2000 { // PSC1
222 device_type = "serial";
223 compatible = "mpc5200-psc-uart\0mpc52xx-psc-uart";
224 port-number = <0>; // Logical port assignment
225 reg = <2000 100>;
226 interrupts = <2 1 0>;
227 interrupt-parent = <500>;
228 };
229
230 // PSC2 in spi mode example
231 spi@2200 { // PSC2
232 device_type = "spi";
233 compatible = "mpc5200-psc-spi\0mpc52xx-psc-spi";
234 reg = <2200 100>;
235 interrupts = <2 2 0>;
236 interrupt-parent = <500>;
237 };
238
239 // PSC3 in CODEC mode example
240 i2s@2400 { // PSC3
241 device_type = "i2s";
242 compatible = "mpc5200-psc-i2s\0mpc52xx-psc-i2s";
243 reg = <2400 100>;
244 interrupts = <2 3 0>;
245 interrupt-parent = <500>;
246 };
247
248 // PSC4 unconfigured
249 //serial@2600 { // PSC4
250 // device_type = "serial";
251 // compatible = "mpc5200-psc-uart\0mpc52xx-psc-uart";
252 // reg = <2600 100>;
253 // interrupts = <2 b 0>;
254 // interrupt-parent = <500>;
255 //};
256
257 // PSC5 unconfigured
258 //serial@2800 { // PSC5
259 // device_type = "serial";
260 // compatible = "mpc5200-psc-uart\0mpc52xx-psc-uart";
261 // reg = <2800 100>;
262 // interrupts = <2 c 0>;
263 // interrupt-parent = <500>;
264 //};
265
266 // PSC6 in AC97 mode example
267 ac97@2c00 { // PSC6
268 device_type = "ac97";
269 compatible = "mpc5200-psc-ac97\0mpc52xx-psc-ac97";
270 reg = <2c00 100>;
271 interrupts = <2 4 0>;
272 interrupt-parent = <500>;
273 };
274
275 ethernet@3000 {
276 device_type = "network";
277 compatible = "mpc5200-fec\0mpc52xx-fec";
278 reg = <3000 800>;
279 mac-address = [ 02 03 04 05 06 07 ]; // Bad!
280 interrupts = <2 5 0>;
281 interrupt-parent = <500>;
282 };
283
284 ata@3a00 {
285 device_type = "ata";
286 compatible = "mpc5200-ata\0mpc52xx-ata";
287 reg = <3a00 100>;
288 interrupts = <2 7 0>;
289 interrupt-parent = <500>;
290 };
291
292 i2c@3d00 {
293 device_type = "i2c";
294 compatible = "mpc5200-i2c\0mpc52xx-i2c";
295 reg = <3d00 40>;
296 interrupts = <2 f 0>;
297 interrupt-parent = <500>;
298 };
299
300 i2c@3d40 {
301 device_type = "i2c";
302 compatible = "mpc5200-i2c\0mpc52xx-i2c";
303 reg = <3d40 40>;
304 interrupts = <2 10 0>;
305 interrupt-parent = <500>;
306 };
307 sram@8000 {
308 device_type = "sram";
309 compatible = "mpc5200-sram\0mpc52xx-sram\0sram";
310 reg = <8000 4000>;
311 };
312 };
313};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-17 12:33:16 -0500