1 files changed, 128 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
new file mode 100644
index 000000000000..a93c55a88560
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
@@ -0,0 +1,128 @@
+/*
+ * T4240 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/dts-v1/;
+/include/ "e6500_power_isa.dtsi"
+/ {
+        compatible = "fsl,T4240";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+        aliases {
+                ccsr = &soc;
+                dcsr = &dcsr;
+                serial0 = &serial0;
+                serial1 = &serial1;
+                serial2 = &serial2;
+                serial3 = &serial3;
+                crypto = &crypto;
+                pci0 = &pci0;
+                pci1 = &pci1;
+                pci2 = &pci2;
+                pci3 = &pci3;
+                dma0 = &dma0;
+                dma1 = &dma1;
+                sdhc = &sdhc;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu0: PowerPC,e6500@0 {
+                        device_type = "cpu";
+                        reg = <0 1>;
+                        next-level-cache = <&L2_1>;
+                };
+                cpu1: PowerPC,e6500@2 {
+                        device_type = "cpu";
+                        reg = <2 3>;
+                        next-level-cache = <&L2_1>;
+                };
+                cpu2: PowerPC,e6500@4 {
+                        device_type = "cpu";
+                        reg = <4 5>;
+                        next-level-cache = <&L2_1>;
+                };
+                cpu3: PowerPC,e6500@6 {
+                        device_type = "cpu";
+                        reg = <6 7>;
+                        next-level-cache = <&L2_1>;
+                };
+                cpu4: PowerPC,e6500@8 {
+                        device_type = "cpu";
+                        reg = <8 9>;
+                        next-level-cache = <&L2_2>;
+                };
+                cpu5: PowerPC,e6500@10 {
+                        device_type = "cpu";
+                        reg = <10 11>;
+                        next-level-cache = <&L2_2>;
+                };
+                cpu6: PowerPC,e6500@12 {
+                        device_type = "cpu";
+                        reg = <12 13>;
+                        next-level-cache = <&L2_2>;
+                };
+                cpu7: PowerPC,e6500@14 {
+                        device_type = "cpu";
+                        reg = <14 15>;
+                        next-level-cache = <&L2_2>;
+                };
+                cpu8: PowerPC,e6500@16 {
+                        device_type = "cpu";
+                        reg = <16 17>;
+                        next-level-cache = <&L2_3>;
+                };
+                cpu9: PowerPC,e6500@18 {
+                        device_type = "cpu";
+                        reg = <18 19>;
+                        next-level-cache = <&L2_3>;
+                };
+                cpu10: PowerPC,e6500@20 {
+                        device_type = "cpu";
+                        reg = <20 21>;
+                        next-level-cache = <&L2_3>;
+                };
+                cpu11: PowerPC,e6500@22 {
+                        device_type = "cpu";
+                        reg = <22 23>;
+                        next-level-cache = <&L2_3>;
+                };
+        };
+};

diff --git a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi new file mode 100644 index 000000000000..a93c55a88560 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
@@ -0,0 +1,128 @@
	1	/*
	2	* T4240 Silicon/SoC Device Tree Source (pre include)
	3	*
	4	* Copyright 2012 Freescale Semiconductor Inc.
	5	*
	6	* Redistribution and use in source and binary forms, with or without
	7	* modification, are permitted provided that the following conditions are met:
	8	* * Redistributions of source code must retain the above copyright
	9	* notice, this list of conditions and the following disclaimer.
	10	* * Redistributions in binary form must reproduce the above copyright
	11	* notice, this list of conditions and the following disclaimer in the
	12	* documentation and/or other materials provided with the distribution.
	13	* * Neither the name of Freescale Semiconductor nor the
	14	* names of its contributors may be used to endorse or promote products
	15	* derived from this software without specific prior written permission.
	16	*
	17	*
	18	* ALTERNATIVELY, this software may be distributed under the terms of the
	19	* GNU General Public License ("GPL") as published by the Free Software
	20	* Foundation, either version 2 of that License or (at your option) any
	21	* later version.
	22	*
	23	* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
	24	* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	25	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	26	* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
	27	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	28	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	29	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	30	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	31	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	32	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	33	*/
	34
	35	/dts-v1/;
	36
	37	/include/ "e6500_power_isa.dtsi"
	38
	39	/ {
	40	compatible = "fsl,T4240";
	41	#address-cells = <2>;
	42	#size-cells = <2>;
	43	interrupt-parent = <&mpic>;
	44
	45	aliases {
	46	ccsr = &soc;
	47	dcsr = &dcsr;
	48
	49	serial0 = &serial0;
	50	serial1 = &serial1;
	51	serial2 = &serial2;
	52	serial3 = &serial3;
	53	crypto = &crypto;
	54	pci0 = &pci0;
	55	pci1 = &pci1;
	56	pci2 = &pci2;
	57	pci3 = &pci3;
	58	dma0 = &dma0;
	59	dma1 = &dma1;
	60	sdhc = &sdhc;
	61	};
	62
	63	cpus {
	64	#address-cells = <1>;
	65	#size-cells = <0>;
	66
	67	cpu0: PowerPC,e6500@0 {
	68	device_type = "cpu";
	69	reg = <0 1>;
	70	next-level-cache = <&L2_1>;
	71	};
	72	cpu1: PowerPC,e6500@2 {
	73	device_type = "cpu";
	74	reg = <2 3>;
	75	next-level-cache = <&L2_1>;
	76	};
	77	cpu2: PowerPC,e6500@4 {
	78	device_type = "cpu";
	79	reg = <4 5>;
	80	next-level-cache = <&L2_1>;
	81	};
	82	cpu3: PowerPC,e6500@6 {
	83	device_type = "cpu";
	84	reg = <6 7>;
	85	next-level-cache = <&L2_1>;
	86	};
	87	cpu4: PowerPC,e6500@8 {
	88	device_type = "cpu";
	89	reg = <8 9>;
	90	next-level-cache = <&L2_2>;
	91	};
	92	cpu5: PowerPC,e6500@10 {
	93	device_type = "cpu";
	94	reg = <10 11>;
	95	next-level-cache = <&L2_2>;
	96	};
	97	cpu6: PowerPC,e6500@12 {
	98	device_type = "cpu";
	99	reg = <12 13>;
	100	next-level-cache = <&L2_2>;
	101	};
	102	cpu7: PowerPC,e6500@14 {
	103	device_type = "cpu";
	104	reg = <14 15>;
	105	next-level-cache = <&L2_2>;
	106	};
	107	cpu8: PowerPC,e6500@16 {
	108	device_type = "cpu";
	109	reg = <16 17>;
	110	next-level-cache = <&L2_3>;
	111	};
	112	cpu9: PowerPC,e6500@18 {
	113	device_type = "cpu";
	114	reg = <18 19>;
	115	next-level-cache = <&L2_3>;
	116	};
	117	cpu10: PowerPC,e6500@20 {
	118	device_type = "cpu";
	119	reg = <20 21>;
	120	next-level-cache = <&L2_3>;
	121	};
	122	cpu11: PowerPC,e6500@22 {
	123	device_type = "cpu";
	124	reg = <22 23>;
	125	next-level-cache = <&L2_3>;
	126	};
	127	};
	128	};