1 files changed, 143 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
new file mode 100644
index 000000000000..b9556ee3a639
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
@@ -0,0 +1,143 @@
+/*
+ * P4080/P4040 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/dts-v1/;
+/ {
+        compatible = "fsl,P4080";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+        aliases {
+                ccsr = &soc;
+                dcsr = &dcsr;
+                serial0 = &serial0;
+                serial1 = &serial1;
+                serial2 = &serial2;
+                serial3 = &serial3;
+                pci0 = &pci0;
+                pci1 = &pci1;
+                pci2 = &pci2;
+                usb0 = &usb0;
+                usb1 = &usb1;
+                dma0 = &dma0;
+                dma1 = &dma1;
+                sdhc = &sdhc;
+                msi0 = &msi0;
+                msi1 = &msi1;
+                msi2 = &msi2;
+                crypto = &crypto;
+                sec_jr0 = &sec_jr0;
+                sec_jr1 = &sec_jr1;
+                sec_jr2 = &sec_jr2;
+                sec_jr3 = &sec_jr3;
+                rtic_a = &rtic_a;
+                rtic_b = &rtic_b;
+                rtic_c = &rtic_c;
+                rtic_d = &rtic_d;
+                sec_mon = &sec_mon;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu0: PowerPC,e500mc@0 {
+                        device_type = "cpu";
+                        reg = <0>;
+                        next-level-cache = <&L2_0>;
+                        L2_0: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+                cpu1: PowerPC,e500mc@1 {
+                        device_type = "cpu";
+                        reg = <1>;
+                        next-level-cache = <&L2_1>;
+                        L2_1: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+                cpu2: PowerPC,e500mc@2 {
+                        device_type = "cpu";
+                        reg = <2>;
+                        next-level-cache = <&L2_2>;
+                        L2_2: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+                cpu3: PowerPC,e500mc@3 {
+                        device_type = "cpu";
+                        reg = <3>;
+                        next-level-cache = <&L2_3>;
+                        L2_3: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+                cpu4: PowerPC,e500mc@4 {
+                        device_type = "cpu";
+                        reg = <4>;
+                        next-level-cache = <&L2_4>;
+                        L2_4: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+                cpu5: PowerPC,e500mc@5 {
+                        device_type = "cpu";
+                        reg = <5>;
+                        next-level-cache = <&L2_5>;
+                        L2_5: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+                cpu6: PowerPC,e500mc@6 {
+                        device_type = "cpu";
+                        reg = <6>;
+                        next-level-cache = <&L2_6>;
+                        L2_6: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+                cpu7: PowerPC,e500mc@7 {
+                        device_type = "cpu";
+                        reg = <7>;
+                        next-level-cache = <&L2_7>;
+                        L2_7: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+        };
+};

diff --git a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi new file mode 100644 index 000000000000..b9556ee3a639 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
@@ -0,0 +1,143 @@
	1	/*
	2	* P4080/P4040 Silicon/SoC Device Tree Source (pre include)
	3	*
	4	* Copyright 2011 Freescale Semiconductor Inc.
	5	*
	6	* Redistribution and use in source and binary forms, with or without
	7	* modification, are permitted provided that the following conditions are met:
	8	* * Redistributions of source code must retain the above copyright
	9	* notice, this list of conditions and the following disclaimer.
	10	* * Redistributions in binary form must reproduce the above copyright
	11	* notice, this list of conditions and the following disclaimer in the
	12	* documentation and/or other materials provided with the distribution.
	13	* * Neither the name of Freescale Semiconductor nor the
	14	* names of its contributors may be used to endorse or promote products
	15	* derived from this software without specific prior written permission.
	16	*
	17	*
	18	* ALTERNATIVELY, this software may be distributed under the terms of the
	19	* GNU General Public License ("GPL") as published by the Free Software
	20	* Foundation, either version 2 of that License or (at your option) any
	21	* later version.
	22	*
	23	* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
	24	* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	25	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	26	* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
	27	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	28	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	29	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	30	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	31	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	32	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	33	*/
	34
	35	/dts-v1/;
	36	/ {
	37	compatible = "fsl,P4080";
	38	#address-cells = <2>;
	39	#size-cells = <2>;
	40	interrupt-parent = <&mpic>;
	41
	42	aliases {
	43	ccsr = &soc;
	44	dcsr = &dcsr;
	45
	46	serial0 = &serial0;
	47	serial1 = &serial1;
	48	serial2 = &serial2;
	49	serial3 = &serial3;
	50	pci0 = &pci0;
	51	pci1 = &pci1;
	52	pci2 = &pci2;
	53	usb0 = &usb0;
	54	usb1 = &usb1;
	55	dma0 = &dma0;
	56	dma1 = &dma1;
	57	sdhc = &sdhc;
	58	msi0 = &msi0;
	59	msi1 = &msi1;
	60	msi2 = &msi2;
	61
	62	crypto = &crypto;
	63	sec_jr0 = &sec_jr0;
	64	sec_jr1 = &sec_jr1;
	65	sec_jr2 = &sec_jr2;
	66	sec_jr3 = &sec_jr3;
	67	rtic_a = &rtic_a;
	68	rtic_b = &rtic_b;
	69	rtic_c = &rtic_c;
	70	rtic_d = &rtic_d;
	71	sec_mon = &sec_mon;
	72	};
	73
	74	cpus {
	75	#address-cells = <1>;
	76	#size-cells = <0>;
	77
	78	cpu0: PowerPC,e500mc@0 {
	79	device_type = "cpu";
	80	reg = <0>;
	81	next-level-cache = <&L2_0>;
	82	L2_0: l2-cache {
	83	next-level-cache = <&cpc>;
	84	};
	85	};
	86	cpu1: PowerPC,e500mc@1 {
	87	device_type = "cpu";
	88	reg = <1>;
	89	next-level-cache = <&L2_1>;
	90	L2_1: l2-cache {
	91	next-level-cache = <&cpc>;
	92	};
	93	};
	94	cpu2: PowerPC,e500mc@2 {
	95	device_type = "cpu";
	96	reg = <2>;
	97	next-level-cache = <&L2_2>;
	98	L2_2: l2-cache {
	99	next-level-cache = <&cpc>;
	100	};
	101	};
	102	cpu3: PowerPC,e500mc@3 {
	103	device_type = "cpu";
	104	reg = <3>;
	105	next-level-cache = <&L2_3>;
	106	L2_3: l2-cache {
	107	next-level-cache = <&cpc>;
	108	};
	109	};
	110	cpu4: PowerPC,e500mc@4 {
	111	device_type = "cpu";
	112	reg = <4>;
	113	next-level-cache = <&L2_4>;
	114	L2_4: l2-cache {
	115	next-level-cache = <&cpc>;
	116	};
	117	};
	118	cpu5: PowerPC,e500mc@5 {
	119	device_type = "cpu";
	120	reg = <5>;
	121	next-level-cache = <&L2_5>;
	122	L2_5: l2-cache {
	123	next-level-cache = <&cpc>;
	124	};
	125	};
	126	cpu6: PowerPC,e500mc@6 {
	127	device_type = "cpu";
	128	reg = <6>;
	129	next-level-cache = <&L2_6>;
	130	L2_6: l2-cache {
	131	next-level-cache = <&cpc>;
	132	};
	133	};
	134	cpu7: PowerPC,e500mc@7 {
	135	device_type = "cpu";
	136	reg = <7>;
	137	next-level-cache = <&L2_7>;
	138	L2_7: l2-cache {
	139	next-level-cache = <&cpc>;
	140	};
	141	};
	142	};
	143	};