1 files changed, 113 insertions, 0 deletions

diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
index 34769a7eafea..2415e1f1d3fa 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
@@ -353,8 +353,121 @@
 
         clockgen: global-utilities@e1000 {
                 compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
+                ranges = <0x0 0xe1000 0x1000>;
                 reg = <0xe1000 0x1000>;
                 clock-frequency = <0>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                sysclk: sysclk {
+                        #clock-cells = <0>;
+                        compatible = "fsl,qoriq-sysclk-1.0";
+                        clock-output-names = "sysclk";
+                };
+
+                pll0: pll0@800 {
+                        #clock-cells = <1>;
+                        reg = <0x800 0x4>;
+                        compatible = "fsl,qoriq-core-pll-1.0";
+                        clocks = <&sysclk>;
+                        clock-output-names = "pll0", "pll0-div2";
+                };
+
+                pll1: pll1@820 {
+                        #clock-cells = <1>;
+                        reg = <0x820 0x4>;
+                        compatible = "fsl,qoriq-core-pll-1.0";
+                        clocks = <&sysclk>;
+                        clock-output-names = "pll1", "pll1-div2";
+                };
+
+                pll2: pll2@840 {
+                        #clock-cells = <1>;
+                        reg = <0x840 0x4>;
+                        compatible = "fsl,qoriq-core-pll-1.0";
+                        clocks = <&sysclk>;
+                        clock-output-names = "pll2", "pll2-div2";
+                };
+
+                pll3: pll3@860 {
+                        #clock-cells = <1>;
+                        reg = <0x860 0x4>;
+                        compatible = "fsl,qoriq-core-pll-1.0";
+                        clocks = <&sysclk>;
+                        clock-output-names = "pll3", "pll3-div2";
+                };
+
+                mux0: mux0@0 {
+                        #clock-cells = <0>;
+                        reg = <0x0 0x4>;
+                        compatible = "fsl,qoriq-core-mux-1.0";
+                        clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                        clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                        clock-output-names = "cmux0";
+                };
+
+                mux1: mux1@20 {
+                        #clock-cells = <0>;
+                        reg = <0x20 0x4>;
+                        compatible = "fsl,qoriq-core-mux-1.0";
+                        clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                        clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                        clock-output-names = "cmux1";
+                };
+
+                mux2: mux2@40 {
+                        #clock-cells = <0>;
+                        reg = <0x40 0x4>;
+                        compatible = "fsl,qoriq-core-mux-1.0";
+                        clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                        clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                        clock-output-names = "cmux2";
+                };
+
+                mux3: mux3@60 {
+                        #clock-cells = <0>;
+                        reg = <0x60 0x4>;
+                        compatible = "fsl,qoriq-core-mux-1.0";
+                        clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                        clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                        clock-output-names = "cmux3";
+                };
+
+                mux4: mux4@80 {
+                        #clock-cells = <0>;
+                        reg = <0x80 0x4>;
+                        compatible = "fsl,qoriq-core-mux-1.0";
+                        clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
+                        clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
+                        clock-output-names = "cmux4";
+                };
+
+                mux5: mux5@a0 {
+                        #clock-cells = <0>;
+                        reg = <0xa0 0x4>;
+                        compatible = "fsl,qoriq-core-mux-1.0";
+                        clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
+                        clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
+                        clock-output-names = "cmux5";
+                };
+
+                mux6: mux6@c0 {
+                        #clock-cells = <0>;
+                        reg = <0xc0 0x4>;
+                        compatible = "fsl,qoriq-core-mux-1.0";
+                        clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
+                        clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
+                        clock-output-names = "cmux6";
+                };
+
+                mux7: mux7@e0 {
+                        #clock-cells = <0>;
+                        reg = <0xe0 0x4>;
+                        compatible = "fsl,qoriq-core-mux-1.0";
+                        clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
+                        clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
+                        clock-output-names = "cmux7";
+                };
         };
 
         rcpm: global-utilities@e2000 {