1 files changed, 2 insertions, 46 deletions

diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
index 69ce1026c948..efd74db4f9b0 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
@@ -305,53 +305,9 @@
                 #sleep-cells = <2>;
         };
 
-        clockgen: global-utilities@e1000 {
+/include/ "qoriq-clockgen1.dtsi"
+        global-utilities@e1000 {
                 compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";
-                ranges = <0x0 0xe1000 0x1000>;
-                reg = <0xe1000 0x1000>;
-                clock-frequency = <0>;
-                #address-cells = <1>;
-                #size-cells = <1>;
-
-                sysclk: sysclk {
-                        #clock-cells = <0>;
-                        compatible = "fsl,qoriq-sysclk-1.0";
-                        clock-output-names = "sysclk";
-                };
-
-                pll0: pll0@800 {
-                        #clock-cells = <1>;
-                        reg = <0x800 0x4>;
-                        compatible = "fsl,qoriq-core-pll-1.0";
-                        clocks = <&sysclk>;
-                        clock-output-names = "pll0", "pll0-div2";
-                };
-
-                pll1: pll1@820 {
-                        #clock-cells = <1>;
-                        reg = <0x820 0x4>;
-                        compatible = "fsl,qoriq-core-pll-1.0";
-                        clocks = <&sysclk>;
-                        clock-output-names = "pll1", "pll1-div2";
-                };
-
-                mux0: mux0@0 {
-                        #clock-cells = <0>;
-                        reg = <0x0 0x4>;
-                        compatible = "fsl,qoriq-core-mux-1.0";
-                        clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
-                        clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
-                        clock-output-names = "cmux0";
-                };
-
-                mux1: mux1@20 {
-                        #clock-cells = <0>;
-                        reg = <0x20 0x4>;
-                        compatible = "fsl,qoriq-core-mux-1.0";
-                        clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
-                        clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
-                        clock-output-names = "cmux1";
-                };
 
                 mux2: mux2@40 {
                         #clock-cells = <0>;