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-rw-r--r--arch/powerpc/boot/dts/ep405.dts228
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diff --git a/arch/powerpc/boot/dts/ep405.dts b/arch/powerpc/boot/dts/ep405.dts
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index 000000000000..92938557ac8a
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1/*
2 * Device Tree Source for EP405
3 *
4 * Copyright 2007 IBM Corp.
5 * Benjamin Herrenschmidt <benh@kernel.crashing.org>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without
9 * any warranty of any kind, whether express or implied.
10 */
11
12/ {
13 #address-cells = <1>;
14 #size-cells = <1>;
15 model = "ep405";
16 compatible = "ep405";
17 dcr-parent = <&/cpus/cpu@0>;
18
19 aliases {
20 ethernet0 = &EMAC;
21 serial0 = &UART0;
22 serial1 = &UART1;
23 };
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 cpu@0 {
30 device_type = "cpu";
31 model = "PowerPC,405GP";
32 reg = <0>;
33 clock-frequency = <bebc200>; /* Filled in by zImage */
34 timebase-frequency = <0>; /* Filled in by zImage */
35 i-cache-line-size = <20>;
36 d-cache-line-size = <20>;
37 i-cache-size = <4000>;
38 d-cache-size = <4000>;
39 dcr-controller;
40 dcr-access-method = "native";
41 };
42 };
43
44 memory {
45 device_type = "memory";
46 reg = <0 0>; /* Filled in by zImage */
47 };
48
49 UIC0: interrupt-controller {
50 compatible = "ibm,uic";
51 interrupt-controller;
52 cell-index = <0>;
53 dcr-reg = <0c0 9>;
54 #address-cells = <0>;
55 #size-cells = <0>;
56 #interrupt-cells = <2>;
57 };
58
59 plb {
60 compatible = "ibm,plb3";
61 #address-cells = <1>;
62 #size-cells = <1>;
63 ranges;
64 clock-frequency = <0>; /* Filled in by zImage */
65
66 SDRAM0: memory-controller {
67 compatible = "ibm,sdram-405gp";
68 dcr-reg = <010 2>;
69 };
70
71 MAL: mcmal {
72 compatible = "ibm,mcmal-405gp", "ibm,mcmal";
73 dcr-reg = <180 62>;
74 num-tx-chans = <1>;
75 num-rx-chans = <1>;
76 interrupt-parent = <&UIC0>;
77 interrupts = <
78 b 4 /* TXEOB */
79 c 4 /* RXEOB */
80 a 4 /* SERR */
81 d 4 /* TXDE */
82 e 4 /* RXDE */>;
83 };
84
85 POB0: opb {
86 compatible = "ibm,opb-405gp", "ibm,opb";
87 #address-cells = <1>;
88 #size-cells = <1>;
89 ranges = <ef600000 ef600000 a00000>;
90 dcr-reg = <0a0 5>;
91 clock-frequency = <0>; /* Filled in by zImage */
92
93 UART0: serial@ef600300 {
94 device_type = "serial";
95 compatible = "ns16550";
96 reg = <ef600300 8>;
97 virtual-reg = <ef600300>;
98 clock-frequency = <0>; /* Filled in by zImage */
99 current-speed = <2580>;
100 interrupt-parent = <&UIC0>;
101 interrupts = <0 4>;
102 };
103
104 UART1: serial@ef600400 {
105 device_type = "serial";
106 compatible = "ns16550";
107 reg = <ef600400 8>;
108 virtual-reg = <ef600400>;
109 clock-frequency = <0>; /* Filled in by zImage */
110 current-speed = <2580>;
111 interrupt-parent = <&UIC0>;
112 interrupts = <1 4>;
113 };
114
115 IIC: i2c@ef600500 {
116 compatible = "ibm,iic-405gp", "ibm,iic";
117 reg = <ef600500 11>;
118 interrupt-parent = <&UIC0>;
119 interrupts = <2 4>;
120 };
121
122 GPIO: gpio@ef600700 {
123 compatible = "ibm,gpio-405gp";
124 reg = <ef600700 20>;
125 };
126
127 EMAC: ethernet@ef600800 {
128 linux,network-index = <0>;
129 device_type = "network";
130 compatible = "ibm,emac-405gp", "ibm,emac";
131 interrupt-parent = <&UIC0>;
132 interrupts = <
133 f 4 /* Ethernet */
134 9 4 /* Ethernet Wake Up */>;
135 local-mac-address = [000000000000]; /* Filled in by zImage */
136 reg = <ef600800 70>;
137 mal-device = <&MAL>;
138 mal-tx-channel = <0>;
139 mal-rx-channel = <0>;
140 cell-index = <0>;
141 max-frame-size = <5dc>;
142 rx-fifo-size = <1000>;
143 tx-fifo-size = <800>;
144 phy-mode = "rmii";
145 phy-map = <00000000>;
146 };
147
148 };
149
150 EBC0: ebc {
151 compatible = "ibm,ebc-405gp", "ibm,ebc";
152 dcr-reg = <012 2>;
153 #address-cells = <2>;
154 #size-cells = <1>;
155
156
157 /* The ranges property is supplied by the bootwrapper
158 * and is based on the firmware's configuration of the
159 * EBC bridge
160 */
161 clock-frequency = <0>; /* Filled in by zImage */
162
163 /* NVRAM and RTC */
164 nvrtc@4,200000 {
165 compatible = "ds1742";
166 reg = <4 200000 0>; /* size fixed up by zImage */
167 };
168
169 /* "BCSR" CPLD contains a PCI irq controller */
170 bcsr@4,0 {
171 compatible = "ep405-bcsr";
172 reg = <4 0 10>;
173 interrupt-controller;
174 /* Routing table */
175 irq-routing = [ 00 /* SYSERR */
176 01 /* STTM */
177 01 /* RTC */
178 01 /* FENET */
179 02 /* NB PCIIRQ mux ? */
180 03 /* SB Winbond 8259 ? */
181 04 /* Serial Ring */
182 05 /* USB (ep405pc) */
183 06 /* XIRQ 0 */
184 06 /* XIRQ 1 */
185 06 /* XIRQ 2 */
186 06 /* XIRQ 3 */
187 06 /* XIRQ 4 */
188 06 /* XIRQ 5 */
189 06 /* XIRQ 6 */
190 07]; /* Reserved */
191 };
192 };
193
194 PCI0: pci@ec000000 {
195 device_type = "pci";
196 #interrupt-cells = <1>;
197 #size-cells = <2>;
198 #address-cells = <3>;
199 compatible = "ibm,plb405gp-pci", "ibm,plb-pci";
200 primary;
201 reg = <eec00000 8 /* Config space access */
202 eed80000 4 /* IACK */
203 eed80000 4 /* Special cycle */
204 ef480000 40>; /* Internal registers */
205
206 /* Outbound ranges, one memory and one IO,
207 * later cannot be changed. Chip supports a second
208 * IO range but we don't use it for now
209 */
210 ranges = <02000000 0 80000000 80000000 0 20000000
211 01000000 0 00000000 e8000000 0 00010000>;
212
213 /* Inbound 2GB range starting at 0 */
214 dma-ranges = <42000000 0 0 0 0 80000000>;
215
216 /* That's all I know about IRQs on that thing ... */
217 interrupt-map-mask = <f800 0 0 0>;
218 interrupt-map = <
219 /* USB */
220 7000 0 0 0 &UIC0 1e 8 /* IRQ5 */
221 >;
222 };
223 };
224
225 chosen {
226 linux,stdout-path = "/plb/opb/serial@ef600300";
227 };
228};
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