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-rw-r--r--arch/powerpc/boot/dts/cm5200.dts234
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diff --git a/arch/powerpc/boot/dts/cm5200.dts b/arch/powerpc/boot/dts/cm5200.dts
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1/*
2 * CM5200 board Device Tree Source
3 *
4 * Copyright (C) 2007 Semihalf
5 * Marian Balakowicz <m8@semihalf.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13/*
14 * WARNING: Do not depend on this tree layout remaining static just yet.
15 * The MPC5200 device tree conventions are still in flux
16 * Keep an eye on the linuxppc-dev mailing list for more details
17 */
18
19/ {
20 model = "schindler,cm5200";
21 compatible = "schindler,cm5200";
22 #address-cells = <1>;
23 #size-cells = <1>;
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 PowerPC,5200@0 {
30 device_type = "cpu";
31 reg = <0>;
32 d-cache-line-size = <20>;
33 i-cache-line-size = <20>;
34 d-cache-size = <4000>; // L1, 16K
35 i-cache-size = <4000>; // L1, 16K
36 timebase-frequency = <0>; // from bootloader
37 bus-frequency = <0>; // from bootloader
38 clock-frequency = <0>; // from bootloader
39 };
40 };
41
42 memory {
43 device_type = "memory";
44 reg = <00000000 04000000>; // 64MB
45 };
46
47 soc5200@f0000000 {
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "fsl,mpc5200b-immr";
51 ranges = <0 f0000000 0000c000>;
52 reg = <f0000000 00000100>;
53 bus-frequency = <0>; // from bootloader
54 system-frequency = <0>; // from bootloader
55
56 cdm@200 {
57 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
58 reg = <200 38>;
59 };
60
61 mpc5200_pic: pic@500 {
62 // 5200 interrupts are encoded into two levels;
63 interrupt-controller;
64 #interrupt-cells = <3>;
65 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
66 reg = <500 80>;
67 };
68
69 timer@600 { // General Purpose Timer
70 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
71 reg = <600 10>;
72 interrupts = <1 9 0>;
73 interrupt-parent = <&mpc5200_pic>;
74 fsl,has-wdt;
75 };
76
77 timer@610 { // General Purpose Timer
78 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
79 reg = <610 10>;
80 interrupts = <1 a 0>;
81 interrupt-parent = <&mpc5200_pic>;
82 };
83
84 timer@620 { // General Purpose Timer
85 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
86 reg = <620 10>;
87 interrupts = <1 b 0>;
88 interrupt-parent = <&mpc5200_pic>;
89 };
90
91 timer@630 { // General Purpose Timer
92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
93 reg = <630 10>;
94 interrupts = <1 c 0>;
95 interrupt-parent = <&mpc5200_pic>;
96 };
97
98 timer@640 { // General Purpose Timer
99 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
100 reg = <640 10>;
101 interrupts = <1 d 0>;
102 interrupt-parent = <&mpc5200_pic>;
103 };
104
105 timer@650 { // General Purpose Timer
106 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
107 reg = <650 10>;
108 interrupts = <1 e 0>;
109 interrupt-parent = <&mpc5200_pic>;
110 };
111
112 timer@660 { // General Purpose Timer
113 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
114 reg = <660 10>;
115 interrupts = <1 f 0>;
116 interrupt-parent = <&mpc5200_pic>;
117 };
118
119 timer@670 { // General Purpose Timer
120 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
121 reg = <670 10>;
122 interrupts = <1 10 0>;
123 interrupt-parent = <&mpc5200_pic>;
124 };
125
126 rtc@800 { // Real time clock
127 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
128 reg = <800 100>;
129 interrupts = <1 5 0 1 6 0>;
130 interrupt-parent = <&mpc5200_pic>;
131 };
132
133 gpio@b00 {
134 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
135 reg = <b00 40>;
136 interrupts = <1 7 0>;
137 interrupt-parent = <&mpc5200_pic>;
138 };
139
140 gpio@c00 {
141 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
142 reg = <c00 40>;
143 interrupts = <1 8 0 0 3 0>;
144 interrupt-parent = <&mpc5200_pic>;
145 };
146
147 spi@f00 {
148 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
149 reg = <f00 20>;
150 interrupts = <2 d 0 2 e 0>;
151 interrupt-parent = <&mpc5200_pic>;
152 };
153
154 usb@1000 {
155 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
156 reg = <1000 ff>;
157 interrupts = <2 6 0>;
158 interrupt-parent = <&mpc5200_pic>;
159 };
160
161 dma-controller@1200 {
162 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
163 reg = <1200 80>;
164 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
165 3 4 0 3 5 0 3 6 0 3 7 0
166 3 8 0 3 9 0 3 a 0 3 b 0
167 3 c 0 3 d 0 3 e 0 3 f 0>;
168 interrupt-parent = <&mpc5200_pic>;
169 };
170
171 xlb@1f00 {
172 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
173 reg = <1f00 100>;
174 };
175
176 serial@2000 { // PSC1
177 device_type = "serial";
178 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
179 port-number = <0>; // Logical port assignment
180 reg = <2000 100>;
181 interrupts = <2 1 0>;
182 interrupt-parent = <&mpc5200_pic>;
183 };
184
185 serial@2200 { // PSC2
186 device_type = "serial";
187 compatible = "fsl,mpc5200-psc-uart";
188 port-number = <1>; // Logical port assignment
189 reg = <2200 100>;
190 interrupts = <2 2 0>;
191 interrupt-parent = <&mpc5200_pic>;
192 };
193
194 serial@2400 { // PSC3
195 device_type = "serial";
196 compatible = "fsl,mpc5200-psc-uart";
197 port-number = <2>; // Logical port assignment
198 reg = <2400 100>;
199 interrupts = <2 3 0>;
200 interrupt-parent = <&mpc5200_pic>;
201 };
202
203 serial@2c00 { // PSC6
204 device_type = "serial";
205 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
206 port-number = <5>; // Logical port assignment
207 reg = <2c00 100>;
208 interrupts = <2 4 0>;
209 interrupt-parent = <&mpc5200_pic>;
210 };
211
212 ethernet@3000 {
213 device_type = "network";
214 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
215 reg = <3000 800>;
216 local-mac-address = [ 00 00 00 00 00 00 ];
217 interrupts = <2 5 0>;
218 interrupt-parent = <&mpc5200_pic>;
219 };
220
221 i2c@3d40 {
222 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
223 reg = <3d40 40>;
224 interrupts = <2 10 0>;
225 interrupt-parent = <&mpc5200_pic>;
226 fsl5200-clocking;
227 };
228
229 sram@8000 {
230 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
231 reg = <8000 4000>;
232 };
233 };
234};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-22 10:53:26 -0500