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Diffstat (limited to 'arch/powerpc/boot/dts/cm5200.dts')
-rw-r--r--arch/powerpc/boot/dts/cm5200.dts60
1 files changed, 29 insertions, 31 deletions
diff --git a/arch/powerpc/boot/dts/cm5200.dts b/arch/powerpc/boot/dts/cm5200.dts
index 9295083d1ce9..30737eafe68e 100644
--- a/arch/powerpc/boot/dts/cm5200.dts
+++ b/arch/powerpc/boot/dts/cm5200.dts
@@ -45,17 +45,16 @@
45 }; 45 };
46 46
47 soc5200@f0000000 { 47 soc5200@f0000000 {
48 model = "fsl,mpc5200b"; 48 #address-cells = <1>;
49 compatible = "fsl,mpc5200b"; 49 #size-cells = <1>;
50 revision = ""; // from bootloader 50 compatible = "fsl,mpc5200b-immr";
51 device_type = "soc";
52 ranges = <0 f0000000 0000c000>; 51 ranges = <0 f0000000 0000c000>;
53 reg = <f0000000 00000100>; 52 reg = <f0000000 00000100>;
54 bus-frequency = <0>; // from bootloader 53 bus-frequency = <0>; // from bootloader
55 system-frequency = <0>; // from bootloader 54 system-frequency = <0>; // from bootloader
56 55
57 cdm@200 { 56 cdm@200 {
58 compatible = "mpc5200b-cdm","mpc5200-cdm"; 57 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
59 reg = <200 38>; 58 reg = <200 38>;
60 }; 59 };
61 60
@@ -63,11 +62,11 @@
63 // 5200 interrupts are encoded into two levels; 62 // 5200 interrupts are encoded into two levels;
64 interrupt-controller; 63 interrupt-controller;
65 #interrupt-cells = <3>; 64 #interrupt-cells = <3>;
66 compatible = "mpc5200b-pic","mpc5200-pic"; 65 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
67 reg = <500 80>; 66 reg = <500 80>;
68 }; 67 };
69 68
70 gpt@600 { // General Purpose Timer 69 timer@600 { // General Purpose Timer
71 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 70 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
72 reg = <600 10>; 71 reg = <600 10>;
73 interrupts = <1 9 0>; 72 interrupts = <1 9 0>;
@@ -75,49 +74,49 @@
75 fsl,has-wdt; 74 fsl,has-wdt;
76 }; 75 };
77 76
78 gpt@610 { // General Purpose Timer 77 timer@610 { // General Purpose Timer
79 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 78 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
80 reg = <610 10>; 79 reg = <610 10>;
81 interrupts = <1 a 0>; 80 interrupts = <1 a 0>;
82 interrupt-parent = <&mpc5200_pic>; 81 interrupt-parent = <&mpc5200_pic>;
83 }; 82 };
84 83
85 gpt@620 { // General Purpose Timer 84 timer@620 { // General Purpose Timer
86 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 85 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
87 reg = <620 10>; 86 reg = <620 10>;
88 interrupts = <1 b 0>; 87 interrupts = <1 b 0>;
89 interrupt-parent = <&mpc5200_pic>; 88 interrupt-parent = <&mpc5200_pic>;
90 }; 89 };
91 90
92 gpt@630 { // General Purpose Timer 91 timer@630 { // General Purpose Timer
93 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
94 reg = <630 10>; 93 reg = <630 10>;
95 interrupts = <1 c 0>; 94 interrupts = <1 c 0>;
96 interrupt-parent = <&mpc5200_pic>; 95 interrupt-parent = <&mpc5200_pic>;
97 }; 96 };
98 97
99 gpt@640 { // General Purpose Timer 98 timer@640 { // General Purpose Timer
100 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 99 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
101 reg = <640 10>; 100 reg = <640 10>;
102 interrupts = <1 d 0>; 101 interrupts = <1 d 0>;
103 interrupt-parent = <&mpc5200_pic>; 102 interrupt-parent = <&mpc5200_pic>;
104 }; 103 };
105 104
106 gpt@650 { // General Purpose Timer 105 timer@650 { // General Purpose Timer
107 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 106 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
108 reg = <650 10>; 107 reg = <650 10>;
109 interrupts = <1 e 0>; 108 interrupts = <1 e 0>;
110 interrupt-parent = <&mpc5200_pic>; 109 interrupt-parent = <&mpc5200_pic>;
111 }; 110 };
112 111
113 gpt@660 { // General Purpose Timer 112 timer@660 { // General Purpose Timer
114 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 113 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
115 reg = <660 10>; 114 reg = <660 10>;
116 interrupts = <1 f 0>; 115 interrupts = <1 f 0>;
117 interrupt-parent = <&mpc5200_pic>; 116 interrupt-parent = <&mpc5200_pic>;
118 }; 117 };
119 118
120 gpt@670 { // General Purpose Timer 119 timer@670 { // General Purpose Timer
121 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 120 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
122 reg = <670 10>; 121 reg = <670 10>;
123 interrupts = <1 10 0>; 122 interrupts = <1 10 0>;
@@ -125,43 +124,42 @@
125 }; 124 };
126 125
127 rtc@800 { // Real time clock 126 rtc@800 { // Real time clock
128 compatible = "mpc5200b-rtc","mpc5200-rtc"; 127 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
129 reg = <800 100>; 128 reg = <800 100>;
130 interrupts = <1 5 0 1 6 0>; 129 interrupts = <1 5 0 1 6 0>;
131 interrupt-parent = <&mpc5200_pic>; 130 interrupt-parent = <&mpc5200_pic>;
132 }; 131 };
133 132
134 gpio@b00 { 133 gpio@b00 {
135 compatible = "mpc5200b-gpio","mpc5200-gpio"; 134 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
136 reg = <b00 40>; 135 reg = <b00 40>;
137 interrupts = <1 7 0>; 136 interrupts = <1 7 0>;
138 interrupt-parent = <&mpc5200_pic>; 137 interrupt-parent = <&mpc5200_pic>;
139 }; 138 };
140 139
141 gpio-wkup@c00 { 140 gpio@c00 {
142 compatible = "mpc5200b-gpio-wkup","mpc5200-gpio-wkup"; 141 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
143 reg = <c00 40>; 142 reg = <c00 40>;
144 interrupts = <1 8 0 0 3 0>; 143 interrupts = <1 8 0 0 3 0>;
145 interrupt-parent = <&mpc5200_pic>; 144 interrupt-parent = <&mpc5200_pic>;
146 }; 145 };
147 146
148 spi@f00 { 147 spi@f00 {
149 compatible = "mpc5200b-spi","mpc5200-spi"; 148 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
150 reg = <f00 20>; 149 reg = <f00 20>;
151 interrupts = <2 d 0 2 e 0>; 150 interrupts = <2 d 0 2 e 0>;
152 interrupt-parent = <&mpc5200_pic>; 151 interrupt-parent = <&mpc5200_pic>;
153 }; 152 };
154 153
155 usb@1000 { 154 usb@1000 {
156 device_type = "usb-ohci-be"; 155 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
157 compatible = "mpc5200b-ohci","mpc5200-ohci","ohci-be";
158 reg = <1000 ff>; 156 reg = <1000 ff>;
159 interrupts = <2 6 0>; 157 interrupts = <2 6 0>;
160 interrupt-parent = <&mpc5200_pic>; 158 interrupt-parent = <&mpc5200_pic>;
161 }; 159 };
162 160
163 dma-controller@1200 { 161 dma-controller@1200 {
164 compatible = "mpc5200b-bestcomm","mpc5200-bestcomm"; 162 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
165 reg = <1200 80>; 163 reg = <1200 80>;
166 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 164 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
167 3 4 0 3 5 0 3 6 0 3 7 0 165 3 4 0 3 5 0 3 6 0 3 7 0
@@ -171,13 +169,13 @@
171 }; 169 };
172 170
173 xlb@1f00 { 171 xlb@1f00 {
174 compatible = "mpc5200b-xlb","mpc5200-xlb"; 172 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
175 reg = <1f00 100>; 173 reg = <1f00 100>;
176 }; 174 };
177 175
178 serial@2000 { // PSC1 176 serial@2000 { // PSC1
179 device_type = "serial"; 177 device_type = "serial";
180 compatible = "mpc5200b-psc-uart","mpc5200-psc-uart"; 178 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
181 port-number = <0>; // Logical port assignment 179 port-number = <0>; // Logical port assignment
182 reg = <2000 100>; 180 reg = <2000 100>;
183 interrupts = <2 1 0>; 181 interrupts = <2 1 0>;
@@ -186,7 +184,7 @@
186 184
187 serial@2200 { // PSC2 185 serial@2200 { // PSC2
188 device_type = "serial"; 186 device_type = "serial";
189 compatible = "mpc5200-psc-uart"; 187 compatible = "fsl,mpc5200-psc-uart";
190 port-number = <1>; // Logical port assignment 188 port-number = <1>; // Logical port assignment
191 reg = <2200 100>; 189 reg = <2200 100>;
192 interrupts = <2 2 0>; 190 interrupts = <2 2 0>;
@@ -195,7 +193,7 @@
195 193
196 serial@2400 { // PSC3 194 serial@2400 { // PSC3
197 device_type = "serial"; 195 device_type = "serial";
198 compatible = "mpc5200-psc-uart"; 196 compatible = "fsl,mpc5200-psc-uart";
199 port-number = <2>; // Logical port assignment 197 port-number = <2>; // Logical port assignment
200 reg = <2400 100>; 198 reg = <2400 100>;
201 interrupts = <2 3 0>; 199 interrupts = <2 3 0>;
@@ -204,7 +202,7 @@
204 202
205 serial@2c00 { // PSC6 203 serial@2c00 { // PSC6
206 device_type = "serial"; 204 device_type = "serial";
207 compatible = "mpc5200b-psc-uart","mpc5200-psc-uart"; 205 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
208 port-number = <5>; // Logical port assignment 206 port-number = <5>; // Logical port assignment
209 reg = <2c00 100>; 207 reg = <2c00 100>;
210 interrupts = <2 4 0>; 208 interrupts = <2 4 0>;
@@ -213,15 +211,15 @@
213 211
214 ethernet@3000 { 212 ethernet@3000 {
215 device_type = "network"; 213 device_type = "network";
216 compatible = "mpc5200b-fec","mpc5200-fec"; 214 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
217 reg = <3000 800>; 215 reg = <3000 800>;
218 local-mac-address = [ 00 00 00 00 00 00 ]; /* Filled in by U-Boot */ 216 local-mac-address = [ 00 00 00 00 00 00 ];
219 interrupts = <2 5 0>; 217 interrupts = <2 5 0>;
220 interrupt-parent = <&mpc5200_pic>; 218 interrupt-parent = <&mpc5200_pic>;
221 }; 219 };
222 220
223 i2c@3d40 { 221 i2c@3d40 {
224 compatible = "mpc5200b-i2c","mpc5200-i2c","fsl-i2c"; 222 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
225 reg = <3d40 40>; 223 reg = <3d40 40>;
226 interrupts = <2 10 0>; 224 interrupts = <2 10 0>;
227 interrupt-parent = <&mpc5200_pic>; 225 interrupt-parent = <&mpc5200_pic>;
@@ -229,7 +227,7 @@
229 }; 227 };
230 228
231 sram@8000 { 229 sram@8000 {
232 compatible = "mpc5200b-sram","mpc5200-sram"; 230 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
233 reg = <8000 4000>; 231 reg = <8000 4000>;
234 }; 232 };
235 }; 233 };
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 07:03:02 -0500