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-rw-r--r--arch/parisc/kernel/irq.c13
1 files changed, 6 insertions, 7 deletions
diff --git a/arch/parisc/kernel/irq.c b/arch/parisc/kernel/irq.c
index f7ae2bcd49a5..21a9c5ad580b 100644
--- a/arch/parisc/kernel/irq.c
+++ b/arch/parisc/kernel/irq.c
@@ -250,10 +250,11 @@ void do_cpu_irq_mask(struct pt_regs *regs)
250 irq_enter(); 250 irq_enter();
251 251
252 /* 252 /*
253 * Only allow interrupt processing to be interrupted by the 253 * Don't allow TIMER or IPI nested interrupts.
254 * timer tick 254 * Allowing any single interrupt to nest can lead to that CPU
255 * handling interrupts with all enabled interrupts unmasked.
255 */ 256 */
256 set_eiem(EIEM_MASK(TIMER_IRQ)); 257 set_eiem(0UL);
257 258
258 /* 1) only process IRQs that are enabled/unmasked (cpu_eiem) 259 /* 1) only process IRQs that are enabled/unmasked (cpu_eiem)
259 * 2) We loop here on EIRR contents in order to avoid 260 * 2) We loop here on EIRR contents in order to avoid
@@ -267,9 +268,6 @@ void do_cpu_irq_mask(struct pt_regs *regs)
267 if (!eirr_val) 268 if (!eirr_val)
268 break; 269 break;
269 270
270 if (eirr_val & EIEM_MASK(TIMER_IRQ))
271 set_eiem(0);
272
273 mtctl(eirr_val, 23); /* reset bits we are going to process */ 271 mtctl(eirr_val, 23); /* reset bits we are going to process */
274 272
275 /* Work our way from MSb to LSb...same order we alloc EIRs */ 273 /* Work our way from MSb to LSb...same order we alloc EIRs */
@@ -283,7 +281,8 @@ void do_cpu_irq_mask(struct pt_regs *regs)
283 __do_IRQ(irq, regs); 281 __do_IRQ(irq, regs);
284 } 282 }
285 } 283 }
286 set_eiem(cpu_eiem); 284
285 set_eiem(cpu_eiem); /* restore original mask */
287 irq_exit(); 286 irq_exit();
288} 287}
289 288