1 files changed, 148 insertions, 0 deletions
diff --git a/arch/parisc/lib/milli/remU.S b/arch/parisc/lib/milli/remU.S
new file mode 100644
index 000000000000..c0a2d6e247c3
--- /dev/null
+++ b/arch/parisc/lib/milli/remU.S
@@ -0,0 +1,148 @@
+/* 32 and 64-bit millicode, original author Hewlett-Packard
+   adapted for gcc by Paul Bame <bame@debian.org>
+   and Alan Modra <alan@linuxcare.com.au>.
+   Copyright 2001, 2002, 2003 Free Software Foundation, Inc.
+   This file is part of GCC and is released under the terms of
+   of the GNU General Public License as published by the Free Software
+   Foundation; either version 2, or (at your option) any later version.
+   See the file COPYING in the top-level GCC source directory for a copy
+   of the license.  */
+#include "milli.h"
+#ifdef L_remU
+/* ROUTINE:     $$remU
+   .    Single precision divide for remainder with unsigned binary integers.
+   .
+   .    The remainder must be dividend-(dividend/divisor)*divisor.
+   .    Divide by zero is trapped.
+   INPUT REGISTERS:
+   .    arg0 == dividend
+   .    arg1 == divisor
+   .    mrp  == return pc
+   .    sr0  == return space when called externally
+   OUTPUT REGISTERS:
+   .    arg0 =  undefined
+   .    arg1 =  undefined
+   .    ret1 =  remainder
+   OTHER REGISTERS AFFECTED:
+   .    r1   =  undefined
+   SIDE EFFECTS:
+   .    Causes a trap under the following conditions:  DIVIDE BY ZERO
+   .    Changes memory at the following places:  NONE
+   PERMISSIBLE CONTEXT:
+   .    Unwindable.
+   .    Does not create a stack frame.
+   .    Suitable for internal or external millicode.
+   .    Assumes the special millicode register conventions.
+   DISCUSSION:
+   .    Calls other millicode routines using mrp: NONE
+   .    Calls other millicode routines: NONE  */
+RDEFINE(temp,r1)
+RDEFINE(rmndr,ret1)     /*  r29 */
+        SUBSPA_MILLI
+        ATTR_MILLI
+        .export $$remU,millicode
+        .proc
+        .callinfo       millicode
+        .entry
+GSYM($$remU)
+        ldo     -1(arg1),temp           /*  is there at most one bit set ? */
+        and,=   arg1,temp,r0            /*  if not, don't use power of 2 */
+        b       LREF(regular_seq)
+        addit,= 0,arg1,r0               /*  trap on div by zero */
+        and     arg0,temp,rmndr         /*  get the result for power of 2 */
+        MILLIRETN
+LSYM(regular_seq)
+        comib,>=,n  0,arg1,LREF(special_case)
+        subi    0,arg1,rmndr            /*  clear carry, negate the divisor */
+        ds      r0,rmndr,r0             /*  set V-bit to 1 */
+        add     arg0,arg0,temp          /*  shift msb bit into carry */
+        ds      r0,arg1,rmndr           /*  1st divide step, if no carry */
+        addc    temp,temp,temp          /*  shift temp with/into carry */
+        ds      rmndr,arg1,rmndr                /*  2nd divide step */
+        addc    temp,temp,temp          /*  shift temp with/into carry */
+        ds      rmndr,arg1,rmndr                /*  3rd divide step */
+        addc    temp,temp,temp          /*  shift temp with/into carry */
+        ds      rmndr,arg1,rmndr                /*  4th divide step */
+        addc    temp,temp,temp          /*  shift temp with/into carry */
+        ds      rmndr,arg1,rmndr                /*  5th divide step */
+        addc    temp,temp,temp          /*  shift temp with/into carry */
+        ds      rmndr,arg1,rmndr                /*  6th divide step */
+        addc    temp,temp,temp          /*  shift temp with/into carry */
+        ds      rmndr,arg1,rmndr                /*  7th divide step */
+        addc    temp,temp,temp          /*  shift temp with/into carry */
+        ds      rmndr,arg1,rmndr                /*  8th divide step */
+        addc    temp,temp,temp          /*  shift temp with/into carry */
+        ds      rmndr,arg1,rmndr                /*  9th divide step */
+        addc    temp,temp,temp          /*  shift temp with/into carry */
+        ds      rmndr,arg1,rmndr                /*  10th divide step */
+        addc    temp,temp,temp          /*  shift temp with/into carry */
+        ds      rmndr,arg1,rmndr                /*  11th divide step */
+        addc    temp,temp,temp          /*  shift temp with/into carry */
+        ds      rmndr,arg1,rmndr                /*  12th divide step */
+        addc    temp,temp,temp          /*  shift temp with/into carry */
+        ds      rmndr,arg1,rmndr                /*  13th divide step */
+        addc    temp,temp,temp          /*  shift temp with/into carry */
+        ds      rmndr,arg1,rmndr                /*  14th divide step */
+        addc    temp,temp,temp          /*  shift temp with/into carry */
+        ds      rmndr,arg1,rmndr                /*  15th divide step */
+        addc    temp,temp,temp          /*  shift temp with/into carry */
+        ds      rmndr,arg1,rmndr                /*  16th divide step */
+        addc    temp,temp,temp          /*  shift temp with/into carry */
+        ds      rmndr,arg1,rmndr                /*  17th divide step */
+        addc    temp,temp,temp          /*  shift temp with/into carry */
+        ds      rmndr,arg1,rmndr                /*  18th divide step */
+        addc    temp,temp,temp          /*  shift temp with/into carry */
+        ds      rmndr,arg1,rmndr                /*  19th divide step */
+        addc    temp,temp,temp          /*  shift temp with/into carry */
+        ds      rmndr,arg1,rmndr                /*  20th divide step */
+        addc    temp,temp,temp          /*  shift temp with/into carry */
+        ds      rmndr,arg1,rmndr                /*  21st divide step */
+        addc    temp,temp,temp          /*  shift temp with/into carry */
+        ds      rmndr,arg1,rmndr                /*  22nd divide step */
+        addc    temp,temp,temp          /*  shift temp with/into carry */
+        ds      rmndr,arg1,rmndr                /*  23rd divide step */
+        addc    temp,temp,temp          /*  shift temp with/into carry */
+        ds      rmndr,arg1,rmndr                /*  24th divide step */
+        addc    temp,temp,temp          /*  shift temp with/into carry */
+        ds      rmndr,arg1,rmndr                /*  25th divide step */
+        addc    temp,temp,temp          /*  shift temp with/into carry */
+        ds      rmndr,arg1,rmndr                /*  26th divide step */
+        addc    temp,temp,temp          /*  shift temp with/into carry */
+        ds      rmndr,arg1,rmndr                /*  27th divide step */
+        addc    temp,temp,temp          /*  shift temp with/into carry */
+        ds      rmndr,arg1,rmndr                /*  28th divide step */
+        addc    temp,temp,temp          /*  shift temp with/into carry */
+        ds      rmndr,arg1,rmndr                /*  29th divide step */
+        addc    temp,temp,temp          /*  shift temp with/into carry */
+        ds      rmndr,arg1,rmndr                /*  30th divide step */
+        addc    temp,temp,temp          /*  shift temp with/into carry */
+        ds      rmndr,arg1,rmndr                /*  31st divide step */
+        addc    temp,temp,temp          /*  shift temp with/into carry */
+        ds      rmndr,arg1,rmndr                /*  32nd divide step, */
+        comiclr,<= 0,rmndr,r0
+          add   rmndr,arg1,rmndr        /*  correction */
+        MILLIRETN
+        nop
+/* Putting >= on the last DS and deleting COMICLR does not work!  */
+LSYM(special_case)
+        sub,>>= arg0,arg1,rmndr
+          copy  arg0,rmndr
+        MILLIRETN
+        nop
+        .exit
+        .procend
+        .end
+#endif

diff --git a/arch/parisc/lib/milli/remU.S b/arch/parisc/lib/milli/remU.S new file mode 100644 index 000000000000..c0a2d6e247c3 --- /dev/null +++ b/arch/parisc/lib/milli/remU.S
@@ -0,0 +1,148 @@
	1	/* 32 and 64-bit millicode, original author Hewlett-Packard
	2	adapted for gcc by Paul Bame <bame@debian.org>
	3	and Alan Modra <alan@linuxcare.com.au>.
	4
	5	Copyright 2001, 2002, 2003 Free Software Foundation, Inc.
	6
	7	This file is part of GCC and is released under the terms of
	8	of the GNU General Public License as published by the Free Software
	9	Foundation; either version 2, or (at your option) any later version.
	10	See the file COPYING in the top-level GCC source directory for a copy
	11	of the license. */
	12
	13	#include "milli.h"
	14
	15	#ifdef L_remU
	16	/* ROUTINE: $$remU
	17	. Single precision divide for remainder with unsigned binary integers.
	18	.
	19	. The remainder must be dividend-(dividend/divisor)*divisor.
	20	. Divide by zero is trapped.
	21
	22	INPUT REGISTERS:
	23	. arg0 == dividend
	24	. arg1 == divisor
	25	. mrp == return pc
	26	. sr0 == return space when called externally
	27
	28	OUTPUT REGISTERS:
	29	. arg0 = undefined
	30	. arg1 = undefined
	31	. ret1 = remainder
	32
	33	OTHER REGISTERS AFFECTED:
	34	. r1 = undefined
	35
	36	SIDE EFFECTS:
	37	. Causes a trap under the following conditions: DIVIDE BY ZERO
	38	. Changes memory at the following places: NONE
	39
	40	PERMISSIBLE CONTEXT:
	41	. Unwindable.
	42	. Does not create a stack frame.
	43	. Suitable for internal or external millicode.
	44	. Assumes the special millicode register conventions.
	45
	46	DISCUSSION:
	47	. Calls other millicode routines using mrp: NONE
	48	. Calls other millicode routines: NONE */
	49
	50
	51	RDEFINE(temp,r1)
	52	RDEFINE(rmndr,ret1) /* r29 */
	53	SUBSPA_MILLI
	54	ATTR_MILLI
	55	.export $$remU,millicode
	56	.proc
	57	.callinfo millicode
	58	.entry
	59	GSYM($$remU)
	60	ldo -1(arg1),temp /* is there at most one bit set ? */
	61	and,= arg1,temp,r0 /* if not, don't use power of 2 */
	62	b LREF(regular_seq)
	63	addit,= 0,arg1,r0 /* trap on div by zero */
	64	and arg0,temp,rmndr /* get the result for power of 2 */
	65	MILLIRETN
	66	LSYM(regular_seq)
	67	comib,>=,n 0,arg1,LREF(special_case)
	68	subi 0,arg1,rmndr /* clear carry, negate the divisor */
	69	ds r0,rmndr,r0 /* set V-bit to 1 */
	70	add arg0,arg0,temp /* shift msb bit into carry */
	71	ds r0,arg1,rmndr /* 1st divide step, if no carry */
	72	addc temp,temp,temp /* shift temp with/into carry */
	73	ds rmndr,arg1,rmndr /* 2nd divide step */
	74	addc temp,temp,temp /* shift temp with/into carry */
	75	ds rmndr,arg1,rmndr /* 3rd divide step */
	76	addc temp,temp,temp /* shift temp with/into carry */
	77	ds rmndr,arg1,rmndr /* 4th divide step */
	78	addc temp,temp,temp /* shift temp with/into carry */
	79	ds rmndr,arg1,rmndr /* 5th divide step */
	80	addc temp,temp,temp /* shift temp with/into carry */
	81	ds rmndr,arg1,rmndr /* 6th divide step */
	82	addc temp,temp,temp /* shift temp with/into carry */
	83	ds rmndr,arg1,rmndr /* 7th divide step */
	84	addc temp,temp,temp /* shift temp with/into carry */
	85	ds rmndr,arg1,rmndr /* 8th divide step */
	86	addc temp,temp,temp /* shift temp with/into carry */
	87	ds rmndr,arg1,rmndr /* 9th divide step */
	88	addc temp,temp,temp /* shift temp with/into carry */
	89	ds rmndr,arg1,rmndr /* 10th divide step */
	90	addc temp,temp,temp /* shift temp with/into carry */
	91	ds rmndr,arg1,rmndr /* 11th divide step */
	92	addc temp,temp,temp /* shift temp with/into carry */
	93	ds rmndr,arg1,rmndr /* 12th divide step */
	94	addc temp,temp,temp /* shift temp with/into carry */
	95	ds rmndr,arg1,rmndr /* 13th divide step */
	96	addc temp,temp,temp /* shift temp with/into carry */
	97	ds rmndr,arg1,rmndr /* 14th divide step */
	98	addc temp,temp,temp /* shift temp with/into carry */
	99	ds rmndr,arg1,rmndr /* 15th divide step */
	100	addc temp,temp,temp /* shift temp with/into carry */
	101	ds rmndr,arg1,rmndr /* 16th divide step */
	102	addc temp,temp,temp /* shift temp with/into carry */
	103	ds rmndr,arg1,rmndr /* 17th divide step */
	104	addc temp,temp,temp /* shift temp with/into carry */
	105	ds rmndr,arg1,rmndr /* 18th divide step */
	106	addc temp,temp,temp /* shift temp with/into carry */
	107	ds rmndr,arg1,rmndr /* 19th divide step */
	108	addc temp,temp,temp /* shift temp with/into carry */
	109	ds rmndr,arg1,rmndr /* 20th divide step */
	110	addc temp,temp,temp /* shift temp with/into carry */
	111	ds rmndr,arg1,rmndr /* 21st divide step */
	112	addc temp,temp,temp /* shift temp with/into carry */
	113	ds rmndr,arg1,rmndr /* 22nd divide step */
	114	addc temp,temp,temp /* shift temp with/into carry */
	115	ds rmndr,arg1,rmndr /* 23rd divide step */
	116	addc temp,temp,temp /* shift temp with/into carry */
	117	ds rmndr,arg1,rmndr /* 24th divide step */
	118	addc temp,temp,temp /* shift temp with/into carry */
	119	ds rmndr,arg1,rmndr /* 25th divide step */
	120	addc temp,temp,temp /* shift temp with/into carry */
	121	ds rmndr,arg1,rmndr /* 26th divide step */
	122	addc temp,temp,temp /* shift temp with/into carry */
	123	ds rmndr,arg1,rmndr /* 27th divide step */
	124	addc temp,temp,temp /* shift temp with/into carry */
	125	ds rmndr,arg1,rmndr /* 28th divide step */
	126	addc temp,temp,temp /* shift temp with/into carry */
	127	ds rmndr,arg1,rmndr /* 29th divide step */
	128	addc temp,temp,temp /* shift temp with/into carry */
	129	ds rmndr,arg1,rmndr /* 30th divide step */
	130	addc temp,temp,temp /* shift temp with/into carry */
	131	ds rmndr,arg1,rmndr /* 31st divide step */
	132	addc temp,temp,temp /* shift temp with/into carry */
	133	ds rmndr,arg1,rmndr /* 32nd divide step, */
	134	comiclr,<= 0,rmndr,r0
	135	add rmndr,arg1,rmndr /* correction */
	136	MILLIRETN
	137	nop
	138
	139	/* Putting >= on the last DS and deleting COMICLR does not work! */
	140	LSYM(special_case)
	141	sub,>>= arg0,arg1,rmndr
	142	copy arg0,rmndr
	143	MILLIRETN
	144	nop
	145	.exit
	146	.procend
	147	.end
	148	#endif