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-rw-r--r--arch/parisc/kernel/pci.c7
-rw-r--r--arch/parisc/kernel/signal.c4
2 files changed, 8 insertions, 3 deletions
diff --git a/arch/parisc/kernel/pci.c b/arch/parisc/kernel/pci.c
index f7064abc3bb6..9e74bfe071dc 100644
--- a/arch/parisc/kernel/pci.c
+++ b/arch/parisc/kernel/pci.c
@@ -18,7 +18,6 @@
18 18
19#include <asm/io.h> 19#include <asm/io.h>
20#include <asm/system.h> 20#include <asm/system.h>
21#include <asm/cache.h> /* for L1_CACHE_BYTES */
22#include <asm/superio.h> 21#include <asm/superio.h>
23 22
24#define DEBUG_RESOURCES 0 23#define DEBUG_RESOURCES 0
@@ -123,6 +122,10 @@ static int __init pcibios_init(void)
123 } else { 122 } else {
124 printk(KERN_WARNING "pci_bios != NULL but init() is!\n"); 123 printk(KERN_WARNING "pci_bios != NULL but init() is!\n");
125 } 124 }
125
126 /* Set the CLS for PCI as early as possible. */
127 pci_cache_line_size = pci_dfl_cache_line_size;
128
126 return 0; 129 return 0;
127} 130}
128 131
@@ -171,7 +174,7 @@ void pcibios_set_master(struct pci_dev *dev)
171 ** upper byte is PCI_LATENCY_TIMER. 174 ** upper byte is PCI_LATENCY_TIMER.
172 */ 175 */
173 pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, 176 pci_write_config_word(dev, PCI_CACHE_LINE_SIZE,
174 (0x80 << 8) | (L1_CACHE_BYTES / sizeof(u32))); 177 (0x80 << 8) | pci_cache_line_size);
175} 178}
176 179
177 180
diff --git a/arch/parisc/kernel/signal.c b/arch/parisc/kernel/signal.c
index fb37ac52e46c..35c827e94e31 100644
--- a/arch/parisc/kernel/signal.c
+++ b/arch/parisc/kernel/signal.c
@@ -468,7 +468,9 @@ handle_signal(unsigned long sig, siginfo_t *info, struct k_sigaction *ka,
468 recalc_sigpending(); 468 recalc_sigpending();
469 spin_unlock_irq(&current->sighand->siglock); 469 spin_unlock_irq(&current->sighand->siglock);
470 470
471 tracehook_signal_handler(sig, info, ka, regs, 0); 471 tracehook_signal_handler(sig, info, ka, regs,
472 test_thread_flag(TIF_SINGLESTEP) ||
473 test_thread_flag(TIF_BLOCKSTEP));
472 474
473 return 1; 475 return 1;
474} 476}