1 files changed, 53 insertions, 52 deletions
diff --git a/arch/parisc/kernel/pacache.S b/arch/parisc/kernel/pacache.S
index 77e03bc0f935..71ade44c4618 100644
--- a/arch/parisc/kernel/pacache.S
+++ b/arch/parisc/kernel/pacache.S
@@ -40,8 +40,8 @@
        .level  2.0
 #endif
-#include <asm/assembly.h>
 #include <asm/psw.h>
+#include <asm/assembly.h>
 #include <asm/pgtable.h>
 #include <asm/cache.h>
@@ -62,32 +62,23 @@ flush_tlb_all_local:
         * to happen in real mode with all interruptions disabled.
         */
-        /*
+        /* pcxt_ssm_bug - relied upon translation! PA 2.0 Arch. F-4 and F-5 */
-         * Once again, we do the rfi dance ... some day we need examine
+        rsm     PSW_SM_I, %r19          /* save I-bit state */
-         * all of our uses of this type of code and see what can be
+        load32          PA(1f), %r1
-         * consolidated.
-         */
-        rsm             PSW_SM_I, %r19          /* relied upon translation! PA 2.0 Arch. F-5 */
        nop
        nop
        nop
        nop
        nop
-        nop
-        nop
+        rsm             PSW_SM_Q, %r0           /* prep to load iia queue */
-        
-        rsm             PSW_SM_Q, %r0           /* Turn off Q bit to load iia queue */
-        ldil            L%REAL_MODE_PSW, %r1
-        ldo             R%REAL_MODE_PSW(%r1), %r1
-        mtctl           %r1, %cr22
        mtctl           %r0, %cr17              /* Clear IIASQ tail */
        mtctl           %r0, %cr17              /* Clear IIASQ head */
-        ldil            L%PA(1f), %r1
-        ldo             R%PA(1f)(%r1), %r1
        mtctl           %r1, %cr18              /* IIAOQ head */
        ldo             4(%r1), %r1
        mtctl           %r1, %cr18              /* IIAOQ tail */
+        load32          REAL_MODE_PSW, %r1
+        mtctl           %r1, %ipsw
        rfi
        nop
@@ -178,29 +169,36 @@ fdtonemiddle:					/* Loop if LOOP = 1 */
        ADDIB>          -1, %r22, fdtoneloop    /* Outer loop count decr */
        add             %r21, %r20, %r20        /* increment space */
-fdtdone:
-        /* Switch back to virtual mode */
+fdtdone:
+        /*
+         * Switch back to virtual mode
+         */
+        /* pcxt_ssm_bug */
+        rsm             PSW_SM_I, %r0
+        load32          2f, %r1
+        nop
+        nop
+        nop
+        nop
+        nop
-        rsm             PSW_SM_Q, %r0           /* clear Q bit to load iia queue */
+        rsm             PSW_SM_Q, %r0           /* prep to load iia queue */
-        ldil            L%KERNEL_PSW, %r1
-        ldo             R%KERNEL_PSW(%r1), %r1
-        or              %r1, %r19, %r1          /* Set I bit if set on entry */
-        mtctl           %r1, %cr22
        mtctl           %r0, %cr17              /* Clear IIASQ tail */
        mtctl           %r0, %cr17              /* Clear IIASQ head */
-        ldil            L%(2f), %r1
-        ldo             R%(2f)(%r1), %r1
        mtctl           %r1, %cr18              /* IIAOQ head */
        ldo             4(%r1), %r1
        mtctl           %r1, %cr18              /* IIAOQ tail */
+        load32          KERNEL_PSW, %r1
+        or              %r1, %r19, %r1  /* I-bit to state on entry */
+        mtctl           %r1, %ipsw      /* restore I-bit (entire PSW) */
        rfi
        nop
 2:      bv              %r0(%r2)
        nop
-        .exit
+        .exit
        .procend
        .export flush_instruction_cache_local,code
@@ -238,7 +236,7 @@ fioneloop:					/* Loop if LOOP = 1 */
 fisync:
        sync
-        mtsm            %r22
+        mtsm            %r22                    /* restore I-bit */
        bv              %r0(%r2)
        nop
        .exit
@@ -281,7 +279,7 @@ fdoneloop:					/* Loop if LOOP = 1 */
 fdsync:
        syncdma
        sync
-        mtsm            %r22
+        mtsm            %r22                    /* restore I-bit */
        bv              %r0(%r2)
        nop
        .exit
@@ -988,11 +986,12 @@ flush_kernel_icache_range_asm:
        bv              %r0(%r2)
        nop
        .exit
        .procend
-        .align  128
+        /* align should cover use of rfi in disable_sr_hashing_asm and
+         * srdis_done.
+         */
+        .align  256
        .export disable_sr_hashing_asm,code
 disable_sr_hashing_asm:
@@ -1000,28 +999,26 @@ disable_sr_hashing_asm:
        .callinfo NO_CALLS
        .entry
-        /* Switch to real mode */
+        /*
+         * Switch to real mode
-        ssm             0, %r0                  /* relied upon translation! */
+         */
-        nop
+        /* pcxt_ssm_bug */
-        nop
+        rsm             PSW_SM_I, %r0
+        load32          PA(1f), %r1
        nop
        nop
        nop
        nop
        nop
-        
-        rsm             (PSW_SM_Q|PSW_SM_I), %r0 /* disable Q&I to load the iia queue */
+        rsm             PSW_SM_Q, %r0           /* prep to load iia queue */
-        ldil            L%REAL_MODE_PSW, %r1
-        ldo             R%REAL_MODE_PSW(%r1), %r1
-        mtctl           %r1, %cr22
        mtctl           %r0, %cr17              /* Clear IIASQ tail */
        mtctl           %r0, %cr17              /* Clear IIASQ head */
-        ldil            L%PA(1f), %r1
-        ldo             R%PA(1f)(%r1), %r1
        mtctl           %r1, %cr18              /* IIAOQ head */
        ldo             4(%r1), %r1
        mtctl           %r1, %cr18              /* IIAOQ tail */
+        load32          REAL_MODE_PSW, %r1
+        mtctl           %r1, %ipsw
        rfi
        nop
@@ -1053,27 +1050,31 @@ srdis_pcxl:
 srdis_pa20:
-        /* Disable Space Register Hashing for PCXU,PCXU+,PCXW,PCXW+ */
+        /* Disable Space Register Hashing for PCXU,PCXU+,PCXW,PCXW+,PCXW2 */
        .word           0x144008bc              /* mfdiag %dr2, %r28 */
        depdi           0, 54,1, %r28           /* clear DIAG_SPHASH_ENAB (bit 54) */
        .word           0x145c1840              /* mtdiag %r28, %dr2 */
-srdis_done:
+srdis_done:
        /* Switch back to virtual mode */
+        rsm             PSW_SM_I, %r0           /* prep to load iia queue */
+        load32          2f, %r1
+        nop
+        nop
+        nop
+        nop
+        nop
-        rsm             PSW_SM_Q, %r0           /* clear Q bit to load iia queue */
+        rsm             PSW_SM_Q, %r0           /* prep to load iia queue */
-        ldil            L%KERNEL_PSW, %r1
-        ldo             R%KERNEL_PSW(%r1), %r1
-        mtctl           %r1, %cr22
        mtctl           %r0, %cr17              /* Clear IIASQ tail */
        mtctl           %r0, %cr17              /* Clear IIASQ head */
-        ldil            L%(2f), %r1
-        ldo             R%(2f)(%r1), %r1
        mtctl           %r1, %cr18              /* IIAOQ head */
        ldo             4(%r1), %r1
        mtctl           %r1, %cr18              /* IIAOQ tail */
+        load32          KERNEL_PSW, %r1
+        mtctl           %r1, %ipsw
        rfi
        nop

diff --git a/arch/parisc/kernel/pacache.S b/arch/parisc/kernel/pacache.S index 77e03bc0f935..71ade44c4618 100644 --- a/arch/parisc/kernel/pacache.S +++ b/arch/parisc/kernel/pacache.S
@@ -40,8 +40,8 @@
40	.level 2.0	40	.level 2.0
41	#endif	41	#endif
42		42
43	#include <asm/assembly.h>
44	#include <asm/psw.h>	43	#include <asm/psw.h>
		44	#include <asm/assembly.h>
45	#include <asm/pgtable.h>	45	#include <asm/pgtable.h>
46	#include <asm/cache.h>	46	#include <asm/cache.h>
47		47
@@ -62,32 +62,23 @@ flush_tlb_all_local:
62	* to happen in real mode with all interruptions disabled.	62	* to happen in real mode with all interruptions disabled.
63	*/	63	*/
64		64
65	/*	65	/* pcxt_ssm_bug - relied upon translation! PA 2.0 Arch. F-4 and F-5 */
66	* Once again, we do the rfi dance ... some day we need examine	66	rsm PSW_SM_I, %r19 /* save I-bit state */
67	* all of our uses of this type of code and see what can be	67	load32 PA(1f), %r1
68	* consolidated.
69	*/
70
71	rsm PSW_SM_I, %r19 /* relied upon translation! PA 2.0 Arch. F-5 */
72	nop	68	nop
73	nop	69	nop
74	nop	70	nop
75	nop	71	nop
76	nop	72	nop
77	nop	73
78	nop	74	rsm PSW_SM_Q, %r0 /* prep to load iia queue */
79
80	rsm PSW_SM_Q, %r0 /* Turn off Q bit to load iia queue */
81	ldil L%REAL_MODE_PSW, %r1
82	ldo R%REAL_MODE_PSW(%r1), %r1
83	mtctl %r1, %cr22
84	mtctl %r0, %cr17 /* Clear IIASQ tail */	75	mtctl %r0, %cr17 /* Clear IIASQ tail */
85	mtctl %r0, %cr17 /* Clear IIASQ head */	76	mtctl %r0, %cr17 /* Clear IIASQ head */
86	ldil L%PA(1f), %r1
87	ldo R%PA(1f)(%r1), %r1
88	mtctl %r1, %cr18 /* IIAOQ head */	77	mtctl %r1, %cr18 /* IIAOQ head */
89	ldo 4(%r1), %r1	78	ldo 4(%r1), %r1
90	mtctl %r1, %cr18 /* IIAOQ tail */	79	mtctl %r1, %cr18 /* IIAOQ tail */
		80	load32 REAL_MODE_PSW, %r1
		81	mtctl %r1, %ipsw
91	rfi	82	rfi
92	nop	83	nop
93		84
@@ -178,29 +169,36 @@ fdtonemiddle: /* Loop if LOOP = 1 */
178	ADDIB> -1, %r22, fdtoneloop /* Outer loop count decr */	169	ADDIB> -1, %r22, fdtoneloop /* Outer loop count decr */
179	add %r21, %r20, %r20 /* increment space */	170	add %r21, %r20, %r20 /* increment space */
180		171
181	fdtdone:
182		172
183	/* Switch back to virtual mode */	173	fdtdone:
		174	/*
		175	* Switch back to virtual mode
		176	*/
		177	/* pcxt_ssm_bug */
		178	rsm PSW_SM_I, %r0
		179	load32 2f, %r1
		180	nop
		181	nop
		182	nop
		183	nop
		184	nop
184		185
185	rsm PSW_SM_Q, %r0 /* clear Q bit to load iia queue */	186	rsm PSW_SM_Q, %r0 /* prep to load iia queue */
186	ldil L%KERNEL_PSW, %r1
187	ldo R%KERNEL_PSW(%r1), %r1
188	or %r1, %r19, %r1 /* Set I bit if set on entry */
189	mtctl %r1, %cr22
190	mtctl %r0, %cr17 /* Clear IIASQ tail */	187	mtctl %r0, %cr17 /* Clear IIASQ tail */
191	mtctl %r0, %cr17 /* Clear IIASQ head */	188	mtctl %r0, %cr17 /* Clear IIASQ head */
192	ldil L%(2f), %r1
193	ldo R%(2f)(%r1), %r1
194	mtctl %r1, %cr18 /* IIAOQ head */	189	mtctl %r1, %cr18 /* IIAOQ head */
195	ldo 4(%r1), %r1	190	ldo 4(%r1), %r1
196	mtctl %r1, %cr18 /* IIAOQ tail */	191	mtctl %r1, %cr18 /* IIAOQ tail */
		192	load32 KERNEL_PSW, %r1
		193	or %r1, %r19, %r1 /* I-bit to state on entry */
		194	mtctl %r1, %ipsw /* restore I-bit (entire PSW) */
197	rfi	195	rfi
198	nop	196	nop
199		197
200	2: bv %r0(%r2)	198	2: bv %r0(%r2)
201	nop	199	nop
202	.exit
203		200
		201	.exit
204	.procend	202	.procend
205		203
206	.export flush_instruction_cache_local,code	204	.export flush_instruction_cache_local,code
@@ -238,7 +236,7 @@ fioneloop: /* Loop if LOOP = 1 */
238		236
239	fisync:	237	fisync:
240	sync	238	sync
241	mtsm %r22	239	mtsm %r22 /* restore I-bit */
242	bv %r0(%r2)	240	bv %r0(%r2)
243	nop	241	nop
244	.exit	242	.exit
@@ -281,7 +279,7 @@ fdoneloop: /* Loop if LOOP = 1 */
281	fdsync:	279	fdsync:
282	syncdma	280	syncdma
283	sync	281	sync
284	mtsm %r22	282	mtsm %r22 /* restore I-bit */
285	bv %r0(%r2)	283	bv %r0(%r2)
286	nop	284	nop
287	.exit	285	.exit
@@ -988,11 +986,12 @@ flush_kernel_icache_range_asm:
988	bv %r0(%r2)	986	bv %r0(%r2)
989	nop	987	nop
990	.exit	988	.exit
991
992	.procend	989	.procend
993		990
994	.align 128	991	/* align should cover use of rfi in disable_sr_hashing_asm and
995		992	* srdis_done.
		993	*/
		994	.align 256
996	.export disable_sr_hashing_asm,code	995	.export disable_sr_hashing_asm,code
997		996
998	disable_sr_hashing_asm:	997	disable_sr_hashing_asm:
@@ -1000,28 +999,26 @@ disable_sr_hashing_asm:
1000	.callinfo NO_CALLS	999	.callinfo NO_CALLS
1001	.entry	1000	.entry
1002		1001
1003	/* Switch to real mode */	1002	/*
1004		1003	* Switch to real mode
1005	ssm 0, %r0 /* relied upon translation! */	1004	*/
1006	nop	1005	/* pcxt_ssm_bug */
1007	nop	1006	rsm PSW_SM_I, %r0
		1007	load32 PA(1f), %r1
1008	nop	1008	nop
1009	nop	1009	nop
1010	nop	1010	nop
1011	nop	1011	nop
1012	nop	1012	nop
1013		1013
1014	rsm (PSW_SM_Q\|PSW_SM_I), %r0 /* disable Q&I to load the iia queue */	1014	rsm PSW_SM_Q, %r0 /* prep to load iia queue */
1015	ldil L%REAL_MODE_PSW, %r1
1016	ldo R%REAL_MODE_PSW(%r1), %r1
1017	mtctl %r1, %cr22
1018	mtctl %r0, %cr17 /* Clear IIASQ tail */	1015	mtctl %r0, %cr17 /* Clear IIASQ tail */
1019	mtctl %r0, %cr17 /* Clear IIASQ head */	1016	mtctl %r0, %cr17 /* Clear IIASQ head */
1020	ldil L%PA(1f), %r1
1021	ldo R%PA(1f)(%r1), %r1
1022	mtctl %r1, %cr18 /* IIAOQ head */	1017	mtctl %r1, %cr18 /* IIAOQ head */
1023	ldo 4(%r1), %r1	1018	ldo 4(%r1), %r1
1024	mtctl %r1, %cr18 /* IIAOQ tail */	1019	mtctl %r1, %cr18 /* IIAOQ tail */
		1020	load32 REAL_MODE_PSW, %r1
		1021	mtctl %r1, %ipsw
1025	rfi	1022	rfi
1026	nop	1023	nop
1027		1024
@@ -1053,27 +1050,31 @@ srdis_pcxl:
1053		1050
1054	srdis_pa20:	1051	srdis_pa20:
1055		1052
1056	/* Disable Space Register Hashing for PCXU,PCXU+,PCXW,PCXW+ */	1053	/* Disable Space Register Hashing for PCXU,PCXU+,PCXW,PCXW+,PCXW2 */
1057		1054
1058	.word 0x144008bc /* mfdiag %dr2, %r28 */	1055	.word 0x144008bc /* mfdiag %dr2, %r28 */
1059	depdi 0, 54,1, %r28 /* clear DIAG_SPHASH_ENAB (bit 54) */	1056	depdi 0, 54,1, %r28 /* clear DIAG_SPHASH_ENAB (bit 54) */
1060	.word 0x145c1840 /* mtdiag %r28, %dr2 */	1057	.word 0x145c1840 /* mtdiag %r28, %dr2 */
1061		1058
1062	srdis_done:
1063		1059
		1060	srdis_done:
1064	/* Switch back to virtual mode */	1061	/* Switch back to virtual mode */
		1062	rsm PSW_SM_I, %r0 /* prep to load iia queue */
		1063	load32 2f, %r1
		1064	nop
		1065	nop
		1066	nop
		1067	nop
		1068	nop
1065		1069
1066	rsm PSW_SM_Q, %r0 /* clear Q bit to load iia queue */	1070	rsm PSW_SM_Q, %r0 /* prep to load iia queue */
1067	ldil L%KERNEL_PSW, %r1
1068	ldo R%KERNEL_PSW(%r1), %r1
1069	mtctl %r1, %cr22
1070	mtctl %r0, %cr17 /* Clear IIASQ tail */	1071	mtctl %r0, %cr17 /* Clear IIASQ tail */
1071	mtctl %r0, %cr17 /* Clear IIASQ head */	1072	mtctl %r0, %cr17 /* Clear IIASQ head */
1072	ldil L%(2f), %r1
1073	ldo R%(2f)(%r1), %r1
1074	mtctl %r1, %cr18 /* IIAOQ head */	1073	mtctl %r1, %cr18 /* IIAOQ head */
1075	ldo 4(%r1), %r1	1074	ldo 4(%r1), %r1
1076	mtctl %r1, %cr18 /* IIAOQ tail */	1075	mtctl %r1, %cr18 /* IIAOQ tail */
		1076	load32 KERNEL_PSW, %r1
		1077	mtctl %r1, %ipsw
1077	rfi	1078	rfi
1078	nop	1079	nop
1079		1080