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-rw-r--r--arch/parisc/kernel/entry.S49
1 files changed, 21 insertions, 28 deletions
diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S
index 111d47284eac..5d0837458c19 100644
--- a/arch/parisc/kernel/entry.S
+++ b/arch/parisc/kernel/entry.S
@@ -38,18 +38,11 @@
38#include <asm/thread_info.h> 38#include <asm/thread_info.h>
39 39
40#include <linux/linkage.h> 40#include <linux/linkage.h>
41#include <linux/init.h>
41 42
42#ifdef CONFIG_64BIT 43#ifdef CONFIG_64BIT
43#define CMPIB cmpib,*
44#define CMPB cmpb,*
45#define COND(x) *x
46
47 .level 2.0w 44 .level 2.0w
48#else 45#else
49#define CMPIB cmpib,
50#define CMPB cmpb,
51#define COND(x) x
52
53 .level 2.0 46 .level 2.0
54#endif 47#endif
55 48
@@ -629,7 +622,7 @@
629 * the static part of the kernel address space. 622 * the static part of the kernel address space.
630 */ 623 */
631 624
632 .text 625 __HEAD
633 626
634 .align PAGE_SIZE 627 .align PAGE_SIZE
635 628
@@ -957,9 +950,9 @@ intr_check_sig:
957 * Only do signals if we are returning to user space 950 * Only do signals if we are returning to user space
958 */ 951 */
959 LDREG PT_IASQ0(%r16), %r20 952 LDREG PT_IASQ0(%r16), %r20
960 CMPIB=,n 0,%r20,intr_restore /* backward */ 953 cmpib,COND(=),n 0,%r20,intr_restore /* backward */
961 LDREG PT_IASQ1(%r16), %r20 954 LDREG PT_IASQ1(%r16), %r20
962 CMPIB=,n 0,%r20,intr_restore /* backward */ 955 cmpib,COND(=),n 0,%r20,intr_restore /* backward */
963 956
964 copy %r0, %r25 /* long in_syscall = 0 */ 957 copy %r0, %r25 /* long in_syscall = 0 */
965#ifdef CONFIG_64BIT 958#ifdef CONFIG_64BIT
@@ -1013,10 +1006,10 @@ intr_do_resched:
1013 * we jump back to intr_restore. 1006 * we jump back to intr_restore.
1014 */ 1007 */
1015 LDREG PT_IASQ0(%r16), %r20 1008 LDREG PT_IASQ0(%r16), %r20
1016 CMPIB= 0, %r20, intr_do_preempt 1009 cmpib,COND(=) 0, %r20, intr_do_preempt
1017 nop 1010 nop
1018 LDREG PT_IASQ1(%r16), %r20 1011 LDREG PT_IASQ1(%r16), %r20
1019 CMPIB= 0, %r20, intr_do_preempt 1012 cmpib,COND(=) 0, %r20, intr_do_preempt
1020 nop 1013 nop
1021 1014
1022#ifdef CONFIG_64BIT 1015#ifdef CONFIG_64BIT
@@ -1045,7 +1038,7 @@ intr_do_preempt:
1045 /* current_thread_info()->preempt_count */ 1038 /* current_thread_info()->preempt_count */
1046 mfctl %cr30, %r1 1039 mfctl %cr30, %r1
1047 LDREG TI_PRE_COUNT(%r1), %r19 1040 LDREG TI_PRE_COUNT(%r1), %r19
1048 CMPIB<> 0, %r19, intr_restore /* if preempt_count > 0 */ 1041 cmpib,COND(<>) 0, %r19, intr_restore /* if preempt_count > 0 */
1049 nop /* prev insn branched backwards */ 1042 nop /* prev insn branched backwards */
1050 1043
1051 /* check if we interrupted a critical path */ 1044 /* check if we interrupted a critical path */
@@ -1064,7 +1057,7 @@ intr_do_preempt:
1064 */ 1057 */
1065 1058
1066intr_extint: 1059intr_extint:
1067 CMPIB=,n 0,%r16,1f 1060 cmpib,COND(=),n 0,%r16,1f
1068 1061
1069 get_stack_use_cr30 1062 get_stack_use_cr30
1070 b,n 2f 1063 b,n 2f
@@ -1099,7 +1092,7 @@ ENDPROC(syscall_exit_rfi)
1099 1092
1100ENTRY(intr_save) /* for os_hpmc */ 1093ENTRY(intr_save) /* for os_hpmc */
1101 mfsp %sr7,%r16 1094 mfsp %sr7,%r16
1102 CMPIB=,n 0,%r16,1f 1095 cmpib,COND(=),n 0,%r16,1f
1103 get_stack_use_cr30 1096 get_stack_use_cr30
1104 b 2f 1097 b 2f
1105 copy %r8,%r26 1098 copy %r8,%r26
@@ -1121,7 +1114,7 @@ ENTRY(intr_save) /* for os_hpmc */
1121 * adjust isr/ior below. 1114 * adjust isr/ior below.
1122 */ 1115 */
1123 1116
1124 CMPIB=,n 6,%r26,skip_save_ior 1117 cmpib,COND(=),n 6,%r26,skip_save_ior
1125 1118
1126 1119
1127 mfctl %cr20, %r16 /* isr */ 1120 mfctl %cr20, %r16 /* isr */
@@ -1450,11 +1443,11 @@ nadtlb_emulate:
1450 bb,>=,n %r9,26,nadtlb_nullify /* m bit not set, just nullify */ 1443 bb,>=,n %r9,26,nadtlb_nullify /* m bit not set, just nullify */
1451 BL get_register,%r25 1444 BL get_register,%r25
1452 extrw,u %r9,15,5,%r8 /* Get index register # */ 1445 extrw,u %r9,15,5,%r8 /* Get index register # */
1453 CMPIB=,n -1,%r1,nadtlb_fault /* have to use slow path */ 1446 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1454 copy %r1,%r24 1447 copy %r1,%r24
1455 BL get_register,%r25 1448 BL get_register,%r25
1456 extrw,u %r9,10,5,%r8 /* Get base register # */ 1449 extrw,u %r9,10,5,%r8 /* Get base register # */
1457 CMPIB=,n -1,%r1,nadtlb_fault /* have to use slow path */ 1450 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1458 BL set_register,%r25 1451 BL set_register,%r25
1459 add,l %r1,%r24,%r1 /* doesn't affect c/b bits */ 1452 add,l %r1,%r24,%r1 /* doesn't affect c/b bits */
1460 1453
@@ -1486,7 +1479,7 @@ nadtlb_probe_check:
1486 cmpb,<>,n %r16,%r17,nadtlb_fault /* Must be probe,[rw]*/ 1479 cmpb,<>,n %r16,%r17,nadtlb_fault /* Must be probe,[rw]*/
1487 BL get_register,%r25 /* Find the target register */ 1480 BL get_register,%r25 /* Find the target register */
1488 extrw,u %r9,31,5,%r8 /* Get target register */ 1481 extrw,u %r9,31,5,%r8 /* Get target register */
1489 CMPIB=,n -1,%r1,nadtlb_fault /* have to use slow path */ 1482 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1490 BL set_register,%r25 1483 BL set_register,%r25
1491 copy %r0,%r1 /* Write zero to target register */ 1484 copy %r0,%r1 /* Write zero to target register */
1492 b nadtlb_nullify /* Nullify return insn */ 1485 b nadtlb_nullify /* Nullify return insn */
@@ -1570,12 +1563,12 @@ dbit_trap_20w:
1570 L3_ptep ptp,pte,t0,va,dbit_fault 1563 L3_ptep ptp,pte,t0,va,dbit_fault
1571 1564
1572#ifdef CONFIG_SMP 1565#ifdef CONFIG_SMP
1573 CMPIB=,n 0,spc,dbit_nolock_20w 1566 cmpib,COND(=),n 0,spc,dbit_nolock_20w
1574 load32 PA(pa_dbit_lock),t0 1567 load32 PA(pa_dbit_lock),t0
1575 1568
1576dbit_spin_20w: 1569dbit_spin_20w:
1577 LDCW 0(t0),t1 1570 LDCW 0(t0),t1
1578 cmpib,= 0,t1,dbit_spin_20w 1571 cmpib,COND(=) 0,t1,dbit_spin_20w
1579 nop 1572 nop
1580 1573
1581dbit_nolock_20w: 1574dbit_nolock_20w:
@@ -1586,7 +1579,7 @@ dbit_nolock_20w:
1586 1579
1587 idtlbt pte,prot 1580 idtlbt pte,prot
1588#ifdef CONFIG_SMP 1581#ifdef CONFIG_SMP
1589 CMPIB=,n 0,spc,dbit_nounlock_20w 1582 cmpib,COND(=),n 0,spc,dbit_nounlock_20w
1590 ldi 1,t1 1583 ldi 1,t1
1591 stw t1,0(t0) 1584 stw t1,0(t0)
1592 1585
@@ -1606,7 +1599,7 @@ dbit_trap_11:
1606 L2_ptep ptp,pte,t0,va,dbit_fault 1599 L2_ptep ptp,pte,t0,va,dbit_fault
1607 1600
1608#ifdef CONFIG_SMP 1601#ifdef CONFIG_SMP
1609 CMPIB=,n 0,spc,dbit_nolock_11 1602 cmpib,COND(=),n 0,spc,dbit_nolock_11
1610 load32 PA(pa_dbit_lock),t0 1603 load32 PA(pa_dbit_lock),t0
1611 1604
1612dbit_spin_11: 1605dbit_spin_11:
@@ -1628,7 +1621,7 @@ dbit_nolock_11:
1628 1621
1629 mtsp t1, %sr1 /* Restore sr1 */ 1622 mtsp t1, %sr1 /* Restore sr1 */
1630#ifdef CONFIG_SMP 1623#ifdef CONFIG_SMP
1631 CMPIB=,n 0,spc,dbit_nounlock_11 1624 cmpib,COND(=),n 0,spc,dbit_nounlock_11
1632 ldi 1,t1 1625 ldi 1,t1
1633 stw t1,0(t0) 1626 stw t1,0(t0)
1634 1627
@@ -1646,7 +1639,7 @@ dbit_trap_20:
1646 L2_ptep ptp,pte,t0,va,dbit_fault 1639 L2_ptep ptp,pte,t0,va,dbit_fault
1647 1640
1648#ifdef CONFIG_SMP 1641#ifdef CONFIG_SMP
1649 CMPIB=,n 0,spc,dbit_nolock_20 1642 cmpib,COND(=),n 0,spc,dbit_nolock_20
1650 load32 PA(pa_dbit_lock),t0 1643 load32 PA(pa_dbit_lock),t0
1651 1644
1652dbit_spin_20: 1645dbit_spin_20:
@@ -1665,7 +1658,7 @@ dbit_nolock_20:
1665 idtlbt pte,prot 1658 idtlbt pte,prot
1666 1659
1667#ifdef CONFIG_SMP 1660#ifdef CONFIG_SMP
1668 CMPIB=,n 0,spc,dbit_nounlock_20 1661 cmpib,COND(=),n 0,spc,dbit_nounlock_20
1669 ldi 1,t1 1662 ldi 1,t1
1670 stw t1,0(t0) 1663 stw t1,0(t0)
1671 1664
@@ -1994,7 +1987,7 @@ ENTRY(syscall_exit)
1994 1987
1995 /* We can't use "CMPIB<> PER_HPUX" since "im5" field is sign extended */ 1988 /* We can't use "CMPIB<> PER_HPUX" since "im5" field is sign extended */
1996 ldo -PER_HPUX(%r19), %r19 1989 ldo -PER_HPUX(%r19), %r19
1997 CMPIB<>,n 0,%r19,1f 1990 cmpib,COND(<>),n 0,%r19,1f
1998 1991
1999 /* Save other hpux returns if personality is PER_HPUX */ 1992 /* Save other hpux returns if personality is PER_HPUX */
2000 STREG %r22,TASK_PT_GR22(%r1) 1993 STREG %r22,TASK_PT_GR22(%r1)