1 files changed, 12 insertions, 1 deletions

diff --git a/arch/parisc/kernel/cache.c b/arch/parisc/kernel/cache.c
index 3f11331c2775..83335f3da5fc 100644
--- a/arch/parisc/kernel/cache.c
+++ b/arch/parisc/kernel/cache.c
@@ -304,10 +304,20 @@ void flush_dcache_page(struct page *page)
                 offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
                 addr = mpnt->vm_start + offset;
 
+                /* The TLB is the engine of coherence on parisc: The
+                 * CPU is entitled to speculate any page with a TLB
+                 * mapping, so here we kill the mapping then flush the
+                 * page along a special flush only alias mapping.
+                 * This guarantees that the page is no-longer in the
+                 * cache for any process and nor may it be
+                 * speculatively read in (until the user or kernel
+                 * specifically accesses it, of course) */
+
+                flush_tlb_page(mpnt, addr);
                 if (old_addr == 0 || (old_addr & (SHMLBA - 1)) != (addr & (SHMLBA - 1))) {
                         __flush_cache_page(mpnt, addr, page_to_phys(page));
                         if (old_addr)
-                                printk(KERN_ERR "INEQUIVALENT ALIASES 0x%lx and 0x%lx in file %s\n", old_addr, addr, mpnt->vm_file ? mpnt->vm_file->f_path.dentry->d_name.name : "(null)");
+                                printk(KERN_ERR "INEQUIVALENT ALIASES 0x%lx and 0x%lx in file %s\n", old_addr, addr, mpnt->vm_file ? (char *)mpnt->vm_file->f_path.dentry->d_name.name : "(null)");
                         old_addr = addr;
                 }
         }
@@ -499,6 +509,7 @@ flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long
 {
         BUG_ON(!vma->vm_mm->context);
 
+        flush_tlb_page(vma, vmaddr);
         __flush_cache_page(vma, vmaddr, page_to_phys(pfn_to_page(pfn)));
 
 }