1 files changed, 7 insertions, 7 deletions

diff --git a/arch/parisc/include/asm/tlbflush.h b/arch/parisc/include/asm/tlbflush.h
index 1f6fd4fc05b9..8f1a8100bf2d 100644
--- a/arch/parisc/include/asm/tlbflush.h
+++ b/arch/parisc/include/asm/tlbflush.h
@@ -12,14 +12,12 @@
  * N class systems, only one PxTLB inter processor broadcast can be
  * active at any one time on the Merced bus.  This tlb purge
  * synchronisation is fairly lightweight and harmless so we activate
- * it on all SMP systems not just the N class.  We also need to have
- * preemption disabled on uniprocessor machines, and spin_lock does that
- * nicely.
+ * it on all systems not just the N class.
  */
 extern spinlock_t pa_tlb_lock;
 
-#define purge_tlb_start(x) spin_lock(&pa_tlb_lock)
-#define purge_tlb_end(x) spin_unlock(&pa_tlb_lock)
+#define purge_tlb_start(flags)  spin_lock_irqsave(&pa_tlb_lock, flags)
+#define purge_tlb_end(flags)    spin_unlock_irqrestore(&pa_tlb_lock, flags)
 
 extern void flush_tlb_all(void);
 extern void flush_tlb_all_local(void *);
@@ -63,14 +61,16 @@ static inline void flush_tlb_mm(struct mm_struct *mm)
 static inline void flush_tlb_page(struct vm_area_struct *vma,
         unsigned long addr)
 {
+        unsigned long flags;
+
         /* For one page, it's not worth testing the split_tlb variable */
 
         mb();
         mtsp(vma->vm_mm->context,1);
-        purge_tlb_start();
+        purge_tlb_start(flags);
         pdtlb(addr);
         pitlb(addr);
-        purge_tlb_end();
+        purge_tlb_end(flags);
 }
 
 void __flush_tlb_range(unsigned long sid,