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-rw-r--r--arch/parisc/include/asm/atomic.h11
1 files changed, 3 insertions, 8 deletions
diff --git a/arch/parisc/include/asm/atomic.h b/arch/parisc/include/asm/atomic.h
index 57fcc4a5ebb4..edbfe25c5fc1 100644
--- a/arch/parisc/include/asm/atomic.h
+++ b/arch/parisc/include/asm/atomic.h
@@ -155,14 +155,11 @@ static inline unsigned long __cmpxchg_local(volatile void *ptr,
155#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) 155#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
156#endif 156#endif
157 157
158/* Note that we need not lock read accesses - aligned word writes/reads 158/*
159 * are atomic, so a reader never sees unconsistent values. 159 * Note that we need not lock read accesses - aligned word writes/reads
160 * 160 * are atomic, so a reader never sees inconsistent values.
161 * Cache-line alignment would conflict with, for example, linux/module.h
162 */ 161 */
163 162
164typedef struct { volatile int counter; } atomic_t;
165
166/* It's possible to reduce all atomic operations to either 163/* It's possible to reduce all atomic operations to either
167 * __atomic_add_return, atomic_set and atomic_read (the latter 164 * __atomic_add_return, atomic_set and atomic_read (the latter
168 * is there only for consistency). 165 * is there only for consistency).
@@ -260,8 +257,6 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
260 257
261#ifdef CONFIG_64BIT 258#ifdef CONFIG_64BIT
262 259
263typedef struct { volatile s64 counter; } atomic64_t;
264
265#define ATOMIC64_INIT(i) ((atomic64_t) { (i) }) 260#define ATOMIC64_INIT(i) ((atomic64_t) { (i) })
266 261
267static __inline__ int 262static __inline__ int