diff options
Diffstat (limited to 'arch/mn10300')
-rw-r--r-- | arch/mn10300/Kconfig | 2 | ||||
-rw-r--r-- | arch/mn10300/include/asm/cpu-regs.h | 2 | ||||
-rw-r--r-- | arch/mn10300/kernel/irq.c | 85 | ||||
-rw-r--r-- | arch/mn10300/kernel/mn10300-serial.c | 2 | ||||
-rw-r--r-- | arch/mn10300/kernel/smp.c | 12 | ||||
-rw-r--r-- | arch/mn10300/unit-asb2364/irq-fpga.c | 3 |
6 files changed, 29 insertions, 77 deletions
diff --git a/arch/mn10300/Kconfig b/arch/mn10300/Kconfig index d8ab97a73db2..feaf09cc8632 100644 --- a/arch/mn10300/Kconfig +++ b/arch/mn10300/Kconfig | |||
@@ -2,7 +2,7 @@ config MN10300 | |||
2 | def_bool y | 2 | def_bool y |
3 | select HAVE_OPROFILE | 3 | select HAVE_OPROFILE |
4 | select HAVE_GENERIC_HARDIRQS | 4 | select HAVE_GENERIC_HARDIRQS |
5 | select GENERIC_HARDIRQS_NO_DEPRECATED | 5 | select GENERIC_IRQ_SHOW |
6 | select HAVE_ARCH_TRACEHOOK | 6 | select HAVE_ARCH_TRACEHOOK |
7 | select HAVE_ARCH_KGDB | 7 | select HAVE_ARCH_KGDB |
8 | 8 | ||
diff --git a/arch/mn10300/include/asm/cpu-regs.h b/arch/mn10300/include/asm/cpu-regs.h index 90ed4a365c97..c54effae2202 100644 --- a/arch/mn10300/include/asm/cpu-regs.h +++ b/arch/mn10300/include/asm/cpu-regs.h | |||
@@ -49,7 +49,7 @@ asm(" .am33_2\n"); | |||
49 | #define EPSW_IM_6 0x00000600 /* interrupt mode 6 */ | 49 | #define EPSW_IM_6 0x00000600 /* interrupt mode 6 */ |
50 | #define EPSW_IM_7 0x00000700 /* interrupt mode 7 */ | 50 | #define EPSW_IM_7 0x00000700 /* interrupt mode 7 */ |
51 | #define EPSW_IE 0x00000800 /* interrupt enable */ | 51 | #define EPSW_IE 0x00000800 /* interrupt enable */ |
52 | #define EPSW_S 0x00003000 /* software auxilliary bits */ | 52 | #define EPSW_S 0x00003000 /* software auxiliary bits */ |
53 | #define EPSW_T 0x00008000 /* trace enable */ | 53 | #define EPSW_T 0x00008000 /* trace enable */ |
54 | #define EPSW_nSL 0x00010000 /* not supervisor level */ | 54 | #define EPSW_nSL 0x00010000 /* not supervisor level */ |
55 | #define EPSW_NMID 0x00020000 /* nonmaskable interrupt disable */ | 55 | #define EPSW_NMID 0x00020000 /* nonmaskable interrupt disable */ |
diff --git a/arch/mn10300/kernel/irq.c b/arch/mn10300/kernel/irq.c index 5f7fc3eb45e6..86af0d7d0771 100644 --- a/arch/mn10300/kernel/irq.c +++ b/arch/mn10300/kernel/irq.c | |||
@@ -263,7 +263,7 @@ void set_intr_level(int irq, u16 level) | |||
263 | */ | 263 | */ |
264 | void mn10300_set_lateack_irq_type(int irq) | 264 | void mn10300_set_lateack_irq_type(int irq) |
265 | { | 265 | { |
266 | set_irq_chip_and_handler(irq, &mn10300_cpu_pic_level, | 266 | irq_set_chip_and_handler(irq, &mn10300_cpu_pic_level, |
267 | handle_level_irq); | 267 | handle_level_irq); |
268 | } | 268 | } |
269 | 269 | ||
@@ -275,12 +275,12 @@ void __init init_IRQ(void) | |||
275 | int irq; | 275 | int irq; |
276 | 276 | ||
277 | for (irq = 0; irq < NR_IRQS; irq++) | 277 | for (irq = 0; irq < NR_IRQS; irq++) |
278 | if (get_irq_chip(irq) == &no_irq_chip) | 278 | if (irq_get_chip(irq) == &no_irq_chip) |
279 | /* due to the PIC latching interrupt requests, even | 279 | /* due to the PIC latching interrupt requests, even |
280 | * when the IRQ is disabled, IRQ_PENDING is superfluous | 280 | * when the IRQ is disabled, IRQ_PENDING is superfluous |
281 | * and we can use handle_level_irq() for edge-triggered | 281 | * and we can use handle_level_irq() for edge-triggered |
282 | * interrupts */ | 282 | * interrupts */ |
283 | set_irq_chip_and_handler(irq, &mn10300_cpu_pic_edge, | 283 | irq_set_chip_and_handler(irq, &mn10300_cpu_pic_edge, |
284 | handle_level_irq); | 284 | handle_level_irq); |
285 | 285 | ||
286 | unit_init_IRQ(); | 286 | unit_init_IRQ(); |
@@ -335,91 +335,42 @@ asmlinkage void do_IRQ(void) | |||
335 | /* | 335 | /* |
336 | * Display interrupt management information through /proc/interrupts | 336 | * Display interrupt management information through /proc/interrupts |
337 | */ | 337 | */ |
338 | int show_interrupts(struct seq_file *p, void *v) | 338 | int arch_show_interrupts(struct seq_file *p, int prec) |
339 | { | 339 | { |
340 | int i = *(loff_t *) v, j, cpu; | ||
341 | struct irqaction *action; | ||
342 | unsigned long flags; | ||
343 | |||
344 | switch (i) { | ||
345 | /* display column title bar naming CPUs */ | ||
346 | case 0: | ||
347 | seq_printf(p, " "); | ||
348 | for (j = 0; j < NR_CPUS; j++) | ||
349 | if (cpu_online(j)) | ||
350 | seq_printf(p, "CPU%d ", j); | ||
351 | seq_putc(p, '\n'); | ||
352 | break; | ||
353 | |||
354 | /* display information rows, one per active CPU */ | ||
355 | case 1 ... NR_IRQS - 1: | ||
356 | raw_spin_lock_irqsave(&irq_desc[i].lock, flags); | ||
357 | |||
358 | action = irq_desc[i].action; | ||
359 | if (action) { | ||
360 | seq_printf(p, "%3d: ", i); | ||
361 | for_each_present_cpu(cpu) | ||
362 | seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu)); | ||
363 | |||
364 | if (i < NR_CPU_IRQS) | ||
365 | seq_printf(p, " %14s.%u", | ||
366 | irq_desc[i].irq_data.chip->name, | ||
367 | (GxICR(i) & GxICR_LEVEL) >> | ||
368 | GxICR_LEVEL_SHIFT); | ||
369 | else | ||
370 | seq_printf(p, " %14s", | ||
371 | irq_desc[i].irq_data.chip->name); | ||
372 | |||
373 | seq_printf(p, " %s", action->name); | ||
374 | |||
375 | for (action = action->next; | ||
376 | action; | ||
377 | action = action->next) | ||
378 | seq_printf(p, ", %s", action->name); | ||
379 | |||
380 | seq_putc(p, '\n'); | ||
381 | } | ||
382 | |||
383 | raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); | ||
384 | break; | ||
385 | |||
386 | /* polish off with NMI and error counters */ | ||
387 | case NR_IRQS: | ||
388 | #ifdef CONFIG_MN10300_WD_TIMER | 340 | #ifdef CONFIG_MN10300_WD_TIMER |
389 | seq_printf(p, "NMI: "); | 341 | int j; |
390 | for (j = 0; j < NR_CPUS; j++) | ||
391 | if (cpu_online(j)) | ||
392 | seq_printf(p, "%10u ", nmi_count(j)); | ||
393 | seq_putc(p, '\n'); | ||
394 | #endif | ||
395 | 342 | ||
396 | seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count)); | 343 | seq_printf(p, "%*s: ", prec, "NMI"); |
397 | break; | 344 | for (j = 0; j < NR_CPUS; j++) |
398 | } | 345 | if (cpu_online(j)) |
346 | seq_printf(p, "%10u ", nmi_count(j)); | ||
347 | seq_putc(p, '\n'); | ||
348 | #endif | ||
399 | 349 | ||
350 | seq_printf(p, "%*s: ", prec, "ERR"); | ||
351 | seq_printf(p, "%10u\n", atomic_read(&irq_err_count)); | ||
400 | return 0; | 352 | return 0; |
401 | } | 353 | } |
402 | 354 | ||
403 | #ifdef CONFIG_HOTPLUG_CPU | 355 | #ifdef CONFIG_HOTPLUG_CPU |
404 | void migrate_irqs(void) | 356 | void migrate_irqs(void) |
405 | { | 357 | { |
406 | irq_desc_t *desc; | ||
407 | int irq; | 358 | int irq; |
408 | unsigned int self, new; | 359 | unsigned int self, new; |
409 | unsigned long flags; | 360 | unsigned long flags; |
410 | 361 | ||
411 | self = smp_processor_id(); | 362 | self = smp_processor_id(); |
412 | for (irq = 0; irq < NR_IRQS; irq++) { | 363 | for (irq = 0; irq < NR_IRQS; irq++) { |
413 | desc = irq_desc + irq; | 364 | struct irq_data *data = irq_get_irq_data(irq); |
414 | 365 | ||
415 | if (desc->status == IRQ_PER_CPU) | 366 | if (irqd_is_per_cpu(data)) |
416 | continue; | 367 | continue; |
417 | 368 | ||
418 | if (cpu_isset(self, irq_desc[irq].affinity) && | 369 | if (cpu_isset(self, data->affinity) && |
419 | !cpus_intersects(irq_affinity[irq], cpu_online_map)) { | 370 | !cpus_intersects(irq_affinity[irq], cpu_online_map)) { |
420 | int cpu_id; | 371 | int cpu_id; |
421 | cpu_id = first_cpu(cpu_online_map); | 372 | cpu_id = first_cpu(cpu_online_map); |
422 | cpu_set(cpu_id, irq_desc[irq].affinity); | 373 | cpu_set(cpu_id, data->affinity); |
423 | } | 374 | } |
424 | /* We need to operate irq_affinity_online atomically. */ | 375 | /* We need to operate irq_affinity_online atomically. */ |
425 | arch_local_cli_save(flags); | 376 | arch_local_cli_save(flags); |
@@ -430,7 +381,7 @@ void migrate_irqs(void) | |||
430 | GxICR(irq) = x & GxICR_LEVEL; | 381 | GxICR(irq) = x & GxICR_LEVEL; |
431 | tmp = GxICR(irq); | 382 | tmp = GxICR(irq); |
432 | 383 | ||
433 | new = any_online_cpu(irq_desc[irq].affinity); | 384 | new = any_online_cpu(data->affinity); |
434 | irq_affinity_online[irq] = new; | 385 | irq_affinity_online[irq] = new; |
435 | 386 | ||
436 | CROSS_GxICR(irq, new) = | 387 | CROSS_GxICR(irq, new) = |
diff --git a/arch/mn10300/kernel/mn10300-serial.c b/arch/mn10300/kernel/mn10300-serial.c index efca426a2ed4..94901c56baf1 100644 --- a/arch/mn10300/kernel/mn10300-serial.c +++ b/arch/mn10300/kernel/mn10300-serial.c | |||
@@ -933,7 +933,7 @@ static int mn10300_serial_startup(struct uart_port *_port) | |||
933 | NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL)); | 933 | NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL)); |
934 | set_intr_level(port->tx_irq, | 934 | set_intr_level(port->tx_irq, |
935 | NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL)); | 935 | NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL)); |
936 | set_irq_chip(port->tm_irq, &mn10300_serial_pic); | 936 | irq_set_chip(port->tm_irq, &mn10300_serial_pic); |
937 | 937 | ||
938 | if (request_irq(port->rx_irq, mn10300_serial_interrupt, | 938 | if (request_irq(port->rx_irq, mn10300_serial_interrupt, |
939 | IRQF_DISABLED, port->rx_name, port) < 0) | 939 | IRQF_DISABLED, port->rx_name, port) < 0) |
diff --git a/arch/mn10300/kernel/smp.c b/arch/mn10300/kernel/smp.c index 51c02f97dcea..226c826a2194 100644 --- a/arch/mn10300/kernel/smp.c +++ b/arch/mn10300/kernel/smp.c | |||
@@ -156,15 +156,15 @@ static void init_ipi(void) | |||
156 | u16 tmp16; | 156 | u16 tmp16; |
157 | 157 | ||
158 | /* set up the reschedule IPI */ | 158 | /* set up the reschedule IPI */ |
159 | set_irq_chip_and_handler(RESCHEDULE_IPI, | 159 | irq_set_chip_and_handler(RESCHEDULE_IPI, &mn10300_ipi_type, |
160 | &mn10300_ipi_type, handle_percpu_irq); | 160 | handle_percpu_irq); |
161 | setup_irq(RESCHEDULE_IPI, &reschedule_ipi); | 161 | setup_irq(RESCHEDULE_IPI, &reschedule_ipi); |
162 | set_intr_level(RESCHEDULE_IPI, RESCHEDULE_GxICR_LV); | 162 | set_intr_level(RESCHEDULE_IPI, RESCHEDULE_GxICR_LV); |
163 | mn10300_ipi_enable(RESCHEDULE_IPI); | 163 | mn10300_ipi_enable(RESCHEDULE_IPI); |
164 | 164 | ||
165 | /* set up the call function IPI */ | 165 | /* set up the call function IPI */ |
166 | set_irq_chip_and_handler(CALL_FUNC_SINGLE_IPI, | 166 | irq_set_chip_and_handler(CALL_FUNC_SINGLE_IPI, &mn10300_ipi_type, |
167 | &mn10300_ipi_type, handle_percpu_irq); | 167 | handle_percpu_irq); |
168 | setup_irq(CALL_FUNC_SINGLE_IPI, &call_function_ipi); | 168 | setup_irq(CALL_FUNC_SINGLE_IPI, &call_function_ipi); |
169 | set_intr_level(CALL_FUNC_SINGLE_IPI, CALL_FUNCTION_GxICR_LV); | 169 | set_intr_level(CALL_FUNC_SINGLE_IPI, CALL_FUNCTION_GxICR_LV); |
170 | mn10300_ipi_enable(CALL_FUNC_SINGLE_IPI); | 170 | mn10300_ipi_enable(CALL_FUNC_SINGLE_IPI); |
@@ -172,8 +172,8 @@ static void init_ipi(void) | |||
172 | /* set up the local timer IPI */ | 172 | /* set up the local timer IPI */ |
173 | #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || \ | 173 | #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || \ |
174 | defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) | 174 | defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) |
175 | set_irq_chip_and_handler(LOCAL_TIMER_IPI, | 175 | irq_set_chip_and_handler(LOCAL_TIMER_IPI, &mn10300_ipi_type, |
176 | &mn10300_ipi_type, handle_percpu_irq); | 176 | handle_percpu_irq); |
177 | setup_irq(LOCAL_TIMER_IPI, &local_timer_ipi); | 177 | setup_irq(LOCAL_TIMER_IPI, &local_timer_ipi); |
178 | set_intr_level(LOCAL_TIMER_IPI, LOCAL_TIMER_GxICR_LV); | 178 | set_intr_level(LOCAL_TIMER_IPI, LOCAL_TIMER_GxICR_LV); |
179 | mn10300_ipi_enable(LOCAL_TIMER_IPI); | 179 | mn10300_ipi_enable(LOCAL_TIMER_IPI); |
diff --git a/arch/mn10300/unit-asb2364/irq-fpga.c b/arch/mn10300/unit-asb2364/irq-fpga.c index ee84e62b16ed..e16c216f31dc 100644 --- a/arch/mn10300/unit-asb2364/irq-fpga.c +++ b/arch/mn10300/unit-asb2364/irq-fpga.c | |||
@@ -100,7 +100,8 @@ void __init irq_fpga_init(void) | |||
100 | SyncExBus(); | 100 | SyncExBus(); |
101 | 101 | ||
102 | for (irq = NR_CPU_IRQS; irq < NR_IRQS; irq++) | 102 | for (irq = NR_CPU_IRQS; irq < NR_IRQS; irq++) |
103 | set_irq_chip_and_handler(irq, &asb2364_fpga_pic, handle_level_irq); | 103 | irq_set_chip_and_handler(irq, &asb2364_fpga_pic, |
104 | handle_level_irq); | ||
104 | 105 | ||
105 | /* the FPGA drives the XIRQ1 input on the CPU PIC */ | 106 | /* the FPGA drives the XIRQ1 input on the CPU PIC */ |
106 | setup_irq(XIRQ1, &fpga_irq[0]); | 107 | setup_irq(XIRQ1, &fpga_irq[0]); |