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-rw-r--r--arch/mn10300/Kconfig.debug9
-rw-r--r--arch/mn10300/kernel/entry.S3
-rw-r--r--arch/mn10300/kernel/gdb-io-serial.c2
-rw-r--r--arch/mn10300/kernel/gdb-stub.c24
-rw-r--r--arch/mn10300/kernel/mn10300-serial.c5
-rw-r--r--arch/mn10300/kernel/module.c35
-rw-r--r--arch/mn10300/kernel/setup.c2
-rw-r--r--arch/mn10300/kernel/vmlinux.lds.S22
-rw-r--r--arch/mn10300/mm/misalignment.c538
9 files changed, 461 insertions, 179 deletions
diff --git a/arch/mn10300/Kconfig.debug b/arch/mn10300/Kconfig.debug
index 524e33819f32..ff80e86b9bd2 100644
--- a/arch/mn10300/Kconfig.debug
+++ b/arch/mn10300/Kconfig.debug
@@ -15,6 +15,15 @@ config DEBUG_DECOMPRESS_KERNEL
15 decompressing Linux seeing "Uncompressing Linux... " and 15 decompressing Linux seeing "Uncompressing Linux... " and
16 "Ok, booting the kernel.\n" on console. 16 "Ok, booting the kernel.\n" on console.
17 17
18config TEST_MISALIGNMENT_HANDLER
19 bool "Run tests on the misalignment handler"
20 depends on DEBUG_KERNEL
21 default n
22 help
23 If you say Y here the kernel will execute a list of misaligned memory
24 accesses to make sure the misalignment handler deals them with
25 correctly. If it does not, the kernel will throw a BUG.
26
18config KPROBES 27config KPROBES
19 bool "Kprobes" 28 bool "Kprobes"
20 depends on DEBUG_KERNEL 29 depends on DEBUG_KERNEL
diff --git a/arch/mn10300/kernel/entry.S b/arch/mn10300/kernel/entry.S
index b7cbb1487af4..62fba8aa9b6e 100644
--- a/arch/mn10300/kernel/entry.S
+++ b/arch/mn10300/kernel/entry.S
@@ -180,6 +180,7 @@ ENTRY(resume_userspace)
180 180
181#ifdef CONFIG_PREEMPT 181#ifdef CONFIG_PREEMPT
182ENTRY(resume_kernel) 182ENTRY(resume_kernel)
183 __cli
183 mov (TI_preempt_count,a2),d0 # non-zero preempt_count ? 184 mov (TI_preempt_count,a2),d0 # non-zero preempt_count ?
184 cmp 0,d0 185 cmp 0,d0
185 bne restore_all 186 bne restore_all
@@ -190,7 +191,7 @@ need_resched:
190 mov (REG_EPSW,fp),d0 191 mov (REG_EPSW,fp),d0
191 and EPSW_IM,d0 192 and EPSW_IM,d0
192 cmp EPSW_IM_7,d0 # interrupts off (exception path) ? 193 cmp EPSW_IM_7,d0 # interrupts off (exception path) ?
193 beq restore_all 194 bne restore_all
194 call preempt_schedule_irq[],0 195 call preempt_schedule_irq[],0
195 jmp need_resched 196 jmp need_resched
196#endif 197#endif
diff --git a/arch/mn10300/kernel/gdb-io-serial.c b/arch/mn10300/kernel/gdb-io-serial.c
index 9a6d4e8ebe73..11584c51acd9 100644
--- a/arch/mn10300/kernel/gdb-io-serial.c
+++ b/arch/mn10300/kernel/gdb-io-serial.c
@@ -99,6 +99,7 @@ int gdbstub_io_rx_char(unsigned char *_ch, int nonblock)
99 try_again: 99 try_again:
100 /* pull chars out of the buffer */ 100 /* pull chars out of the buffer */
101 ix = gdbstub_rx_outp; 101 ix = gdbstub_rx_outp;
102 barrier();
102 if (ix == gdbstub_rx_inp) { 103 if (ix == gdbstub_rx_inp) {
103 if (nonblock) 104 if (nonblock)
104 return -EAGAIN; 105 return -EAGAIN;
@@ -110,6 +111,7 @@ int gdbstub_io_rx_char(unsigned char *_ch, int nonblock)
110 111
111 ch = gdbstub_rx_buffer[ix++]; 112 ch = gdbstub_rx_buffer[ix++];
112 st = gdbstub_rx_buffer[ix++]; 113 st = gdbstub_rx_buffer[ix++];
114 barrier();
113 gdbstub_rx_outp = ix & 0x00000fff; 115 gdbstub_rx_outp = ix & 0x00000fff;
114 116
115 if (st & UART_LSR_BI) { 117 if (st & UART_LSR_BI) {
diff --git a/arch/mn10300/kernel/gdb-stub.c b/arch/mn10300/kernel/gdb-stub.c
index 54be6afb5555..0ea7482c1522 100644
--- a/arch/mn10300/kernel/gdb-stub.c
+++ b/arch/mn10300/kernel/gdb-stub.c
@@ -522,17 +522,7 @@ static int gdbstub_single_step(struct pt_regs *regs)
522 } else { 522 } else {
523 switch (cur) { 523 switch (cur) {
524 /* Bxx (d8,PC) */ 524 /* Bxx (d8,PC) */
525 case 0xc0: 525 case 0xc0 ... 0xca:
526 case 0xc1:
527 case 0xc2:
528 case 0xc3:
529 case 0xc4:
530 case 0xc5:
531 case 0xc6:
532 case 0xc7:
533 case 0xc8:
534 case 0xc9:
535 case 0xca:
536 if (gdbstub_read_byte(pc + 1, (u8 *) &x) < 0) 526 if (gdbstub_read_byte(pc + 1, (u8 *) &x) < 0)
537 goto fault; 527 goto fault;
538 if (!__gdbstub_mark_bp(pc + 2, 0)) 528 if (!__gdbstub_mark_bp(pc + 2, 0))
@@ -543,17 +533,7 @@ static int gdbstub_single_step(struct pt_regs *regs)
543 break; 533 break;
544 534
545 /* LXX (d8,PC) */ 535 /* LXX (d8,PC) */
546 case 0xd0: 536 case 0xd0 ... 0xda:
547 case 0xd1:
548 case 0xd2:
549 case 0xd3:
550 case 0xd4:
551 case 0xd5:
552 case 0xd6:
553 case 0xd7:
554 case 0xd8:
555 case 0xd9:
556 case 0xda:
557 if (!__gdbstub_mark_bp(pc + 1, 0)) 537 if (!__gdbstub_mark_bp(pc + 1, 0))
558 goto fault; 538 goto fault;
559 if (regs->pc != regs->lar && 539 if (regs->pc != regs->lar &&
diff --git a/arch/mn10300/kernel/mn10300-serial.c b/arch/mn10300/kernel/mn10300-serial.c
index aa07d0cd1905..59b9c4bf9583 100644
--- a/arch/mn10300/kernel/mn10300-serial.c
+++ b/arch/mn10300/kernel/mn10300-serial.c
@@ -566,6 +566,11 @@ static void mn10300_serial_transmit_interrupt(struct mn10300_serial_port *port)
566{ 566{
567 _enter("%s", port->name); 567 _enter("%s", port->name);
568 568
569 if (!port->uart.info || !port->uart.info->port.tty) {
570 mn10300_serial_dis_tx_intr(port);
571 return;
572 }
573
569 if (uart_tx_stopped(&port->uart) || 574 if (uart_tx_stopped(&port->uart) ||
570 uart_circ_empty(&port->uart.info->xmit)) 575 uart_circ_empty(&port->uart.info->xmit))
571 mn10300_serial_dis_tx_intr(port); 576 mn10300_serial_dis_tx_intr(port);
diff --git a/arch/mn10300/kernel/module.c b/arch/mn10300/kernel/module.c
index 8fa36893df7a..6b287f2e8e84 100644
--- a/arch/mn10300/kernel/module.c
+++ b/arch/mn10300/kernel/module.c
@@ -1,6 +1,6 @@
1/* MN10300 Kernel module helper routines 1/* MN10300 Kernel module helper routines
2 * 2 *
3 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. 3 * Copyright (C) 2007, 2008 Red Hat, Inc. All Rights Reserved.
4 * Written by Mark Salter (msalter@redhat.com) 4 * Written by Mark Salter (msalter@redhat.com)
5 * - Derived from arch/i386/kernel/module.c 5 * - Derived from arch/i386/kernel/module.c
6 * 6 *
@@ -64,21 +64,6 @@ int module_frob_arch_sections(Elf_Ehdr *hdr,
64 return 0; 64 return 0;
65} 65}
66 66
67static uint32_t reloc_get16(uint8_t *p)
68{
69 return p[0] | (p[1] << 8);
70}
71
72static uint32_t reloc_get24(uint8_t *p)
73{
74 return reloc_get16(p) | (p[2] << 16);
75}
76
77static uint32_t reloc_get32(uint8_t *p)
78{
79 return reloc_get16(p) | (reloc_get16(p+2) << 16);
80}
81
82static void reloc_put16(uint8_t *p, uint32_t val) 67static void reloc_put16(uint8_t *p, uint32_t val)
83{ 68{
84 p[0] = val & 0xff; 69 p[0] = val & 0xff;
@@ -144,25 +129,19 @@ int apply_relocate_add(Elf32_Shdr *sechdrs,
144 relocation = sym->st_value + rel[i].r_addend; 129 relocation = sym->st_value + rel[i].r_addend;
145 130
146 switch (ELF32_R_TYPE(rel[i].r_info)) { 131 switch (ELF32_R_TYPE(rel[i].r_info)) {
147 /* for the first four relocation types, we add the 132 /* for the first four relocation types, we simply
148 * adjustment into the value at the location given */ 133 * store the adjustment at the location given */
149 case R_MN10300_32: 134 case R_MN10300_32:
150 value = reloc_get32(location); 135 reloc_put32(location, relocation);
151 value += relocation;
152 reloc_put32(location, value);
153 break; 136 break;
154 case R_MN10300_24: 137 case R_MN10300_24:
155 value = reloc_get24(location); 138 reloc_put24(location, relocation);
156 value += relocation;
157 reloc_put24(location, value);
158 break; 139 break;
159 case R_MN10300_16: 140 case R_MN10300_16:
160 value = reloc_get16(location); 141 reloc_put16(location, relocation);
161 value += relocation;
162 reloc_put16(location, value);
163 break; 142 break;
164 case R_MN10300_8: 143 case R_MN10300_8:
165 *location += relocation; 144 *location = relocation;
166 break; 145 break;
167 146
168 /* for the next three relocation types, we write the 147 /* for the next three relocation types, we write the
diff --git a/arch/mn10300/kernel/setup.c b/arch/mn10300/kernel/setup.c
index 017121ce896f..e1d88ab51008 100644
--- a/arch/mn10300/kernel/setup.c
+++ b/arch/mn10300/kernel/setup.c
@@ -161,7 +161,7 @@ void __init setup_arch(char **cmdline_p)
161 reserve the page it is occupying. */ 161 reserve the page it is occupying. */
162 if (CONFIG_INTERRUPT_VECTOR_BASE >= CONFIG_KERNEL_RAM_BASE_ADDRESS && 162 if (CONFIG_INTERRUPT_VECTOR_BASE >= CONFIG_KERNEL_RAM_BASE_ADDRESS &&
163 CONFIG_INTERRUPT_VECTOR_BASE < memory_end) 163 CONFIG_INTERRUPT_VECTOR_BASE < memory_end)
164 reserve_bootmem(CONFIG_INTERRUPT_VECTOR_BASE, 1, 164 reserve_bootmem(CONFIG_INTERRUPT_VECTOR_BASE, PAGE_SIZE,
165 BOOTMEM_DEFAULT); 165 BOOTMEM_DEFAULT);
166 166
167 reserve_bootmem(PAGE_ALIGN(PFN_PHYS(free_pfn)), bootmap_size, 167 reserve_bootmem(PAGE_ALIGN(PFN_PHYS(free_pfn)), bootmap_size,
diff --git a/arch/mn10300/kernel/vmlinux.lds.S b/arch/mn10300/kernel/vmlinux.lds.S
index a3e80f444f55..b8259668f7dc 100644
--- a/arch/mn10300/kernel/vmlinux.lds.S
+++ b/arch/mn10300/kernel/vmlinux.lds.S
@@ -11,6 +11,7 @@
11#define __VMLINUX_LDS__ 11#define __VMLINUX_LDS__
12#include <asm-generic/vmlinux.lds.h> 12#include <asm-generic/vmlinux.lds.h>
13#include <asm/thread_info.h> 13#include <asm/thread_info.h>
14#include <asm/page.h>
14 15
15OUTPUT_FORMAT("elf32-am33lin", "elf32-am33lin", "elf32-am33lin") 16OUTPUT_FORMAT("elf32-am33lin", "elf32-am33lin", "elf32-am33lin")
16OUTPUT_ARCH(mn10300) 17OUTPUT_ARCH(mn10300)
@@ -55,13 +56,13 @@ SECTIONS
55 CONSTRUCTORS 56 CONSTRUCTORS
56 } 57 }
57 58
58 . = ALIGN(4096); 59 . = ALIGN(PAGE_SIZE);
59 __nosave_begin = .; 60 __nosave_begin = .;
60 .data_nosave : { *(.data.nosave) } 61 .data_nosave : { *(.data.nosave) }
61 . = ALIGN(4096); 62 . = ALIGN(PAGE_SIZE);
62 __nosave_end = .; 63 __nosave_end = .;
63 64
64 . = ALIGN(4096); 65 . = ALIGN(PAGE_SIZE);
65 .data.page_aligned : { *(.data.idt) } 66 .data.page_aligned : { *(.data.idt) }
66 67
67 . = ALIGN(32); 68 . = ALIGN(32);
@@ -78,7 +79,7 @@ SECTIONS
78 .data.init_task : { *(.data.init_task) } 79 .data.init_task : { *(.data.init_task) }
79 80
80 /* might get freed after init */ 81 /* might get freed after init */
81 . = ALIGN(4096); 82 . = ALIGN(PAGE_SIZE);
82 .smp_locks : AT(ADDR(.smp_locks) - LOAD_OFFSET) { 83 .smp_locks : AT(ADDR(.smp_locks) - LOAD_OFFSET) {
83 __smp_locks = .; 84 __smp_locks = .;
84 *(.smp_locks) 85 *(.smp_locks)
@@ -86,7 +87,7 @@ SECTIONS
86 } 87 }
87 88
88 /* will be freed after init */ 89 /* will be freed after init */
89 . = ALIGN(4096); /* Init code and data */ 90 . = ALIGN(PAGE_SIZE); /* Init code and data */
90 __init_begin = .; 91 __init_begin = .;
91 .init.text : { 92 .init.text : {
92 _sinittext = .; 93 _sinittext = .;
@@ -120,17 +121,14 @@ SECTIONS
120 .exit.data : { *(.exit.data) } 121 .exit.data : { *(.exit.data) }
121 122
122#ifdef CONFIG_BLK_DEV_INITRD 123#ifdef CONFIG_BLK_DEV_INITRD
123 . = ALIGN(4096); 124 . = ALIGN(PAGE_SIZE);
124 __initramfs_start = .; 125 __initramfs_start = .;
125 .init.ramfs : { *(.init.ramfs) } 126 .init.ramfs : { *(.init.ramfs) }
126 __initramfs_end = .; 127 __initramfs_end = .;
127#endif 128#endif
128 129
129 . = ALIGN(32); 130 PERCPU(32)
130 __per_cpu_start = .; 131 . = ALIGN(PAGE_SIZE);
131 .data.percpu : { *(.data.percpu) }
132 __per_cpu_end = .;
133 . = ALIGN(4096);
134 __init_end = .; 132 __init_end = .;
135 /* freed after init ends here */ 133 /* freed after init ends here */
136 134
@@ -145,7 +143,7 @@ SECTIONS
145 _end = . ; 143 _end = . ;
146 144
147 /* This is where the kernel creates the early boot page tables */ 145 /* This is where the kernel creates the early boot page tables */
148 . = ALIGN(4096); 146 . = ALIGN(PAGE_SIZE);
149 pg0 = .; 147 pg0 = .;
150 148
151 /* Sections to be discarded */ 149 /* Sections to be discarded */
diff --git a/arch/mn10300/mm/misalignment.c b/arch/mn10300/mm/misalignment.c
index 32aa89dc3848..94c4a4358065 100644
--- a/arch/mn10300/mm/misalignment.c
+++ b/arch/mn10300/mm/misalignment.c
@@ -37,26 +37,22 @@
37#include <asm/asm-offsets.h> 37#include <asm/asm-offsets.h>
38 38
39#if 0 39#if 0
40#define kdebug(FMT, ...) printk(KERN_DEBUG FMT, ##__VA_ARGS__) 40#define kdebug(FMT, ...) printk(KERN_DEBUG "MISALIGN: "FMT"\n", ##__VA_ARGS__)
41#else 41#else
42#define kdebug(FMT, ...) do {} while (0) 42#define kdebug(FMT, ...) do {} while (0)
43#endif 43#endif
44 44
45static int misalignment_addr(unsigned long *registers, unsigned params, 45static int misalignment_addr(unsigned long *registers, unsigned long sp,
46 unsigned opcode, unsigned disp, 46 unsigned params, unsigned opcode,
47 void **_address, unsigned long **_postinc); 47 unsigned long disp,
48 void **_address, unsigned long **_postinc,
49 unsigned long *_inc);
48 50
49static int misalignment_reg(unsigned long *registers, unsigned params, 51static int misalignment_reg(unsigned long *registers, unsigned params,
50 unsigned opcode, unsigned disp, 52 unsigned opcode, unsigned long disp,
51 unsigned long **_register); 53 unsigned long **_register);
52 54
53static inline unsigned int_log2(unsigned x) 55static void misalignment_MOV_Lcc(struct pt_regs *regs, uint32_t opcode);
54{
55 unsigned y;
56 asm("bsch %1,%0" : "=r"(y) : "r"(x), "0"(0));
57 return y;
58}
59#define log2(x) int_log2(x)
60 56
61static const unsigned Dreg_index[] = { 57static const unsigned Dreg_index[] = {
62 REG_D0 >> 2, REG_D1 >> 2, REG_D2 >> 2, REG_D3 >> 2 58 REG_D0 >> 2, REG_D1 >> 2, REG_D2 >> 2, REG_D3 >> 2
@@ -86,9 +82,10 @@ enum format_id {
86 FMT_D7, 82 FMT_D7,
87 FMT_D8, 83 FMT_D8,
88 FMT_D9, 84 FMT_D9,
85 FMT_D10,
89}; 86};
90 87
91struct { 88static const struct {
92 u_int8_t opsz, dispsz; 89 u_int8_t opsz, dispsz;
93} format_tbl[16] = { 90} format_tbl[16] = {
94 [FMT_S0] = { 8, 0 }, 91 [FMT_S0] = { 8, 0 },
@@ -103,6 +100,7 @@ struct {
103 [FMT_D7] = { 24, 8 }, 100 [FMT_D7] = { 24, 8 },
104 [FMT_D8] = { 24, 24 }, 101 [FMT_D8] = { 24, 24 },
105 [FMT_D9] = { 24, 32 }, 102 [FMT_D9] = { 24, 32 },
103 [FMT_D10] = { 32, 0 },
106}; 104};
107 105
108enum value_id { 106enum value_id {
@@ -128,9 +126,14 @@ enum value_id {
128 SD24, /* 24-bit signed displacement */ 126 SD24, /* 24-bit signed displacement */
129 SIMM4_2, /* 4-bit signed displacement in opcode bits 4-7 */ 127 SIMM4_2, /* 4-bit signed displacement in opcode bits 4-7 */
130 SIMM8, /* 8-bit signed immediate */ 128 SIMM8, /* 8-bit signed immediate */
129 IMM8, /* 8-bit unsigned immediate */
130 IMM16, /* 16-bit unsigned immediate */
131 IMM24, /* 24-bit unsigned immediate */ 131 IMM24, /* 24-bit unsigned immediate */
132 IMM32, /* 32-bit unsigned immediate */ 132 IMM32, /* 32-bit unsigned immediate */
133 IMM32_HIGH8, /* 32-bit unsigned immediate, high 8-bits in opcode */ 133 IMM32_HIGH8, /* 32-bit unsigned immediate, LSB in opcode */
134
135 IMM32_MEM, /* 32-bit unsigned displacement */
136 IMM32_HIGH8_MEM, /* 32-bit unsigned displacement, LSB in opcode */
134 137
135 DN0 = DM0, 138 DN0 = DM0,
136 DN1 = DM1, 139 DN1 = DM1,
@@ -149,7 +152,7 @@ enum value_id {
149}; 152};
150 153
151struct mn10300_opcode { 154struct mn10300_opcode {
152 const char *name; 155 const char name[8];
153 u_int32_t opcode; 156 u_int32_t opcode;
154 u_int32_t opmask; 157 u_int32_t opmask;
155 unsigned exclusion; 158 unsigned exclusion;
@@ -185,6 +188,10 @@ struct mn10300_opcode {
185 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 188 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
186*/ 189*/
187static const struct mn10300_opcode mn10300_opcodes[] = { 190static const struct mn10300_opcode mn10300_opcodes[] = {
191{ "mov", 0x4200, 0xf300, 0, FMT_S1, 0, {DM1, MEM2(IMM8, SP)}},
192{ "mov", 0x4300, 0xf300, 0, FMT_S1, 0, {AM1, MEM2(IMM8, SP)}},
193{ "mov", 0x5800, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), DN0}},
194{ "mov", 0x5c00, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), AN0}},
188{ "mov", 0x60, 0xf0, 0, FMT_S0, 0, {DM1, MEM(AN0)}}, 195{ "mov", 0x60, 0xf0, 0, FMT_S0, 0, {DM1, MEM(AN0)}},
189{ "mov", 0x70, 0xf0, 0, FMT_S0, 0, {MEM(AM0), DN1}}, 196{ "mov", 0x70, 0xf0, 0, FMT_S0, 0, {MEM(AM0), DN1}},
190{ "mov", 0xf000, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), AN1}}, 197{ "mov", 0xf000, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), AN1}},
@@ -197,8 +204,6 @@ static const struct mn10300_opcode mn10300_opcodes[] = {
197{ "mov", 0xf81000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}}, 204{ "mov", 0xf81000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}},
198{ "mov", 0xf82000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8,AM0), AN1}}, 205{ "mov", 0xf82000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8,AM0), AN1}},
199{ "mov", 0xf83000, 0xfff000, 0, FMT_D1, 0, {AM1, MEM2(SD8, AN0)}}, 206{ "mov", 0xf83000, 0xfff000, 0, FMT_D1, 0, {AM1, MEM2(SD8, AN0)}},
200{ "mov", 0xf8f000, 0xfffc00, 0, FMT_D1, AM33, {MEM2(SD8, AM0), SP}},
201{ "mov", 0xf8f400, 0xfffc00, 0, FMT_D1, AM33, {SP, MEM2(SD8, AN0)}},
202{ "mov", 0xf90a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}}, 207{ "mov", 0xf90a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}},
203{ "mov", 0xf91a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}}, 208{ "mov", 0xf91a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}},
204{ "mov", 0xf96a00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}}, 209{ "mov", 0xf96a00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}},
@@ -207,24 +212,46 @@ static const struct mn10300_opcode mn10300_opcodes[] = {
207{ "mov", 0xfa100000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}}, 212{ "mov", 0xfa100000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}},
208{ "mov", 0xfa200000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), AN1}}, 213{ "mov", 0xfa200000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), AN1}},
209{ "mov", 0xfa300000, 0xfff00000, 0, FMT_D2, 0, {AM1, MEM2(SD16, AN0)}}, 214{ "mov", 0xfa300000, 0xfff00000, 0, FMT_D2, 0, {AM1, MEM2(SD16, AN0)}},
215{ "mov", 0xfa900000, 0xfff30000, 0, FMT_D2, 0, {AM1, MEM2(IMM16, SP)}},
216{ "mov", 0xfa910000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}},
217{ "mov", 0xfab00000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), AN0}},
218{ "mov", 0xfab40000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}},
210{ "mov", 0xfb0a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}}, 219{ "mov", 0xfb0a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
211{ "mov", 0xfb1a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}}, 220{ "mov", 0xfb1a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
212{ "mov", 0xfb6a0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}}, 221{ "mov", 0xfb6a0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}},
213{ "mov", 0xfb7a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}}, 222{ "mov", 0xfb7a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}},
223{ "mov", 0xfb8a0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}},
214{ "mov", 0xfb8e0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}}, 224{ "mov", 0xfb8e0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
225{ "mov", 0xfb9a0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}},
215{ "mov", 0xfb9e0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}}, 226{ "mov", 0xfb9e0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
216{ "mov", 0xfc000000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}}, 227{ "mov", 0xfc000000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}},
217{ "mov", 0xfc100000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}}, 228{ "mov", 0xfc100000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}},
218{ "mov", 0xfc200000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), AN1}}, 229{ "mov", 0xfc200000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), AN1}},
219{ "mov", 0xfc300000, 0xfff00000, 0, FMT_D4, 0, {AM1, MEM2(IMM32,AN0)}}, 230{ "mov", 0xfc300000, 0xfff00000, 0, FMT_D4, 0, {AM1, MEM2(IMM32,AN0)}},
231{ "mov", 0xfc800000, 0xfff30000, 0, FMT_D4, 0, {AM1, MEM(IMM32_MEM)}},
232{ "mov", 0xfc810000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}},
233{ "mov", 0xfc900000, 0xfff30000, 0, FMT_D4, 0, {AM1, MEM2(IMM32, SP)}},
234{ "mov", 0xfc910000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}},
235{ "mov", 0xfca00000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), AN0}},
236{ "mov", 0xfca40000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}},
237{ "mov", 0xfcb00000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), AN0}},
238{ "mov", 0xfcb40000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}},
220{ "mov", 0xfd0a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}}, 239{ "mov", 0xfd0a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
221{ "mov", 0xfd1a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}}, 240{ "mov", 0xfd1a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
222{ "mov", 0xfd6a0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}}, 241{ "mov", 0xfd6a0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}},
223{ "mov", 0xfd7a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}}, 242{ "mov", 0xfd7a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}},
243{ "mov", 0xfd8a0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}},
244{ "mov", 0xfd9a0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}},
224{ "mov", 0xfe0a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}}, 245{ "mov", 0xfe0a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}},
246{ "mov", 0xfe0a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}},
247{ "mov", 0xfe0e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}},
248{ "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
225{ "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}}, 249{ "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
250{ "mov", 0xfe1e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}},
226{ "mov", 0xfe6a0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}}, 251{ "mov", 0xfe6a0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}},
227{ "mov", 0xfe7a0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}}, 252{ "mov", 0xfe7a0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
253{ "mov", 0xfe8a0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}},
254{ "mov", 0xfe9a0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}},
228 255
229{ "movhu", 0xf060, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), DN1}}, 256{ "movhu", 0xf060, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), DN1}},
230{ "movhu", 0xf070, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}}, 257{ "movhu", 0xf070, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}},
@@ -232,29 +259,58 @@ static const struct mn10300_opcode mn10300_opcodes[] = {
232{ "movhu", 0xf4c0, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}}, 259{ "movhu", 0xf4c0, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
233{ "movhu", 0xf86000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}}, 260{ "movhu", 0xf86000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
234{ "movhu", 0xf87000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}}, 261{ "movhu", 0xf87000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}},
262{ "movhu", 0xf89300, 0xfff300, 0, FMT_D1, 0, {DM1, MEM2(IMM8, SP)}},
263{ "movhu", 0xf8bc00, 0xfffc00, 0, FMT_D1, 0, {MEM2(IMM8, SP), DN0}},
235{ "movhu", 0xf94a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}}, 264{ "movhu", 0xf94a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}},
236{ "movhu", 0xf95a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}}, 265{ "movhu", 0xf95a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}},
237{ "movhu", 0xf9ea00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}}, 266{ "movhu", 0xf9ea00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}},
238{ "movhu", 0xf9fa00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}}, 267{ "movhu", 0xf9fa00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}},
239{ "movhu", 0xfa600000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}}, 268{ "movhu", 0xfa600000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
240{ "movhu", 0xfa700000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}}, 269{ "movhu", 0xfa700000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}},
270{ "movhu", 0xfa930000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}},
271{ "movhu", 0xfabc0000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}},
241{ "movhu", 0xfb4a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}}, 272{ "movhu", 0xfb4a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
242{ "movhu", 0xfb5a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}}, 273{ "movhu", 0xfb5a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
274{ "movhu", 0xfbca0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}},
243{ "movhu", 0xfbce0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}}, 275{ "movhu", 0xfbce0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
276{ "movhu", 0xfbda0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}},
244{ "movhu", 0xfbde0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}}, 277{ "movhu", 0xfbde0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
245{ "movhu", 0xfbea0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}}, 278{ "movhu", 0xfbea0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}},
246{ "movhu", 0xfbfa0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}}, 279{ "movhu", 0xfbfa0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}},
247{ "movhu", 0xfc600000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}}, 280{ "movhu", 0xfc600000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}},
248{ "movhu", 0xfc700000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}}, 281{ "movhu", 0xfc700000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}},
282{ "movhu", 0xfc830000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}},
283{ "movhu", 0xfc930000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}},
284{ "movhu", 0xfcac0000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}},
285{ "movhu", 0xfcbc0000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}},
249{ "movhu", 0xfd4a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}}, 286{ "movhu", 0xfd4a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
250{ "movhu", 0xfd5a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}}, 287{ "movhu", 0xfd5a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
288{ "movhu", 0xfdca0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}},
289{ "movhu", 0xfdda0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}},
251{ "movhu", 0xfdea0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}}, 290{ "movhu", 0xfdea0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}},
252{ "movhu", 0xfdfa0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}}, 291{ "movhu", 0xfdfa0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}},
253{ "movhu", 0xfe4a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}}, 292{ "movhu", 0xfe4a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}},
293{ "movhu", 0xfe4e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}},
254{ "movhu", 0xfe5a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}}, 294{ "movhu", 0xfe5a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
295{ "movhu", 0xfe5e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}},
296{ "movhu", 0xfeca0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}},
297{ "movhu", 0xfeda0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}},
255{ "movhu", 0xfeea0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}}, 298{ "movhu", 0xfeea0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}},
256{ "movhu", 0xfefa0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}}, 299{ "movhu", 0xfefa0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
257{ 0, 0, 0, 0, 0, 0, {0}}, 300
301{ "mov_llt", 0xf7e00000, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
302{ "mov_lgt", 0xf7e00001, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
303{ "mov_lge", 0xf7e00002, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
304{ "mov_lle", 0xf7e00003, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
305{ "mov_lcs", 0xf7e00004, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
306{ "mov_lhi", 0xf7e00005, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
307{ "mov_lcc", 0xf7e00006, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
308{ "mov_lls", 0xf7e00007, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
309{ "mov_leq", 0xf7e00008, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
310{ "mov_lne", 0xf7e00009, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
311{ "mov_lra", 0xf7e0000a, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
312
313{ "", 0, 0, 0, 0, 0, {0}},
258}; 314};
259 315
260/* 316/*
@@ -265,18 +321,21 @@ asmlinkage void misalignment(struct pt_regs *regs, enum exception_code code)
265 const struct exception_table_entry *fixup; 321 const struct exception_table_entry *fixup;
266 const struct mn10300_opcode *pop; 322 const struct mn10300_opcode *pop;
267 unsigned long *registers = (unsigned long *) regs; 323 unsigned long *registers = (unsigned long *) regs;
268 unsigned long data, *store, *postinc; 324 unsigned long data, *store, *postinc, disp, inc, sp;
269 mm_segment_t seg; 325 mm_segment_t seg;
270 siginfo_t info; 326 siginfo_t info;
271 uint32_t opcode, disp, noc, xo, xm; 327 uint32_t opcode, noc, xo, xm;
272 uint8_t *pc, byte; 328 uint8_t *pc, byte, datasz;
273 void *address; 329 void *address;
274 unsigned tmp, npop; 330 unsigned tmp, npop, dispsz, loop;
331
332 /* we don't fix up userspace misalignment faults */
333 if (user_mode(regs))
334 goto bus_error;
275 335
276 kdebug("MISALIGN at %lx\n", regs->pc); 336 sp = (unsigned long) regs + sizeof(*regs);
277 337
278 if (in_interrupt()) 338 kdebug("==>misalignment({pc=%lx,sp=%lx})", regs->pc, sp);
279 die("Misalignment trap in interrupt context", regs, code);
280 339
281 if (regs->epsw & EPSW_IE) 340 if (regs->epsw & EPSW_IE)
282 asm volatile("or %0,epsw" : : "i"(EPSW_IE)); 341 asm volatile("or %0,epsw" : : "i"(EPSW_IE));
@@ -294,8 +353,8 @@ asmlinkage void misalignment(struct pt_regs *regs, enum exception_code code)
294 opcode = byte; 353 opcode = byte;
295 noc = 8; 354 noc = 8;
296 355
297 for (pop = mn10300_opcodes; pop->name; pop++) { 356 for (pop = mn10300_opcodes; pop->name[0]; pop++) {
298 npop = log2(pop->opcode | pop->opmask); 357 npop = ilog2(pop->opcode | pop->opmask);
299 if (npop <= 0 || npop > 31) 358 if (npop <= 0 || npop > 31)
300 continue; 359 continue;
301 npop = (npop + 8) & ~7; 360 npop = (npop + 8) & ~7;
@@ -328,15 +387,15 @@ asmlinkage void misalignment(struct pt_regs *regs, enum exception_code code)
328 } 387 }
329 388
330 /* didn't manage to find a fixup */ 389 /* didn't manage to find a fixup */
331 if (!user_mode(regs)) 390 printk(KERN_CRIT "MISALIGN: %lx: unsupported instruction %x\n",
332 printk(KERN_CRIT "MISALIGN: %lx: unsupported instruction %x\n", 391 regs->pc, opcode);
333 regs->pc, opcode);
334 392
335failed: 393failed:
336 set_fs(seg); 394 set_fs(seg);
337 if (die_if_no_fixup("misalignment error", regs, code)) 395 if (die_if_no_fixup("misalignment error", regs, code))
338 return; 396 return;
339 397
398bus_error:
340 info.si_signo = SIGBUS; 399 info.si_signo = SIGBUS;
341 info.si_errno = 0; 400 info.si_errno = 0;
342 info.si_code = BUS_ADRALN; 401 info.si_code = BUS_ADRALN;
@@ -346,31 +405,27 @@ failed:
346 405
347 /* error reading opcodes */ 406 /* error reading opcodes */
348fetch_error: 407fetch_error:
349 if (!user_mode(regs)) 408 printk(KERN_CRIT
350 printk(KERN_CRIT 409 "MISALIGN: %p: fault whilst reading instruction data\n",
351 "MISALIGN: %p: fault whilst reading instruction data\n", 410 pc);
352 pc);
353 goto failed; 411 goto failed;
354 412
355bad_addr_mode: 413bad_addr_mode:
356 if (!user_mode(regs)) 414 printk(KERN_CRIT
357 printk(KERN_CRIT 415 "MISALIGN: %lx: unsupported addressing mode %x\n",
358 "MISALIGN: %lx: unsupported addressing mode %x\n", 416 regs->pc, opcode);
359 regs->pc, opcode);
360 goto failed; 417 goto failed;
361 418
362bad_reg_mode: 419bad_reg_mode:
363 if (!user_mode(regs)) 420 printk(KERN_CRIT
364 printk(KERN_CRIT 421 "MISALIGN: %lx: unsupported register mode %x\n",
365 "MISALIGN: %lx: unsupported register mode %x\n", 422 regs->pc, opcode);
366 regs->pc, opcode);
367 goto failed; 423 goto failed;
368 424
369unsupported_instruction: 425unsupported_instruction:
370 if (!user_mode(regs)) 426 printk(KERN_CRIT
371 printk(KERN_CRIT 427 "MISALIGN: %lx: unsupported instruction %x (%s)\n",
372 "MISALIGN: %lx: unsupported instruction %x (%s)\n", 428 regs->pc, opcode, pop->name);
373 regs->pc, opcode, pop->name);
374 goto failed; 429 goto failed;
375 430
376transfer_failed: 431transfer_failed:
@@ -391,7 +446,7 @@ transfer_failed:
391 446
392 /* we matched the opcode */ 447 /* we matched the opcode */
393found_opcode: 448found_opcode:
394 kdebug("MISALIGN: %lx: %x==%x { %x, %x }\n", 449 kdebug("%lx: %x==%x { %x, %x }",
395 regs->pc, opcode, pop->opcode, pop->params[0], pop->params[1]); 450 regs->pc, opcode, pop->opcode, pop->params[0], pop->params[1]);
396 451
397 tmp = format_tbl[pop->format].opsz; 452 tmp = format_tbl[pop->format].opsz;
@@ -406,106 +461,108 @@ found_opcode:
406 461
407 /* grab the extra displacement (note it's LSB first) */ 462 /* grab the extra displacement (note it's LSB first) */
408 disp = 0; 463 disp = 0;
409 tmp = format_tbl[pop->format].dispsz >> 3; 464 dispsz = format_tbl[pop->format].dispsz;
410 while (tmp > 0) { 465 for (loop = 0; loop < dispsz; loop += 8) {
411 tmp--;
412 disp <<= 8;
413
414 pc++; 466 pc++;
415 if (__get_user(byte, pc) != 0) 467 if (__get_user(byte, pc) != 0)
416 goto fetch_error; 468 goto fetch_error;
417 disp |= byte; 469 disp |= byte << loop;
470 kdebug("{%p} disp[%02x]=%02x", pc, loop, byte);
418 } 471 }
419 472
473 kdebug("disp=%lx", disp);
474
420 set_fs(KERNEL_XDS); 475 set_fs(KERNEL_XDS);
421 if (fixup || regs->epsw & EPSW_nSL) 476 if (fixup)
422 set_fs(seg); 477 set_fs(seg);
423 478
424 tmp = (pop->params[0] ^ pop->params[1]) & 0x80000000; 479 tmp = (pop->params[0] ^ pop->params[1]) & 0x80000000;
425 if (!tmp) { 480 if (!tmp) {
426 if (!user_mode(regs)) 481 printk(KERN_CRIT
427 printk(KERN_CRIT 482 "MISALIGN: %lx: insn not move to/from memory %x\n",
428 "MISALIGN: %lx:" 483 regs->pc, opcode);
429 " insn not move to/from memory %x\n",
430 regs->pc, opcode);
431 goto failed; 484 goto failed;
432 } 485 }
433 486
487 /* determine the data transfer size of the move */
488 if (pop->name[3] == 0 || /* "mov" */
489 pop->name[4] == 'l') /* mov_lcc */
490 inc = datasz = 4;
491 else if (pop->name[3] == 'h') /* movhu */
492 inc = datasz = 2;
493 else
494 goto unsupported_instruction;
495
434 if (pop->params[0] & 0x80000000) { 496 if (pop->params[0] & 0x80000000) {
435 /* move memory to register */ 497 /* move memory to register */
436 if (!misalignment_addr(registers, pop->params[0], opcode, disp, 498 if (!misalignment_addr(registers, sp,
437 &address, &postinc)) 499 pop->params[0], opcode, disp,
500 &address, &postinc, &inc))
438 goto bad_addr_mode; 501 goto bad_addr_mode;
439 502
440 if (!misalignment_reg(registers, pop->params[1], opcode, disp, 503 if (!misalignment_reg(registers, pop->params[1], opcode, disp,
441 &store)) 504 &store))
442 goto bad_reg_mode; 505 goto bad_reg_mode;
443 506
444 if (strcmp(pop->name, "mov") == 0) { 507 kdebug("mov%u (%p),DARn", datasz, address);
445 kdebug("FIXUP: mov (%p),DARn\n", address); 508 if (copy_from_user(&data, (void *) address, datasz) != 0)
446 if (copy_from_user(&data, (void *) address, 4) != 0) 509 goto transfer_failed;
447 goto transfer_failed; 510 if (pop->params[0] & 0x1000000) {
448 if (pop->params[0] & 0x1000000) 511 kdebug("inc=%lx", inc);
449 *postinc += 4; 512 *postinc += inc;
450 } else if (strcmp(pop->name, "movhu") == 0) {
451 kdebug("FIXUP: movhu (%p),DARn\n", address);
452 data = 0;
453 if (copy_from_user(&data, (void *) address, 2) != 0)
454 goto transfer_failed;
455 if (pop->params[0] & 0x1000000)
456 *postinc += 2;
457 } else {
458 goto unsupported_instruction;
459 } 513 }
460 514
461 *store = data; 515 *store = data;
516 kdebug("loaded %lx", data);
462 } else { 517 } else {
463 /* move register to memory */ 518 /* move register to memory */
464 if (!misalignment_reg(registers, pop->params[0], opcode, disp, 519 if (!misalignment_reg(registers, pop->params[0], opcode, disp,
465 &store)) 520 &store))
466 goto bad_reg_mode; 521 goto bad_reg_mode;
467 522
468 if (!misalignment_addr(registers, pop->params[1], opcode, disp, 523 if (!misalignment_addr(registers, sp,
469 &address, &postinc)) 524 pop->params[1], opcode, disp,
525 &address, &postinc, &inc))
470 goto bad_addr_mode; 526 goto bad_addr_mode;
471 527
472 data = *store; 528 data = *store;
473 529
474 if (strcmp(pop->name, "mov") == 0) { 530 kdebug("mov%u %lx,(%p)", datasz, data, address);
475 kdebug("FIXUP: mov %lx,(%p)\n", data, address); 531 if (copy_to_user((void *) address, &data, datasz) != 0)
476 if (copy_to_user((void *) address, &data, 4) != 0) 532 goto transfer_failed;
477 goto transfer_failed; 533 if (pop->params[1] & 0x1000000)
478 if (pop->params[1] & 0x1000000) 534 *postinc += inc;
479 *postinc += 4;
480 } else if (strcmp(pop->name, "movhu") == 0) {
481 kdebug("FIXUP: movhu %hx,(%p)\n",
482 (uint16_t) data, address);
483 if (copy_to_user((void *) address, &data, 2) != 0)
484 goto transfer_failed;
485 if (pop->params[1] & 0x1000000)
486 *postinc += 2;
487 } else {
488 goto unsupported_instruction;
489 }
490 } 535 }
491 536
492 tmp = format_tbl[pop->format].opsz + format_tbl[pop->format].dispsz; 537 tmp = format_tbl[pop->format].opsz + format_tbl[pop->format].dispsz;
493 regs->pc += tmp >> 3; 538 regs->pc += tmp >> 3;
494 539
540 /* handle MOV_Lcc, which are currently the only FMT_D10 insns that
541 * access memory */
542 if (pop->format == FMT_D10)
543 misalignment_MOV_Lcc(regs, opcode);
544
495 set_fs(seg); 545 set_fs(seg);
496 return;
497} 546}
498 547
499/* 548/*
500 * determine the address that was being accessed 549 * determine the address that was being accessed
501 */ 550 */
502static int misalignment_addr(unsigned long *registers, unsigned params, 551static int misalignment_addr(unsigned long *registers, unsigned long sp,
503 unsigned opcode, unsigned disp, 552 unsigned params, unsigned opcode,
504 void **_address, unsigned long **_postinc) 553 unsigned long disp,
554 void **_address, unsigned long **_postinc,
555 unsigned long *_inc)
505{ 556{
506 unsigned long *postinc = NULL, address = 0, tmp; 557 unsigned long *postinc = NULL, address = 0, tmp;
507 558
508 params &= 0x7fffffff; 559 if (!(params & 0x1000000)) {
560 kdebug("noinc");
561 *_inc = 0;
562 _inc = NULL;
563 }
564
565 params &= 0x00ffffff;
509 566
510 do { 567 do {
511 switch (params & 0xff) { 568 switch (params & 0xff) {
@@ -514,11 +571,11 @@ static int misalignment_addr(unsigned long *registers, unsigned params,
514 address += *postinc; 571 address += *postinc;
515 break; 572 break;
516 case DM1: 573 case DM1:
517 postinc = &registers[Dreg_index[opcode >> 2 & 0x0c]]; 574 postinc = &registers[Dreg_index[opcode >> 2 & 0x03]];
518 address += *postinc; 575 address += *postinc;
519 break; 576 break;
520 case DM2: 577 case DM2:
521 postinc = &registers[Dreg_index[opcode >> 4 & 0x30]]; 578 postinc = &registers[Dreg_index[opcode >> 4 & 0x03]];
522 address += *postinc; 579 address += *postinc;
523 break; 580 break;
524 case AM0: 581 case AM0:
@@ -526,11 +583,11 @@ static int misalignment_addr(unsigned long *registers, unsigned params,
526 address += *postinc; 583 address += *postinc;
527 break; 584 break;
528 case AM1: 585 case AM1:
529 postinc = &registers[Areg_index[opcode >> 2 & 0x0c]]; 586 postinc = &registers[Areg_index[opcode >> 2 & 0x03]];
530 address += *postinc; 587 address += *postinc;
531 break; 588 break;
532 case AM2: 589 case AM2:
533 postinc = &registers[Areg_index[opcode >> 4 & 0x30]]; 590 postinc = &registers[Areg_index[opcode >> 4 & 0x03]];
534 address += *postinc; 591 address += *postinc;
535 break; 592 break;
536 case RM0: 593 case RM0:
@@ -561,33 +618,53 @@ static int misalignment_addr(unsigned long *registers, unsigned params,
561 postinc = &registers[Rreg_index[disp >> 4 & 0x0f]]; 618 postinc = &registers[Rreg_index[disp >> 4 & 0x0f]];
562 address += *postinc; 619 address += *postinc;
563 break; 620 break;
621 case SP:
622 address += sp;
623 break;
564 624
625 /* displacements are either to be added to the address
626 * before use, or, in the case of post-inc addressing,
627 * to be added into the base register after use */
565 case SD8: 628 case SD8:
566 case SIMM8: 629 case SIMM8:
567 address += (int32_t) (int8_t) (disp & 0xff); 630 disp = (long) (int8_t) (disp & 0xff);
568 break; 631 goto displace_or_inc;
569 case SD16: 632 case SD16:
570 address += (int32_t) (int16_t) (disp & 0xffff); 633 disp = (long) (int16_t) (disp & 0xffff);
571 break; 634 goto displace_or_inc;
572 case SD24: 635 case SD24:
573 tmp = disp << 8; 636 tmp = disp << 8;
574 asm("asr 8,%0" : "=r"(tmp) : "0"(tmp)); 637 asm("asr 8,%0" : "=r"(tmp) : "0"(tmp));
575 address += tmp; 638 disp = (long) tmp;
576 break; 639 goto displace_or_inc;
577 case SIMM4_2: 640 case SIMM4_2:
578 tmp = opcode >> 4 & 0x0f; 641 tmp = opcode >> 4 & 0x0f;
579 tmp <<= 28; 642 tmp <<= 28;
580 asm("asr 28,%0" : "=r"(tmp) : "0"(tmp)); 643 asm("asr 28,%0" : "=r"(tmp) : "0"(tmp));
581 address += tmp; 644 disp = (long) tmp;
582 break; 645 goto displace_or_inc;
646 case IMM8:
647 disp &= 0x000000ff;
648 goto displace_or_inc;
649 case IMM16:
650 disp &= 0x0000ffff;
651 goto displace_or_inc;
583 case IMM24: 652 case IMM24:
584 address += disp & 0x00ffffff; 653 disp &= 0x00ffffff;
585 break; 654 goto displace_or_inc;
586 case IMM32: 655 case IMM32:
656 case IMM32_MEM:
587 case IMM32_HIGH8: 657 case IMM32_HIGH8:
588 address += disp; 658 case IMM32_HIGH8_MEM:
659 displace_or_inc:
660 kdebug("%s %lx", _inc ? "incr" : "disp", disp);
661 if (!_inc)
662 address += disp;
663 else
664 *_inc = disp;
589 break; 665 break;
590 default: 666 default:
667 BUG();
591 return 0; 668 return 0;
592 } 669 }
593 } while ((params >>= 8)); 670 } while ((params >>= 8));
@@ -601,7 +678,7 @@ static int misalignment_addr(unsigned long *registers, unsigned params,
601 * determine the register that is acting as source/dest 678 * determine the register that is acting as source/dest
602 */ 679 */
603static int misalignment_reg(unsigned long *registers, unsigned params, 680static int misalignment_reg(unsigned long *registers, unsigned params,
604 unsigned opcode, unsigned disp, 681 unsigned opcode, unsigned long disp,
605 unsigned long **_register) 682 unsigned long **_register)
606{ 683{
607 params &= 0x7fffffff; 684 params &= 0x7fffffff;
@@ -654,8 +731,239 @@ static int misalignment_reg(unsigned long *registers, unsigned params,
654 break; 731 break;
655 732
656 default: 733 default:
734 BUG();
657 return 0; 735 return 0;
658 } 736 }
659 737
660 return 1; 738 return 1;
661} 739}
740
741/*
742 * handle the conditional loop part of the move-and-loop instructions
743 */
744static void misalignment_MOV_Lcc(struct pt_regs *regs, uint32_t opcode)
745{
746 unsigned long epsw = regs->epsw;
747 unsigned long NxorV;
748
749 kdebug("MOV_Lcc %x [flags=%lx]", opcode, epsw & 0xf);
750
751 /* calculate N^V and shift onto the same bit position as Z */
752 NxorV = ((epsw >> 3) ^ epsw >> 1) & 1;
753
754 switch (opcode & 0xf) {
755 case 0x0: /* MOV_LLT: N^V */
756 if (NxorV)
757 goto take_the_loop;
758 return;
759 case 0x1: /* MOV_LGT: ~(Z or (N^V))*/
760 if (!((epsw & EPSW_FLAG_Z) | NxorV))
761 goto take_the_loop;
762 return;
763 case 0x2: /* MOV_LGE: ~(N^V) */
764 if (!NxorV)
765 goto take_the_loop;
766 return;
767 case 0x3: /* MOV_LLE: Z or (N^V) */
768 if ((epsw & EPSW_FLAG_Z) | NxorV)
769 goto take_the_loop;
770 return;
771
772 case 0x4: /* MOV_LCS: C */
773 if (epsw & EPSW_FLAG_C)
774 goto take_the_loop;
775 return;
776 case 0x5: /* MOV_LHI: ~(C or Z) */
777 if (!(epsw & (EPSW_FLAG_C | EPSW_FLAG_Z)))
778 goto take_the_loop;
779 return;
780 case 0x6: /* MOV_LCC: ~C */
781 if (!(epsw & EPSW_FLAG_C))
782 goto take_the_loop;
783 return;
784 case 0x7: /* MOV_LLS: C or Z */
785 if (epsw & (EPSW_FLAG_C | EPSW_FLAG_Z))
786 goto take_the_loop;
787 return;
788
789 case 0x8: /* MOV_LEQ: Z */
790 if (epsw & EPSW_FLAG_Z)
791 goto take_the_loop;
792 return;
793 case 0x9: /* MOV_LNE: ~Z */
794 if (!(epsw & EPSW_FLAG_Z))
795 goto take_the_loop;
796 return;
797 case 0xa: /* MOV_LRA: always */
798 goto take_the_loop;
799
800 default:
801 BUG();
802 }
803
804take_the_loop:
805 /* wind the PC back to just after the SETLB insn */
806 kdebug("loop LAR=%lx", regs->lar);
807 regs->pc = regs->lar - 4;
808}
809
810/*
811 * misalignment handler tests
812 */
813#ifdef CONFIG_TEST_MISALIGNMENT_HANDLER
814static u8 __initdata testbuf[512] __attribute__((aligned(16))) = {
815 [257] = 0x11,
816 [258] = 0x22,
817 [259] = 0x33,
818 [260] = 0x44,
819};
820
821#define ASSERTCMP(X, OP, Y) \
822do { \
823 if (unlikely(!((X) OP (Y)))) { \
824 printk(KERN_ERR "\n"); \
825 printk(KERN_ERR "MISALIGN: Assertion failed at line %u\n", \
826 __LINE__); \
827 printk(KERN_ERR "0x%lx " #OP " 0x%lx is false\n", \
828 (unsigned long)(X), (unsigned long)(Y)); \
829 BUG(); \
830 } \
831} while(0)
832
833static int __init test_misalignment(void)
834{
835 register void *r asm("e0");
836 register u32 y asm("e1");
837 void *p = testbuf, *q;
838 u32 tmp, tmp2, x;
839
840 printk(KERN_NOTICE "==>test_misalignment() [testbuf=%p]\n", p);
841 p++;
842
843 printk(KERN_NOTICE "___ MOV (Am),Dn ___\n");
844 q = p + 256;
845 asm volatile("mov (%0),%1" : "+a"(q), "=d"(x));
846 ASSERTCMP(q, ==, p + 256);
847 ASSERTCMP(x, ==, 0x44332211);
848
849 printk(KERN_NOTICE "___ MOV (256,Am),Dn ___\n");
850 q = p;
851 asm volatile("mov (256,%0),%1" : "+a"(q), "=d"(x));
852 ASSERTCMP(q, ==, p);
853 ASSERTCMP(x, ==, 0x44332211);
854
855 printk(KERN_NOTICE "___ MOV (Di,Am),Dn ___\n");
856 tmp = 256;
857 q = p;
858 asm volatile("mov (%2,%0),%1" : "+a"(q), "=d"(x), "+d"(tmp));
859 ASSERTCMP(q, ==, p);
860 ASSERTCMP(x, ==, 0x44332211);
861 ASSERTCMP(tmp, ==, 256);
862
863 printk(KERN_NOTICE "___ MOV (256,Rm),Rn ___\n");
864 r = p;
865 asm volatile("mov (256,%0),%1" : "+r"(r), "=r"(y));
866 ASSERTCMP(r, ==, p);
867 ASSERTCMP(y, ==, 0x44332211);
868
869 printk(KERN_NOTICE "___ MOV (Rm+),Rn ___\n");
870 r = p + 256;
871 asm volatile("mov (%0+),%1" : "+r"(r), "=r"(y));
872 ASSERTCMP(r, ==, p + 256 + 4);
873 ASSERTCMP(y, ==, 0x44332211);
874
875 printk(KERN_NOTICE "___ MOV (Rm+,8),Rn ___\n");
876 r = p + 256;
877 asm volatile("mov (%0+,8),%1" : "+r"(r), "=r"(y));
878 ASSERTCMP(r, ==, p + 256 + 8);
879 ASSERTCMP(y, ==, 0x44332211);
880
881 printk(KERN_NOTICE "___ MOV (7,SP),Rn ___\n");
882 asm volatile(
883 "add -16,sp \n"
884 "mov +0x11,%0 \n"
885 "movbu %0,(7,sp) \n"
886 "mov +0x22,%0 \n"
887 "movbu %0,(8,sp) \n"
888 "mov +0x33,%0 \n"
889 "movbu %0,(9,sp) \n"
890 "mov +0x44,%0 \n"
891 "movbu %0,(10,sp) \n"
892 "mov (7,sp),%1 \n"
893 "add +16,sp \n"
894 : "+a"(q), "=d"(x));
895 ASSERTCMP(x, ==, 0x44332211);
896
897 printk(KERN_NOTICE "___ MOV (259,SP),Rn ___\n");
898 asm volatile(
899 "add -264,sp \n"
900 "mov +0x11,%0 \n"
901 "movbu %0,(259,sp) \n"
902 "mov +0x22,%0 \n"
903 "movbu %0,(260,sp) \n"
904 "mov +0x33,%0 \n"
905 "movbu %0,(261,sp) \n"
906 "mov +0x55,%0 \n"
907 "movbu %0,(262,sp) \n"
908 "mov (259,sp),%1 \n"
909 "add +264,sp \n"
910 : "+d"(tmp), "=d"(x));
911 ASSERTCMP(x, ==, 0x55332211);
912
913 printk(KERN_NOTICE "___ MOV (260,SP),Rn ___\n");
914 asm volatile(
915 "add -264,sp \n"
916 "mov +0x11,%0 \n"
917 "movbu %0,(260,sp) \n"
918 "mov +0x22,%0 \n"
919 "movbu %0,(261,sp) \n"
920 "mov +0x33,%0 \n"
921 "movbu %0,(262,sp) \n"
922 "mov +0x55,%0 \n"
923 "movbu %0,(263,sp) \n"
924 "mov (260,sp),%1 \n"
925 "add +264,sp \n"
926 : "+d"(tmp), "=d"(x));
927 ASSERTCMP(x, ==, 0x55332211);
928
929
930 printk(KERN_NOTICE "___ MOV_LNE ___\n");
931 tmp = 1;
932 tmp2 = 2;
933 q = p + 256;
934 asm volatile(
935 "setlb \n"
936 "mov %2,%3 \n"
937 "mov %1,%2 \n"
938 "cmp +0,%1 \n"
939 "mov_lne (%0+,4),%1"
940 : "+r"(q), "+d"(tmp), "+d"(tmp2), "=d"(x)
941 :
942 : "cc");
943 ASSERTCMP(q, ==, p + 256 + 12);
944 ASSERTCMP(x, ==, 0x44332211);
945
946 printk(KERN_NOTICE "___ MOV in SETLB ___\n");
947 tmp = 1;
948 tmp2 = 2;
949 q = p + 256;
950 asm volatile(
951 "setlb \n"
952 "mov %1,%3 \n"
953 "mov (%0+),%1 \n"
954 "cmp +0,%1 \n"
955 "lne "
956 : "+a"(q), "+d"(tmp), "+d"(tmp2), "=d"(x)
957 :
958 : "cc");
959
960 ASSERTCMP(q, ==, p + 256 + 8);
961 ASSERTCMP(x, ==, 0x44332211);
962
963 printk(KERN_NOTICE "<==test_misalignment()\n");
964 return 0;
965}
966
967arch_initcall(test_misalignment);
968
969#endif /* CONFIG_TEST_MISALIGNMENT_HANDLER */
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-14 02:47:57 -0500