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-rw-r--r--arch/mn10300/proc-mn2ws0050/include/proc/cache.h48
-rw-r--r--arch/mn10300/proc-mn2ws0050/include/proc/clock.h20
-rw-r--r--arch/mn10300/proc-mn2ws0050/include/proc/dmactl-regs.h103
-rw-r--r--arch/mn10300/proc-mn2ws0050/include/proc/intctl-regs.h29
-rw-r--r--arch/mn10300/proc-mn2ws0050/include/proc/irq.h49
-rw-r--r--arch/mn10300/proc-mn2ws0050/include/proc/nand-regs.h120
-rw-r--r--arch/mn10300/proc-mn2ws0050/include/proc/proc.h18
-rw-r--r--arch/mn10300/proc-mn2ws0050/include/proc/smp-regs.h51
8 files changed, 438 insertions, 0 deletions
diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/cache.h b/arch/mn10300/proc-mn2ws0050/include/proc/cache.h
new file mode 100644
index 000000000000..cafd7b5b55b4
--- /dev/null
+++ b/arch/mn10300/proc-mn2ws0050/include/proc/cache.h
@@ -0,0 +1,48 @@
1/* Cache specification
2 *
3 * Copyright (C) 2005 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 *
6 * Modified by Matsushita Electric Industrial Co., Ltd.
7 * Modifications:
8 * 13-Nov-2006 MEI Add L1_CACHE_SHIFT_MAX definition.
9 * 29-Jul-2008 MEI Add define for MN10300_HAS_AREAPURGE_REG.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
15 */
16#ifndef _ASM_PROC_CACHE_H
17#define _ASM_PROC_CACHE_H
18
19/*
20 * L1 cache
21 */
22#define L1_CACHE_NWAYS 4 /* number of ways in caches */
23#define L1_CACHE_NENTRIES 128 /* number of entries in each way */
24#define L1_CACHE_BYTES 32 /* bytes per entry */
25#define L1_CACHE_SHIFT 5 /* shift for bytes per entry */
26#define L1_CACHE_WAYDISP 0x1000 /* distance from one way to the next */
27
28#define L1_CACHE_TAG_VALID 0x00000001 /* cache tag valid bit */
29#define L1_CACHE_TAG_DIRTY 0x00000008 /* data cache tag dirty bit */
30#define L1_CACHE_TAG_ENTRY 0x00000fe0 /* cache tag entry address mask */
31#define L1_CACHE_TAG_ADDRESS 0xfffff000 /* cache tag line address mask */
32
33/*
34 * specification of the interval between interrupt checking intervals whilst
35 * managing the cache with the interrupts disabled
36 */
37#define MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL 4
38
39/*
40 * The size of range at which it becomes more economical to just flush the
41 * whole cache rather than trying to flush the specified range.
42 */
43#define MN10300_DCACHE_FLUSH_BORDER \
44 +(L1_CACHE_NWAYS * L1_CACHE_NENTRIES * L1_CACHE_BYTES)
45#define MN10300_DCACHE_FLUSH_INV_BORDER \
46 +(L1_CACHE_NWAYS * L1_CACHE_NENTRIES * L1_CACHE_BYTES)
47
48#endif /* _ASM_PROC_CACHE_H */
diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/clock.h b/arch/mn10300/proc-mn2ws0050/include/proc/clock.h
new file mode 100644
index 000000000000..fe4c0a4a53a2
--- /dev/null
+++ b/arch/mn10300/proc-mn2ws0050/include/proc/clock.h
@@ -0,0 +1,20 @@
1/* clock.h: proc-specific clocks
2 *
3 * Copyright (C) 2002 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 *
6 * Modified by Matsushita Electric Industrial Co., Ltd.
7 * Modifications:
8 * 23-Feb-2007 MEI Delete define for watchdog timer.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15#ifndef _ASM_PROC_CLOCK_H
16#define _ASM_PROC_CLOCK_H
17
18#include <unit/clock.h>
19
20#endif /* _ASM_PROC_CLOCK_H */
diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/dmactl-regs.h b/arch/mn10300/proc-mn2ws0050/include/proc/dmactl-regs.h
new file mode 100644
index 000000000000..4c4319e241d1
--- /dev/null
+++ b/arch/mn10300/proc-mn2ws0050/include/proc/dmactl-regs.h
@@ -0,0 +1,103 @@
1/* MN2WS0050 on-board DMA controller registers
2 *
3 * Copyright (C) 2002 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 */
10
11#ifndef _ASM_PROC_DMACTL_REGS_H
12#define _ASM_PROC_DMACTL_REGS_H
13
14#include <asm/cpu-regs.h>
15
16#ifdef __KERNEL__
17
18/* DMA registers */
19#define DMxCTR(N) __SYSREG(0xd4005000+(N*0x100), u32) /* control reg */
20#define DMxCTR_BG 0x0000001f /* transfer request source */
21#define DMxCTR_BG_SOFT 0x00000000 /* - software source */
22#define DMxCTR_BG_SC0TX 0x00000002 /* - serial port 0 transmission */
23#define DMxCTR_BG_SC0RX 0x00000003 /* - serial port 0 reception */
24#define DMxCTR_BG_SC1TX 0x00000004 /* - serial port 1 transmission */
25#define DMxCTR_BG_SC1RX 0x00000005 /* - serial port 1 reception */
26#define DMxCTR_BG_SC2TX 0x00000006 /* - serial port 2 transmission */
27#define DMxCTR_BG_SC2RX 0x00000007 /* - serial port 2 reception */
28#define DMxCTR_BG_TM0UFLOW 0x00000008 /* - timer 0 underflow */
29#define DMxCTR_BG_TM1UFLOW 0x00000009 /* - timer 1 underflow */
30#define DMxCTR_BG_TM2UFLOW 0x0000000a /* - timer 2 underflow */
31#define DMxCTR_BG_TM3UFLOW 0x0000000b /* - timer 3 underflow */
32#define DMxCTR_BG_TM6ACMPCAP 0x0000000c /* - timer 6A compare/capture */
33#define DMxCTR_BG_RYBY 0x0000000d /* - NAND Flash RY/BY request source */
34#define DMxCTR_BG_RMC 0x0000000e /* - remote controller output */
35#define DMxCTR_BG_XIRQ12 0x00000011 /* - XIRQ12 pin interrupt source */
36#define DMxCTR_BG_XIRQ13 0x00000012 /* - XIRQ13 pin interrupt source */
37#define DMxCTR_BG_TCK 0x00000014 /* - tick timer underflow */
38#define DMxCTR_BG_SC4TX 0x00000019 /* - serial port4 transmission */
39#define DMxCTR_BG_SC4RX 0x0000001a /* - serial port4 reception */
40#define DMxCTR_BG_SC5TX 0x0000001b /* - serial port5 transmission */
41#define DMxCTR_BG_SC5RX 0x0000001c /* - serial port5 reception */
42#define DMxCTR_BG_SC6TX 0x0000001d /* - serial port6 transmission */
43#define DMxCTR_BG_SC6RX 0x0000001e /* - serial port6 reception */
44#define DMxCTR_BG_TMSUFLOW 0x0000001f /* - timestamp timer underflow */
45#define DMxCTR_SAM 0x00000060 /* DMA transfer src addr mode */
46#define DMxCTR_SAM_INCR 0x00000000 /* - increment */
47#define DMxCTR_SAM_DECR 0x00000020 /* - decrement */
48#define DMxCTR_SAM_FIXED 0x00000040 /* - fixed */
49#define DMxCTR_DAM 0x00000300 /* DMA transfer dest addr mode */
50#define DMxCTR_DAM_INCR 0x00000000 /* - increment */
51#define DMxCTR_DAM_DECR 0x00000100 /* - decrement */
52#define DMxCTR_DAM_FIXED 0x00000200 /* - fixed */
53#define DMxCTR_UT 0x00006000 /* DMA transfer unit */
54#define DMxCTR_UT_1 0x00000000 /* - 1 byte */
55#define DMxCTR_UT_2 0x00002000 /* - 2 byte */
56#define DMxCTR_UT_4 0x00004000 /* - 4 byte */
57#define DMxCTR_UT_16 0x00006000 /* - 16 byte */
58#define DMxCTR_RRE 0x00008000 /* DMA round robin enable */
59#define DMxCTR_TEN 0x00010000 /* DMA channel transfer enable */
60#define DMxCTR_RQM 0x00060000 /* external request input source mode */
61#define DMxCTR_RQM_FALLEDGE 0x00000000 /* - falling edge */
62#define DMxCTR_RQM_RISEEDGE 0x00020000 /* - rising edge */
63#define DMxCTR_RQM_LOLEVEL 0x00040000 /* - low level */
64#define DMxCTR_RQM_HILEVEL 0x00060000 /* - high level */
65#define DMxCTR_RQF 0x01000000 /* DMA transfer request flag */
66#define DMxCTR_PERR 0x40000000 /* DMA transfer parameter error flag */
67#define DMxCTR_XEND 0x80000000 /* DMA transfer end flag */
68
69#define DMxSRC(N) __SYSREG(0xd4005004+(N*0x100), u32) /* control reg */
70
71#define DMxDST(N) __SYSREG(0xd4005008+(N*0x100), u32) /* source addr reg */
72
73#define DMxSIZ(N) __SYSREG(0xd400500c+(N*0x100), u32) /* dest addr reg */
74#define DMxSIZ_CT 0x000fffff /* number of bytes to transfer */
75
76#define DMxCYC(N) __SYSREG(0xd4005010+(N*0x100), u32) /* intermittent size reg */
77#define DMxCYC_CYC 0x000000ff /* number of interrmittent transfers -1 */
78
79#define DM0IRQ 16 /* DMA channel 0 complete IRQ */
80#define DM1IRQ 17 /* DMA channel 1 complete IRQ */
81#define DM2IRQ 18 /* DMA channel 2 complete IRQ */
82#define DM3IRQ 19 /* DMA channel 3 complete IRQ */
83
84#define DM0ICR GxICR(DM0IRQ) /* DMA channel 0 complete intr ctrl reg */
85#define DM1ICR GxICR(DM0IR1) /* DMA channel 1 complete intr ctrl reg */
86#define DM2ICR GxICR(DM0IR2) /* DMA channel 2 complete intr ctrl reg */
87#define DM3ICR GxICR(DM0IR3) /* DMA channel 3 complete intr ctrl reg */
88
89#ifndef __ASSEMBLY__
90
91struct mn10300_dmactl_regs {
92 u32 ctr;
93 const void *src;
94 void *dst;
95 u32 siz;
96 u32 cyc;
97} __attribute__((aligned(0x100)));
98
99#endif /* __ASSEMBLY__ */
100
101#endif /* __KERNEL__ */
102
103#endif /* _ASM_PROC_DMACTL_REGS_H */
diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/intctl-regs.h b/arch/mn10300/proc-mn2ws0050/include/proc/intctl-regs.h
new file mode 100644
index 000000000000..a1e977273d19
--- /dev/null
+++ b/arch/mn10300/proc-mn2ws0050/include/proc/intctl-regs.h
@@ -0,0 +1,29 @@
1#ifndef _ASM_PROC_INTCTL_REGS_H
2#define _ASM_PROC_INTCTL_REGS_H
3
4#ifndef _ASM_INTCTL_REGS_H
5# error "please don't include this file directly"
6#endif
7
8/* intr acceptance group reg */
9#define IAGR __SYSREG(0xd4000100, u16)
10
11/* group number register */
12#define IAGR_GN 0x003fc
13
14#define __GET_XIRQ_TRIGGER(X, Z) (((Z) >> ((X) * 2)) & 3)
15
16#define __SET_XIRQ_TRIGGER(X, Y, Z) \
17({ \
18 typeof(Z) x = (Z); \
19 x &= ~(3 << ((X) * 2)); \
20 x |= ((Y) & 3) << ((X) * 2); \
21 (Z) = x; \
22})
23
24/* external pin intr spec reg */
25#define EXTMD0 __SYSREG(0xd4000200, u32)
26#define GET_XIRQ_TRIGGER(X) __GET_XIRQ_TRIGGER(X, EXTMD0)
27#define SET_XIRQ_TRIGGER(X, Y) __SET_XIRQ_TRIGGER(X, Y, EXTMD0)
28
29#endif /* _ASM_PROC_INTCTL_REGS_H */
diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/irq.h b/arch/mn10300/proc-mn2ws0050/include/proc/irq.h
new file mode 100644
index 000000000000..37777a85ab6f
--- /dev/null
+++ b/arch/mn10300/proc-mn2ws0050/include/proc/irq.h
@@ -0,0 +1,49 @@
1/* MN2WS0050 on-board interrupt controller registers
2 *
3 * Copyright (C) 2002 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 *
6 * Modified by Matsushita Electric Industrial Co., Ltd.
7 * Modifications:
8 * 13-Nov-2006 MEI Define extended IRQ number for SMP support.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15
16#ifndef _PROC_IRQ_H
17#define _PROC_IRQ_H
18
19#ifdef __KERNEL__
20
21#define GxICR_NUM_IRQS 163
22#ifdef CONFIG_SMP
23#define GxICR_NUM_EXT_IRQS 197
24#endif /* CONFIG_SMP */
25
26#define GxICR_NUM_XIRQS 16
27
28#define XIRQ0 34
29#define XIRQ1 35
30#define XIRQ2 36
31#define XIRQ3 37
32#define XIRQ4 38
33#define XIRQ5 39
34#define XIRQ6 40
35#define XIRQ7 41
36#define XIRQ8 42
37#define XIRQ9 43
38#define XIRQ10 44
39#define XIRQ11 45
40#define XIRQ12 46
41#define XIRQ13 47
42#define XIRQ14 48
43#define XIRQ15 49
44
45#define XIRQ2IRQ(num) (XIRQ0 + num)
46
47#endif /* __KERNEL__ */
48
49#endif /* _PROC_IRQ_H */
diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/nand-regs.h b/arch/mn10300/proc-mn2ws0050/include/proc/nand-regs.h
new file mode 100644
index 000000000000..84448f3828b3
--- /dev/null
+++ b/arch/mn10300/proc-mn2ws0050/include/proc/nand-regs.h
@@ -0,0 +1,120 @@
1/* NAND flash interface register definitions
2 *
3 * Copyright (C) 2008-2009 Panasonic Corporation
4 * All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef _PROC_NAND_REGS_H_
17#define _PROC_NAND_REGS_H_
18
19/* command register */
20#define FCOMMAND_0 __SYSREG(0xd8f00000, u8) /* fcommand[24:31] */
21#define FCOMMAND_1 __SYSREG(0xd8f00001, u8) /* fcommand[16:23] */
22#define FCOMMAND_2 __SYSREG(0xd8f00002, u8) /* fcommand[8:15] */
23#define FCOMMAND_3 __SYSREG(0xd8f00003, u8) /* fcommand[0:7] */
24
25/* for dma 16 byte trans, use FCOMMAND2 register */
26#define FCOMMAND2_0 __SYSREG(0xd8f00110, u8) /* fcommand2[24:31] */
27#define FCOMMAND2_1 __SYSREG(0xd8f00111, u8) /* fcommand2[16:23] */
28#define FCOMMAND2_2 __SYSREG(0xd8f00112, u8) /* fcommand2[8:15] */
29#define FCOMMAND2_3 __SYSREG(0xd8f00113, u8) /* fcommand2[0:7] */
30
31#define FCOMMAND_FIEN 0x80 /* nand flash I/F enable */
32#define FCOMMAND_BW_8BIT 0x00 /* 8bit bus width */
33#define FCOMMAND_BW_16BIT 0x40 /* 16bit bus width */
34#define FCOMMAND_BLOCKSZ_SMALL 0x00 /* small block */
35#define FCOMMAND_BLOCKSZ_LARGE 0x20 /* large block */
36#define FCOMMAND_DMASTART 0x10 /* dma start */
37#define FCOMMAND_RYBY 0x08 /* ready/busy flag */
38#define FCOMMAND_RYBYINTMSK 0x04 /* mask ready/busy interrupt */
39#define FCOMMAND_XFWP 0x02 /* write protect enable */
40#define FCOMMAND_XFCE 0x01 /* flash device disable */
41#define FCOMMAND_SEQKILL 0x10 /* stop seq-read */
42#define FCOMMAND_ANUM 0x07 /* address cycle */
43#define FCOMMAND_ANUM_NONE 0x00 /* address cycle none */
44#define FCOMMAND_ANUM_1CYC 0x01 /* address cycle 1cycle */
45#define FCOMMAND_ANUM_2CYC 0x02 /* address cycle 2cycle */
46#define FCOMMAND_ANUM_3CYC 0x03 /* address cycle 3cycle */
47#define FCOMMAND_ANUM_4CYC 0x04 /* address cycle 4cycle */
48#define FCOMMAND_ANUM_5CYC 0x05 /* address cycle 5cycle */
49#define FCOMMAND_FCMD_READ0 0x00 /* read1 command */
50#define FCOMMAND_FCMD_SEQIN 0x80 /* page program 1st command */
51#define FCOMMAND_FCMD_PAGEPROG 0x10 /* page program 2nd command */
52#define FCOMMAND_FCMD_RESET 0xff /* reset command */
53#define FCOMMAND_FCMD_ERASE1 0x60 /* erase 1st command */
54#define FCOMMAND_FCMD_ERASE2 0xd0 /* erase 2nd command */
55#define FCOMMAND_FCMD_STATUS 0x70 /* read status command */
56#define FCOMMAND_FCMD_READID 0x90 /* read id command */
57#define FCOMMAND_FCMD_READOOB 0x50 /* read3 command */
58/* address register */
59#define FADD __SYSREG(0xd8f00004, u32)
60/* address register 2 */
61#define FADD2 __SYSREG(0xd8f00008, u32)
62/* error judgement register */
63#define FJUDGE __SYSREG(0xd8f0000c, u32)
64#define FJUDGE_NOERR 0x0 /* no error */
65#define FJUDGE_1BITERR 0x1 /* 1bit error in data area */
66#define FJUDGE_PARITYERR 0x2 /* parity error */
67#define FJUDGE_UNCORRECTABLE 0x3 /* uncorrectable error */
68#define FJUDGE_ERRJDG_MSK 0x3 /* mask of judgement result */
69/* 1st ECC store register */
70#define FECC11 __SYSREG(0xd8f00010, u32)
71/* 2nd ECC store register */
72#define FECC12 __SYSREG(0xd8f00014, u32)
73/* 3rd ECC store register */
74#define FECC21 __SYSREG(0xd8f00018, u32)
75/* 4th ECC store register */
76#define FECC22 __SYSREG(0xd8f0001c, u32)
77/* 5th ECC store register */
78#define FECC31 __SYSREG(0xd8f00020, u32)
79/* 6th ECC store register */
80#define FECC32 __SYSREG(0xd8f00024, u32)
81/* 7th ECC store register */
82#define FECC41 __SYSREG(0xd8f00028, u32)
83/* 8th ECC store register */
84#define FECC42 __SYSREG(0xd8f0002c, u32)
85/* data register */
86#define FDATA __SYSREG(0xd8f00030, u32)
87/* access pulse register */
88#define FPWS __SYSREG(0xd8f00100, u32)
89#define FPWS_PWS1W_2CLK 0x00000000 /* write pulse width 1clock */
90#define FPWS_PWS1W_3CLK 0x01000000 /* write pulse width 2clock */
91#define FPWS_PWS1W_4CLK 0x02000000 /* write pulse width 4clock */
92#define FPWS_PWS1W_5CLK 0x03000000 /* write pulse width 5clock */
93#define FPWS_PWS1W_6CLK 0x04000000 /* write pulse width 6clock */
94#define FPWS_PWS1W_7CLK 0x05000000 /* write pulse width 7clock */
95#define FPWS_PWS1W_8CLK 0x06000000 /* write pulse width 8clock */
96#define FPWS_PWS1R_3CLK 0x00010000 /* read pulse width 3clock */
97#define FPWS_PWS1R_4CLK 0x00020000 /* read pulse width 4clock */
98#define FPWS_PWS1R_5CLK 0x00030000 /* read pulse width 5clock */
99#define FPWS_PWS1R_6CLK 0x00040000 /* read pulse width 6clock */
100#define FPWS_PWS1R_7CLK 0x00050000 /* read pulse width 7clock */
101#define FPWS_PWS1R_8CLK 0x00060000 /* read pulse width 8clock */
102#define FPWS_PWS2W_2CLK 0x00000100 /* write pulse interval 2clock */
103#define FPWS_PWS2W_3CLK 0x00000200 /* write pulse interval 3clock */
104#define FPWS_PWS2W_4CLK 0x00000300 /* write pulse interval 4clock */
105#define FPWS_PWS2W_5CLK 0x00000400 /* write pulse interval 5clock */
106#define FPWS_PWS2W_6CLK 0x00000500 /* write pulse interval 6clock */
107#define FPWS_PWS2R_2CLK 0x00000001 /* read pulse interval 2clock */
108#define FPWS_PWS2R_3CLK 0x00000002 /* read pulse interval 3clock */
109#define FPWS_PWS2R_4CLK 0x00000003 /* read pulse interval 4clock */
110#define FPWS_PWS2R_5CLK 0x00000004 /* read pulse interval 5clock */
111#define FPWS_PWS2R_6CLK 0x00000005 /* read pulse interval 6clock */
112/* command register 2 */
113#define FCOMMAND2 __SYSREG(0xd8f00110, u32)
114/* transfer frequency register */
115#define FNUM __SYSREG(0xd8f00114, u32)
116#define FSDATA_ADDR 0xd8f00400
117/* active data register */
118#define FSDATA __SYSREG(FSDATA_ADDR, u32)
119
120#endif /* _PROC_NAND_REGS_H_ */
diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/proc.h b/arch/mn10300/proc-mn2ws0050/include/proc/proc.h
new file mode 100644
index 000000000000..90d5cadd05bd
--- /dev/null
+++ b/arch/mn10300/proc-mn2ws0050/include/proc/proc.h
@@ -0,0 +1,18 @@
1/* proc.h: MN2WS0050 processor description
2 *
3 * Copyright (C) 2002 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#ifndef _ASM_PROC_PROC_H
13#define _ASM_PROC_PROC_H
14
15#define PROCESSOR_VENDOR_NAME "Panasonic"
16#define PROCESSOR_MODEL_NAME "mn2ws0050"
17
18#endif /* _ASM_PROC_PROC_H */
diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/smp-regs.h b/arch/mn10300/proc-mn2ws0050/include/proc/smp-regs.h
new file mode 100644
index 000000000000..22f277fbb4de
--- /dev/null
+++ b/arch/mn10300/proc-mn2ws0050/include/proc/smp-regs.h
@@ -0,0 +1,51 @@
1/* MN10300/AM33v2 Microcontroller SMP registers
2 *
3 * Copyright (C) 2006 Matsushita Electric Industrial Co., Ltd.
4 * All Rights Reserved.
5 * Created:
6 * 13-Nov-2006 MEI Add extended cache and atomic operation register
7 * for SMP support.
8 * 23-Feb-2007 MEI Add define for gdbstub SMP.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15
16#ifndef _ASM_PROC_SMP_REGS_H
17#define _ASM_PROC_SMP_REGS_H
18
19#ifdef __KERNEL__
20
21#ifndef __ASSEMBLY__
22#include <linux/types.h>
23#endif
24#include <asm/cpu-regs.h>
25
26/*
27 * Reference to the interrupt controllers of other CPUs
28 */
29#define CROSS_ICR_CPU_SHIFT 16
30
31#define CROSS_GxICR(X, CPU) __SYSREG(0xc4000000 + (X) * 4 + \
32 ((X) >= 64 && (X) < 192) * 0xf00 + ((CPU) << CROSS_ICR_CPU_SHIFT), u16)
33#define CROSS_GxICR_u8(X, CPU) __SYSREG(0xc4000000 + (X) * 4 + \
34 (((X) >= 64) && ((X) < 192)) * 0xf00 + ((CPU) << CROSS_ICR_CPU_SHIFT), u8)
35
36/* CPU ID register */
37#define CPUID __SYSREGC(0xc0000054, u32)
38#define CPUID_MASK 0x00000007 /* CPU ID mask */
39
40/* extended cache control register */
41#define ECHCTR __SYSREG(0xc0000c20, u32)
42#define ECHCTR_IBCM 0x00000001 /* instruction cache broad cast mask */
43#define ECHCTR_DBCM 0x00000002 /* data cache broad cast mask */
44#define ECHCTR_ISPM 0x00000004 /* instruction cache snoop mask */
45#define ECHCTR_DSPM 0x00000008 /* data cache snoop mask */
46
47#define NMIAGR __SYSREG(0xd400013c, u16)
48#define NMIAGR_GN 0x03fc
49
50#endif /* __KERNEL__ */
51#endif /* _ASM_PROC_SMP_REGS_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 08:37:42 -0500