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-rw-r--r--arch/mn10300/include/asm/exceptions.h2
-rw-r--r--arch/mn10300/include/asm/frame.inc36
-rw-r--r--arch/mn10300/include/asm/hardirq.h2
-rw-r--r--arch/mn10300/include/asm/intctl-regs.h37
-rw-r--r--arch/mn10300/include/asm/irq.h4
-rw-r--r--arch/mn10300/include/asm/irqflags.h26
-rw-r--r--arch/mn10300/include/asm/pgtable.h19
-rw-r--r--arch/mn10300/include/asm/processor.h47
-rw-r--r--arch/mn10300/include/asm/ptrace.h15
-rw-r--r--arch/mn10300/include/asm/reset-regs.h2
-rw-r--r--arch/mn10300/include/asm/rtc.h11
-rw-r--r--arch/mn10300/include/asm/rwlock.h125
-rw-r--r--arch/mn10300/include/asm/serial-regs.h51
-rw-r--r--arch/mn10300/include/asm/serial.h8
-rw-r--r--arch/mn10300/include/asm/smp.h102
-rw-r--r--arch/mn10300/include/asm/spinlock.h179
-rw-r--r--arch/mn10300/include/asm/spinlock_types.h20
-rw-r--r--arch/mn10300/include/asm/system.h11
-rw-r--r--arch/mn10300/include/asm/timer-regs.h191
-rw-r--r--arch/mn10300/include/asm/timex.h3
-rw-r--r--arch/mn10300/include/asm/uaccess.h2
21 files changed, 793 insertions, 100 deletions
diff --git a/arch/mn10300/include/asm/exceptions.h b/arch/mn10300/include/asm/exceptions.h
index 7d8080bc6590..ca3e20508c77 100644
--- a/arch/mn10300/include/asm/exceptions.h
+++ b/arch/mn10300/include/asm/exceptions.h
@@ -114,6 +114,8 @@ extern void die(const char *, struct pt_regs *, enum exception_code)
114 114
115extern int die_if_no_fixup(const char *, struct pt_regs *, enum exception_code); 115extern int die_if_no_fixup(const char *, struct pt_regs *, enum exception_code);
116 116
117#define NUM2EXCEP_IRQ_LEVEL(num) (EXCEP_IRQ_LEVEL0 + (num) * 8)
118
117#endif /* __ASSEMBLY__ */ 119#endif /* __ASSEMBLY__ */
118 120
119#endif /* _ASM_EXCEPTIONS_H */ 121#endif /* _ASM_EXCEPTIONS_H */
diff --git a/arch/mn10300/include/asm/frame.inc b/arch/mn10300/include/asm/frame.inc
index 5b1949bdf039..406060e5e1c0 100644
--- a/arch/mn10300/include/asm/frame.inc
+++ b/arch/mn10300/include/asm/frame.inc
@@ -18,6 +18,9 @@
18#ifndef __ASM_OFFSETS_H__ 18#ifndef __ASM_OFFSETS_H__
19#include <asm/asm-offsets.h> 19#include <asm/asm-offsets.h>
20#endif 20#endif
21#ifdef CONFIG_SMP
22#include <proc/smp-regs.h>
23#endif
21 24
22#define pi break 25#define pi break
23 26
@@ -37,9 +40,25 @@
37 movm [d2,d3,a2,a3,exreg0,exreg1,exother],(sp) 40 movm [d2,d3,a2,a3,exreg0,exreg1,exother],(sp)
38 mov sp,fp # FRAME pointer in A3 41 mov sp,fp # FRAME pointer in A3
39 add -12,sp # allow for calls to be made 42 add -12,sp # allow for calls to be made
43#ifdef CONFIG_SMP
44#ifdef CONFIG_PREEMPT /* FIXME */
45 mov epsw,d2
46 and ~EPSW_IE,epsw
47#endif
48 mov (CPUID),a0
49 add a0,a0
50 add a0,a0
51 mov (___frame,a0),a1
52 mov a1,(REG_NEXT,fp)
53 mov fp,(___frame,a0)
54#ifdef CONFIG_PREEMPT /* FIXME */
55 mov d2,epsw
56#endif
57#else /* CONFIG_SMP */
40 mov (__frame),a1 58 mov (__frame),a1
41 mov a1,(REG_NEXT,fp) 59 mov a1,(REG_NEXT,fp)
42 mov fp,(__frame) 60 mov fp,(__frame)
61#endif /* CONFIG_SMP */
43 62
44 and ~EPSW_FE,epsw # disable the FPU inside the kernel 63 and ~EPSW_FE,epsw # disable the FPU inside the kernel
45 64
@@ -57,10 +76,27 @@
57.macro RESTORE_ALL 76.macro RESTORE_ALL
58 # peel back the stack to the calling frame 77 # peel back the stack to the calling frame
59 # - this permits execve() to discard extra frames due to kernel syscalls 78 # - this permits execve() to discard extra frames due to kernel syscalls
79#ifdef CONFIG_SMP
80#ifdef CONFIG_PREEMPT /* FIXME */
81 mov epsw,d2
82 and ~EPSW_IE,epsw
83#endif
84 mov (CPUID),a0
85 add a0,a0
86 add a0,a0
87 mov (___frame,a0),fp
88 mov fp,sp
89 mov (REG_NEXT,fp),d0 # userspace has regs->next == 0
90 mov d0,(___frame,a0)
91#ifdef CONFIG_PREEMPT /* FIXME */
92 mov d2,epsw
93#endif
94#else /* CONFIG_SMP */
60 mov (__frame),fp 95 mov (__frame),fp
61 mov fp,sp 96 mov fp,sp
62 mov (REG_NEXT,fp),d0 # userspace has regs->next == 0 97 mov (REG_NEXT,fp),d0 # userspace has regs->next == 0
63 mov d0,(__frame) 98 mov d0,(__frame)
99#endif /* CONFIG_SMP */
64 100
65#ifndef CONFIG_MN10300_USING_JTAG 101#ifndef CONFIG_MN10300_USING_JTAG
66 mov (REG_EPSW,fp),d0 102 mov (REG_EPSW,fp),d0
diff --git a/arch/mn10300/include/asm/hardirq.h b/arch/mn10300/include/asm/hardirq.h
index 7bd9b7cc2451..0000d650b55f 100644
--- a/arch/mn10300/include/asm/hardirq.h
+++ b/arch/mn10300/include/asm/hardirq.h
@@ -19,8 +19,10 @@
19/* assembly code in softirq.h is sensitive to the offsets of these fields */ 19/* assembly code in softirq.h is sensitive to the offsets of these fields */
20typedef struct { 20typedef struct {
21 unsigned int __softirq_pending; 21 unsigned int __softirq_pending;
22#ifdef CONFIG_MN10300_WD_TIMER
22 unsigned int __nmi_count; /* arch dependent */ 23 unsigned int __nmi_count; /* arch dependent */
23 unsigned int __irq_count; /* arch dependent */ 24 unsigned int __irq_count; /* arch dependent */
25#endif
24} ____cacheline_aligned irq_cpustat_t; 26} ____cacheline_aligned irq_cpustat_t;
25 27
26#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */ 28#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
diff --git a/arch/mn10300/include/asm/intctl-regs.h b/arch/mn10300/include/asm/intctl-regs.h
index ba544c796c5a..585b708c2bc0 100644
--- a/arch/mn10300/include/asm/intctl-regs.h
+++ b/arch/mn10300/include/asm/intctl-regs.h
@@ -15,24 +15,19 @@
15 15
16#ifdef __KERNEL__ 16#ifdef __KERNEL__
17 17
18/* interrupt controller registers */ 18/*
19#define GxICR(X) __SYSREG(0xd4000000 + (X) * 4, u16) /* group irq ctrl regs */ 19 * Interrupt controller registers
20 20 * - Registers 64-191 are at addresses offset from the main array
21#define IAGR __SYSREG(0xd4000100, u16) /* intr acceptance group reg */ 21 */
22#define IAGR_GN 0x00fc /* group number register 22#define GxICR(X) \
23 * (documentation _has_ to be wrong) 23 __SYSREG(0xd4000000 + (X) * 4 + \
24 */ 24 (((X) >= 64) && ((X) < 192)) * 0xf00, u16)
25 25
26#define EXTMD __SYSREG(0xd4000200, u16) /* external pin intr spec reg */ 26#define GxICR_u8(X) \
27#define GET_XIRQ_TRIGGER(X) ((EXTMD >> ((X) * 2)) & 3) 27 __SYSREG(0xd4000000 + (X) * 4 + \
28 (((X) >= 64) && ((X) < 192)) * 0xf00, u8)
28 29
29#define SET_XIRQ_TRIGGER(X,Y) \ 30#include <proc/intctl-regs.h>
30do { \
31 u16 x = EXTMD; \
32 x &= ~(3 << ((X) * 2)); \
33 x |= ((Y) & 3) << ((X) * 2); \
34 EXTMD = x; \
35} while (0)
36 31
37#define XIRQ_TRIGGER_LOWLEVEL 0 32#define XIRQ_TRIGGER_LOWLEVEL 0
38#define XIRQ_TRIGGER_HILEVEL 1 33#define XIRQ_TRIGGER_HILEVEL 1
@@ -59,10 +54,18 @@ do { \
59#define GxICR_LEVEL_5 0x5000 /* - level 5 */ 54#define GxICR_LEVEL_5 0x5000 /* - level 5 */
60#define GxICR_LEVEL_6 0x6000 /* - level 6 */ 55#define GxICR_LEVEL_6 0x6000 /* - level 6 */
61#define GxICR_LEVEL_SHIFT 12 56#define GxICR_LEVEL_SHIFT 12
57#define GxICR_NMI 0x8000 /* nmi request flag */
58
59#define NUM2GxICR_LEVEL(num) ((num) << GxICR_LEVEL_SHIFT)
62 60
63#ifndef __ASSEMBLY__ 61#ifndef __ASSEMBLY__
64extern void set_intr_level(int irq, u16 level); 62extern void set_intr_level(int irq, u16 level);
65extern void set_intr_postackable(int irq); 63extern void mn10300_intc_set_level(unsigned int irq, unsigned int level);
64extern void mn10300_intc_clear(unsigned int irq);
65extern void mn10300_intc_set(unsigned int irq);
66extern void mn10300_intc_enable(unsigned int irq);
67extern void mn10300_intc_disable(unsigned int irq);
68extern void mn10300_set_lateack_irq_type(int irq);
66#endif 69#endif
67 70
68/* external interrupts */ 71/* external interrupts */
diff --git a/arch/mn10300/include/asm/irq.h b/arch/mn10300/include/asm/irq.h
index 25c045d16d1c..b7b8e175b167 100644
--- a/arch/mn10300/include/asm/irq.h
+++ b/arch/mn10300/include/asm/irq.h
@@ -22,7 +22,11 @@
22#define NO_IRQ INT_MAX 22#define NO_IRQ INT_MAX
23 23
24/* hardware irq numbers */ 24/* hardware irq numbers */
25#ifdef CONFIG_SMP
26#define NR_IRQS GxICR_NUM_EXT_IRQS
27#else
25#define NR_IRQS GxICR_NUM_IRQS 28#define NR_IRQS GxICR_NUM_IRQS
29#endif
26 30
27/* external hardware irq numbers */ 31/* external hardware irq numbers */
28#define NR_XIRQS GxICR_NUM_XIRQS 32#define NR_XIRQS GxICR_NUM_XIRQS
diff --git a/arch/mn10300/include/asm/irqflags.h b/arch/mn10300/include/asm/irqflags.h
index b3ab2071354d..7a7ae12c7119 100644
--- a/arch/mn10300/include/asm/irqflags.h
+++ b/arch/mn10300/include/asm/irqflags.h
@@ -13,6 +13,9 @@
13#define _ASM_IRQFLAGS_H 13#define _ASM_IRQFLAGS_H
14 14
15#include <asm/cpu-regs.h> 15#include <asm/cpu-regs.h>
16#ifndef __ASSEMBLY__
17#include <linux/smp.h>
18#endif
16 19
17/* 20/*
18 * interrupt control 21 * interrupt control
@@ -60,11 +63,12 @@ static inline unsigned long arch_local_irq_save(void)
60/* 63/*
61 * we make sure arch_irq_enable() doesn't cause priority inversion 64 * we make sure arch_irq_enable() doesn't cause priority inversion
62 */ 65 */
63extern unsigned long __mn10300_irq_enabled_epsw; 66extern unsigned long __mn10300_irq_enabled_epsw[];
64 67
65static inline void arch_local_irq_enable(void) 68static inline void arch_local_irq_enable(void)
66{ 69{
67 unsigned long tmp; 70 unsigned long tmp;
71 int cpu = raw_smp_processor_id();
68 72
69 asm volatile( 73 asm volatile(
70 " mov epsw,%0 \n" 74 " mov epsw,%0 \n"
@@ -72,8 +76,8 @@ static inline void arch_local_irq_enable(void)
72 " or %2,%0 \n" 76 " or %2,%0 \n"
73 " mov %0,epsw \n" 77 " mov %0,epsw \n"
74 : "=&d"(tmp) 78 : "=&d"(tmp)
75 : "i"(~EPSW_IM), "r"(__mn10300_irq_enabled_epsw) 79 : "i"(~EPSW_IM), "r"(__mn10300_irq_enabled_epsw[cpu])
76 : "memory"); 80 : "memory", "cc");
77} 81}
78 82
79static inline void arch_local_irq_restore(unsigned long flags) 83static inline void arch_local_irq_restore(unsigned long flags)
@@ -105,6 +109,9 @@ static inline bool arch_irqs_disabled(void)
105 */ 109 */
106static inline void arch_safe_halt(void) 110static inline void arch_safe_halt(void)
107{ 111{
112#ifdef CONFIG_SMP
113 arch_local_irq_enable();
114#else
108 asm volatile( 115 asm volatile(
109 " or %0,epsw \n" 116 " or %0,epsw \n"
110 " nop \n" 117 " nop \n"
@@ -113,8 +120,21 @@ static inline void arch_safe_halt(void)
113 : 120 :
114 : "i"(EPSW_IE|EPSW_IM), "n"(&CPUM), "i"(CPUM_SLEEP) 121 : "i"(EPSW_IE|EPSW_IM), "n"(&CPUM), "i"(CPUM_SLEEP)
115 : "cc"); 122 : "cc");
123#endif
116} 124}
117 125
126#define __sleep_cpu() \
127do { \
128 asm volatile( \
129 " bset %1,(%0)\n" \
130 "1: btst %1,(%0)\n" \
131 " bne 1b\n" \
132 : \
133 : "i"(&CPUM), "i"(CPUM_SLEEP) \
134 : "cc" \
135 ); \
136} while (0)
137
118static inline void arch_local_cli(void) 138static inline void arch_local_cli(void)
119{ 139{
120 asm volatile( 140 asm volatile(
diff --git a/arch/mn10300/include/asm/pgtable.h b/arch/mn10300/include/asm/pgtable.h
index 05dda641af80..cd568bf5407e 100644
--- a/arch/mn10300/include/asm/pgtable.h
+++ b/arch/mn10300/include/asm/pgtable.h
@@ -90,9 +90,15 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
90 * The vmalloc() routines also leaves a hole of 4kB between each vmalloced 90 * The vmalloc() routines also leaves a hole of 4kB between each vmalloced
91 * area to catch addressing errors. 91 * area to catch addressing errors.
92 */ 92 */
93#ifndef __ASSEMBLY__
94#define VMALLOC_OFFSET (8UL * 1024 * 1024)
95#define VMALLOC_START (0x70000000UL)
96#define VMALLOC_END (0x7C000000UL)
97#else
93#define VMALLOC_OFFSET (8 * 1024 * 1024) 98#define VMALLOC_OFFSET (8 * 1024 * 1024)
94#define VMALLOC_START (0x70000000) 99#define VMALLOC_START (0x70000000)
95#define VMALLOC_END (0x7C000000) 100#define VMALLOC_END (0x7C000000)
101#endif
96 102
97#ifndef __ASSEMBLY__ 103#ifndef __ASSEMBLY__
98extern pte_t kernel_vmalloc_ptes[(VMALLOC_END - VMALLOC_START) / PAGE_SIZE]; 104extern pte_t kernel_vmalloc_ptes[(VMALLOC_END - VMALLOC_START) / PAGE_SIZE];
@@ -329,11 +335,7 @@ static inline int pte_exec_kernel(pte_t pte)
329 return 1; 335 return 1;
330} 336}
331 337
332/* 338#define PTE_FILE_MAX_BITS 30
333 * Bits 0 and 1 are taken, split up the 29 bits of offset
334 * into this range:
335 */
336#define PTE_FILE_MAX_BITS 29
337 339
338#define pte_to_pgoff(pte) (pte_val(pte) >> 2) 340#define pte_to_pgoff(pte) (pte_val(pte) >> 2)
339#define pgoff_to_pte(off) __pte((off) << 2 | _PAGE_FILE) 341#define pgoff_to_pte(off) __pte((off) << 2 | _PAGE_FILE)
@@ -379,8 +381,13 @@ static inline void ptep_mkdirty(pte_t *ptep)
379 * Macro to mark a page protection value as "uncacheable". On processors which 381 * Macro to mark a page protection value as "uncacheable". On processors which
380 * do not support it, this is a no-op. 382 * do not support it, this is a no-op.
381 */ 383 */
382#define pgprot_noncached(prot) __pgprot(pgprot_val(prot) | _PAGE_CACHE) 384#define pgprot_noncached(prot) __pgprot(pgprot_val(prot) & ~_PAGE_CACHE)
383 385
386/*
387 * Macro to mark a page protection value as "Write-Through".
388 * On processors which do not support it, this is a no-op.
389 */
390#define pgprot_through(prot) __pgprot(pgprot_val(prot) | _PAGE_CACHE_WT)
384 391
385/* 392/*
386 * Conversion functions: convert a page and protection to a page entry, 393 * Conversion functions: convert a page and protection to a page entry,
diff --git a/arch/mn10300/include/asm/processor.h b/arch/mn10300/include/asm/processor.h
index 0032fc76c8ba..75c422abcd6b 100644
--- a/arch/mn10300/include/asm/processor.h
+++ b/arch/mn10300/include/asm/processor.h
@@ -33,6 +33,8 @@ struct mm_struct;
33 __pc; \ 33 __pc; \
34}) 34})
35 35
36extern void get_mem_info(unsigned long *mem_base, unsigned long *mem_size);
37
36extern void show_registers(struct pt_regs *regs); 38extern void show_registers(struct pt_regs *regs);
37 39
38/* 40/*
@@ -43,17 +45,22 @@ extern void show_registers(struct pt_regs *regs);
43 45
44struct mn10300_cpuinfo { 46struct mn10300_cpuinfo {
45 int type; 47 int type;
46 unsigned long loops_per_sec; 48 unsigned long loops_per_jiffy;
47 char hard_math; 49 char hard_math;
48 unsigned long *pgd_quick;
49 unsigned long *pte_quick;
50 unsigned long pgtable_cache_sz;
51}; 50};
52 51
53extern struct mn10300_cpuinfo boot_cpu_data; 52extern struct mn10300_cpuinfo boot_cpu_data;
54 53
54#ifdef CONFIG_SMP
55#if CONFIG_NR_CPUS < 2 || CONFIG_NR_CPUS > 8
56# error Sorry, NR_CPUS should be 2 to 8
57#endif
58extern struct mn10300_cpuinfo cpu_data[];
59#define current_cpu_data cpu_data[smp_processor_id()]
60#else /* CONFIG_SMP */
55#define cpu_data &boot_cpu_data 61#define cpu_data &boot_cpu_data
56#define current_cpu_data boot_cpu_data 62#define current_cpu_data boot_cpu_data
63#endif /* CONFIG_SMP */
57 64
58extern void identify_cpu(struct mn10300_cpuinfo *); 65extern void identify_cpu(struct mn10300_cpuinfo *);
59extern void print_cpu_info(struct mn10300_cpuinfo *); 66extern void print_cpu_info(struct mn10300_cpuinfo *);
@@ -92,21 +99,21 @@ struct thread_struct {
92 unsigned long a3; /* kernel FP */ 99 unsigned long a3; /* kernel FP */
93 unsigned long wchan; 100 unsigned long wchan;
94 unsigned long usp; 101 unsigned long usp;
95 struct pt_regs *__frame; 102 struct pt_regs *frame;
96 unsigned long fpu_flags; 103 unsigned long fpu_flags;
97#define THREAD_USING_FPU 0x00000001 /* T if this task is using the FPU */ 104#define THREAD_USING_FPU 0x00000001 /* T if this task is using the FPU */
98#define THREAD_HAS_FPU 0x00000002 /* T if this task owns the FPU right now */ 105#define THREAD_HAS_FPU 0x00000002 /* T if this task owns the FPU right now */
99 struct fpu_state_struct fpu_state; 106 struct fpu_state_struct fpu_state;
100}; 107};
101 108
102#define INIT_THREAD \ 109#define INIT_THREAD \
103{ \ 110{ \
104 .uregs = init_uregs, \ 111 .uregs = init_uregs, \
105 .pc = 0, \ 112 .pc = 0, \
106 .sp = 0, \ 113 .sp = 0, \
107 .a3 = 0, \ 114 .a3 = 0, \
108 .wchan = 0, \ 115 .wchan = 0, \
109 .__frame = NULL, \ 116 .frame = NULL, \
110} 117}
111 118
112#define INIT_MMAP \ 119#define INIT_MMAP \
@@ -118,6 +125,19 @@ struct thread_struct {
118 * - need to discard the frame stacked by the kernel thread invoking the execve 125 * - need to discard the frame stacked by the kernel thread invoking the execve
119 * syscall (see RESTORE_ALL macro) 126 * syscall (see RESTORE_ALL macro)
120 */ 127 */
128#if defined(CONFIG_SMP) && defined(CONFIG_PREEMPT) /* FIXME */
129#define start_thread(regs, new_pc, new_sp) do { \
130 int cpu; \
131 preempt_disable(); \
132 cpu = CPUID; \
133 set_fs(USER_DS); \
134 ___frame[cpu] = current->thread.uregs; \
135 ___frame[cpu]->epsw = EPSW_nSL | EPSW_IE | EPSW_IM;\
136 ___frame[cpu]->pc = new_pc; \
137 ___frame[cpu]->sp = new_sp; \
138 preempt_enable(); \
139} while (0)
140#else /* CONFIG_SMP && CONFIG_PREEMPT */
121#define start_thread(regs, new_pc, new_sp) do { \ 141#define start_thread(regs, new_pc, new_sp) do { \
122 set_fs(USER_DS); \ 142 set_fs(USER_DS); \
123 __frame = current->thread.uregs; \ 143 __frame = current->thread.uregs; \
@@ -125,6 +145,7 @@ struct thread_struct {
125 __frame->pc = new_pc; \ 145 __frame->pc = new_pc; \
126 __frame->sp = new_sp; \ 146 __frame->sp = new_sp; \
127} while (0) 147} while (0)
148#endif /* CONFIG_SMP && CONFIG_PREEMPT */
128 149
129/* Free all resources held by a thread. */ 150/* Free all resources held by a thread. */
130extern void release_thread(struct task_struct *); 151extern void release_thread(struct task_struct *);
diff --git a/arch/mn10300/include/asm/ptrace.h b/arch/mn10300/include/asm/ptrace.h
index 7c2e911052b6..c2b77bd3064a 100644
--- a/arch/mn10300/include/asm/ptrace.h
+++ b/arch/mn10300/include/asm/ptrace.h
@@ -40,7 +40,6 @@
40#define PT_PC 26 40#define PT_PC 26
41#define NR_PTREGS 27 41#define NR_PTREGS 27
42 42
43#ifndef __ASSEMBLY__
44/* 43/*
45 * This defines the way registers are stored in the event of an exception 44 * This defines the way registers are stored in the event of an exception
46 * - the strange order is due to the MOVM instruction 45 * - the strange order is due to the MOVM instruction
@@ -75,7 +74,6 @@ struct pt_regs {
75 unsigned long epsw; 74 unsigned long epsw;
76 unsigned long pc; 75 unsigned long pc;
77}; 76};
78#endif
79 77
80/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ 78/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
81#define PTRACE_GETREGS 12 79#define PTRACE_GETREGS 12
@@ -86,12 +84,13 @@ struct pt_regs {
86/* options set using PTRACE_SETOPTIONS */ 84/* options set using PTRACE_SETOPTIONS */
87#define PTRACE_O_TRACESYSGOOD 0x00000001 85#define PTRACE_O_TRACESYSGOOD 0x00000001
88 86
89#if defined(__KERNEL__) 87#ifdef __KERNEL__
90 88
89#ifdef CONFIG_SMP
90extern struct pt_regs *___frame[]; /* current frame pointer */
91#else
91extern struct pt_regs *__frame; /* current frame pointer */ 92extern struct pt_regs *__frame; /* current frame pointer */
92 93#endif
93#if !defined(__ASSEMBLY__)
94struct task_struct;
95 94
96#define user_mode(regs) (((regs)->epsw & EPSW_nSL) == EPSW_nSL) 95#define user_mode(regs) (((regs)->epsw & EPSW_nSL) == EPSW_nSL)
97#define instruction_pointer(regs) ((regs)->pc) 96#define instruction_pointer(regs) ((regs)->pc)
@@ -100,9 +99,7 @@ extern void show_regs(struct pt_regs *);
100 99
101#define arch_has_single_step() (1) 100#define arch_has_single_step() (1)
102 101
103#endif /* !__ASSEMBLY */
104
105#define profile_pc(regs) ((regs)->pc) 102#define profile_pc(regs) ((regs)->pc)
106 103
107#endif /* __KERNEL__ */ 104#endif /* __KERNEL__ */
108#endif /* _ASM_PTRACE_H */ 105#endif /* _ASM_PTRACE_H */
diff --git a/arch/mn10300/include/asm/reset-regs.h b/arch/mn10300/include/asm/reset-regs.h
index 174523d50132..10c7502a113f 100644
--- a/arch/mn10300/include/asm/reset-regs.h
+++ b/arch/mn10300/include/asm/reset-regs.h
@@ -50,7 +50,7 @@ static inline void mn10300_proc_hard_reset(void)
50 RSTCTR |= RSTCTR_CHIPRST; 50 RSTCTR |= RSTCTR_CHIPRST;
51} 51}
52 52
53extern unsigned int watchdog_alert_counter; 53extern unsigned int watchdog_alert_counter[];
54 54
55extern void watchdog_go(void); 55extern void watchdog_go(void);
56extern asmlinkage void watchdog_handler(void); 56extern asmlinkage void watchdog_handler(void);
diff --git a/arch/mn10300/include/asm/rtc.h b/arch/mn10300/include/asm/rtc.h
index c295194cc703..6c14bb1d0d9b 100644
--- a/arch/mn10300/include/asm/rtc.h
+++ b/arch/mn10300/include/asm/rtc.h
@@ -15,25 +15,14 @@
15 15
16#include <linux/init.h> 16#include <linux/init.h>
17 17
18extern void check_rtc_time(void);
19extern void __init calibrate_clock(void); 18extern void __init calibrate_clock(void);
20extern unsigned long __init get_initial_rtc_time(void);
21 19
22#else /* !CONFIG_MN10300_RTC */ 20#else /* !CONFIG_MN10300_RTC */
23 21
24static inline void check_rtc_time(void)
25{
26}
27
28static inline void calibrate_clock(void) 22static inline void calibrate_clock(void)
29{ 23{
30} 24}
31 25
32static inline unsigned long get_initial_rtc_time(void)
33{
34 return 0;
35}
36
37#endif /* !CONFIG_MN10300_RTC */ 26#endif /* !CONFIG_MN10300_RTC */
38 27
39#include <asm-generic/rtc.h> 28#include <asm-generic/rtc.h>
diff --git a/arch/mn10300/include/asm/rwlock.h b/arch/mn10300/include/asm/rwlock.h
new file mode 100644
index 000000000000..6d594d4a0e10
--- /dev/null
+++ b/arch/mn10300/include/asm/rwlock.h
@@ -0,0 +1,125 @@
1/*
2 * Helpers used by both rw spinlocks and rw semaphores.
3 *
4 * Based in part on code from semaphore.h and
5 * spinlock.h Copyright 1996 Linus Torvalds.
6 *
7 * Copyright 1999 Red Hat, Inc.
8 *
9 * Written by Benjamin LaHaise.
10 *
11 * Modified by Matsushita Electric Industrial Co., Ltd.
12 * Modifications:
13 * 13-Nov-2006 MEI Temporarily delete lock functions for SMP support.
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the Free
17 * Software Foundation; either version 2 of the License, or (at your option)
18 * any later version.
19 */
20#ifndef _ASM_RWLOCK_H
21#define _ASM_RWLOCK_H
22
23#define RW_LOCK_BIAS 0x01000000
24
25#ifndef CONFIG_SMP
26
27typedef struct { unsigned long a[100]; } __dummy_lock_t;
28#define __dummy_lock(lock) (*(__dummy_lock_t *)(lock))
29
30#define RW_LOCK_BIAS_STR "0x01000000"
31
32#define __build_read_lock_ptr(rw, helper) \
33 do { \
34 asm volatile( \
35 " mov (%0),d3 \n" \
36 " sub 1,d3 \n" \
37 " mov d3,(%0) \n" \
38 " blt 1f \n" \
39 " bra 2f \n" \
40 "1: jmp 3f \n" \
41 "2: \n" \
42 " .section .text.lock,\"ax\" \n" \
43 "3: call "helper"[],0 \n" \
44 " jmp 2b \n" \
45 " .previous" \
46 : \
47 : "d" (rw) \
48 : "memory", "d3", "cc"); \
49 } while (0)
50
51#define __build_read_lock_const(rw, helper) \
52 do { \
53 asm volatile( \
54 " mov (%0),d3 \n" \
55 " sub 1,d3 \n" \
56 " mov d3,(%0) \n" \
57 " blt 1f \n" \
58 " bra 2f \n" \
59 "1: jmp 3f \n" \
60 "2: \n" \
61 " .section .text.lock,\"ax\" \n" \
62 "3: call "helper"[],0 \n" \
63 " jmp 2b \n" \
64 " .previous" \
65 : \
66 : "d" (rw) \
67 : "memory", "d3", "cc"); \
68 } while (0)
69
70#define __build_read_lock(rw, helper) \
71 do { \
72 if (__builtin_constant_p(rw)) \
73 __build_read_lock_const(rw, helper); \
74 else \
75 __build_read_lock_ptr(rw, helper); \
76 } while (0)
77
78#define __build_write_lock_ptr(rw, helper) \
79 do { \
80 asm volatile( \
81 " mov (%0),d3 \n" \
82 " sub 1,d3 \n" \
83 " mov d3,(%0) \n" \
84 " blt 1f \n" \
85 " bra 2f \n" \
86 "1: jmp 3f \n" \
87 "2: \n" \
88 " .section .text.lock,\"ax\" \n" \
89 "3: call "helper"[],0 \n" \
90 " jmp 2b \n" \
91 " .previous" \
92 : \
93 : "d" (rw) \
94 : "memory", "d3", "cc"); \
95 } while (0)
96
97#define __build_write_lock_const(rw, helper) \
98 do { \
99 asm volatile( \
100 " mov (%0),d3 \n" \
101 " sub 1,d3 \n" \
102 " mov d3,(%0) \n" \
103 " blt 1f \n" \
104 " bra 2f \n" \
105 "1: jmp 3f \n" \
106 "2: \n" \
107 " .section .text.lock,\"ax\" \n" \
108 "3: call "helper"[],0 \n" \
109 " jmp 2b \n" \
110 " .previous" \
111 : \
112 : "d" (rw) \
113 : "memory", "d3", "cc"); \
114 } while (0)
115
116#define __build_write_lock(rw, helper) \
117 do { \
118 if (__builtin_constant_p(rw)) \
119 __build_write_lock_const(rw, helper); \
120 else \
121 __build_write_lock_ptr(rw, helper); \
122 } while (0)
123
124#endif /* CONFIG_SMP */
125#endif /* _ASM_RWLOCK_H */
diff --git a/arch/mn10300/include/asm/serial-regs.h b/arch/mn10300/include/asm/serial-regs.h
index 6498469e93ac..8320cda32f5a 100644
--- a/arch/mn10300/include/asm/serial-regs.h
+++ b/arch/mn10300/include/asm/serial-regs.h
@@ -20,18 +20,25 @@
20/* serial port 0 */ 20/* serial port 0 */
21#define SC0CTR __SYSREG(0xd4002000, u16) /* control reg */ 21#define SC0CTR __SYSREG(0xd4002000, u16) /* control reg */
22#define SC01CTR_CK 0x0007 /* clock source select */ 22#define SC01CTR_CK 0x0007 /* clock source select */
23#define SC0CTR_CK_TM8UFLOW_8 0x0000 /* - 1/8 timer 8 underflow (serial port 0 only) */
24#define SC1CTR_CK_TM9UFLOW_8 0x0000 /* - 1/8 timer 9 underflow (serial port 1 only) */
25#define SC01CTR_CK_IOCLK_8 0x0001 /* - 1/8 IOCLK */ 23#define SC01CTR_CK_IOCLK_8 0x0001 /* - 1/8 IOCLK */
26#define SC01CTR_CK_IOCLK_32 0x0002 /* - 1/32 IOCLK */ 24#define SC01CTR_CK_IOCLK_32 0x0002 /* - 1/32 IOCLK */
25#define SC01CTR_CK_EXTERN_8 0x0006 /* - 1/8 external closk */
26#define SC01CTR_CK_EXTERN 0x0007 /* - external closk */
27#if defined(CONFIG_AM33_2) || defined(CONFIG_AM33_3)
28#define SC0CTR_CK_TM8UFLOW_8 0x0000 /* - 1/8 timer 8 underflow (serial port 0 only) */
27#define SC0CTR_CK_TM2UFLOW_2 0x0003 /* - 1/2 timer 2 underflow (serial port 0 only) */ 29#define SC0CTR_CK_TM2UFLOW_2 0x0003 /* - 1/2 timer 2 underflow (serial port 0 only) */
28#define SC1CTR_CK_TM3UFLOW_2 0x0003 /* - 1/2 timer 3 underflow (serial port 1 only) */ 30#define SC0CTR_CK_TM0UFLOW_8 0x0004 /* - 1/8 timer 0 underflow (serial port 0 only) */
29#define SC0CTR_CK_TM0UFLOW_8 0x0004 /* - 1/8 timer 1 underflow (serial port 0 only) */
30#define SC1CTR_CK_TM1UFLOW_8 0x0004 /* - 1/8 timer 2 underflow (serial port 1 only) */
31#define SC0CTR_CK_TM2UFLOW_8 0x0005 /* - 1/8 timer 2 underflow (serial port 0 only) */ 31#define SC0CTR_CK_TM2UFLOW_8 0x0005 /* - 1/8 timer 2 underflow (serial port 0 only) */
32#define SC1CTR_CK_TM9UFLOW_8 0x0000 /* - 1/8 timer 9 underflow (serial port 1 only) */
33#define SC1CTR_CK_TM3UFLOW_2 0x0003 /* - 1/2 timer 3 underflow (serial port 1 only) */
34#define SC1CTR_CK_TM1UFLOW_8 0x0004 /* - 1/8 timer 1 underflow (serial port 1 only) */
32#define SC1CTR_CK_TM3UFLOW_8 0x0005 /* - 1/8 timer 3 underflow (serial port 1 only) */ 35#define SC1CTR_CK_TM3UFLOW_8 0x0005 /* - 1/8 timer 3 underflow (serial port 1 only) */
33#define SC01CTR_CK_EXTERN_8 0x0006 /* - 1/8 external closk */ 36#else /* CONFIG_AM33_2 || CONFIG_AM33_3 */
34#define SC01CTR_CK_EXTERN 0x0007 /* - external closk */ 37#define SC0CTR_CK_TM8UFLOW_8 0x0000 /* - 1/8 timer 8 underflow (serial port 0 only) */
38#define SC0CTR_CK_TM0UFLOW_8 0x0004 /* - 1/8 timer 0 underflow (serial port 0 only) */
39#define SC0CTR_CK_TM2UFLOW_8 0x0005 /* - 1/8 timer 2 underflow (serial port 0 only) */
40#define SC1CTR_CK_TM12UFLOW_8 0x0000 /* - 1/8 timer 12 underflow (serial port 1 only) */
41#endif /* CONFIG_AM33_2 || CONFIG_AM33_3 */
35#define SC01CTR_STB 0x0008 /* stop bit select */ 42#define SC01CTR_STB 0x0008 /* stop bit select */
36#define SC01CTR_STB_1BIT 0x0000 /* - 1 stop bit */ 43#define SC01CTR_STB_1BIT 0x0000 /* - 1 stop bit */
37#define SC01CTR_STB_2BIT 0x0008 /* - 2 stop bits */ 44#define SC01CTR_STB_2BIT 0x0008 /* - 2 stop bits */
@@ -100,11 +107,23 @@
100 107
101/* serial port 2 */ 108/* serial port 2 */
102#define SC2CTR __SYSREG(0xd4002020, u16) /* control reg */ 109#define SC2CTR __SYSREG(0xd4002020, u16) /* control reg */
110#ifdef CONFIG_AM33_2
103#define SC2CTR_CK 0x0003 /* clock source select */ 111#define SC2CTR_CK 0x0003 /* clock source select */
104#define SC2CTR_CK_TM10UFLOW 0x0000 /* - timer 10 underflow */ 112#define SC2CTR_CK_TM10UFLOW 0x0000 /* - timer 10 underflow */
105#define SC2CTR_CK_TM2UFLOW 0x0001 /* - timer 2 underflow */ 113#define SC2CTR_CK_TM2UFLOW 0x0001 /* - timer 2 underflow */
106#define SC2CTR_CK_EXTERN 0x0002 /* - external closk */ 114#define SC2CTR_CK_EXTERN 0x0002 /* - external closk */
107#define SC2CTR_CK_TM3UFLOW 0x0003 /* - timer 3 underflow */ 115#define SC2CTR_CK_TM3UFLOW 0x0003 /* - timer 3 underflow */
116#else /* CONFIG_AM33_2 */
117#define SC2CTR_CK 0x0007 /* clock source select */
118#define SC2CTR_CK_TM9UFLOW_8 0x0000 /* - 1/8 timer 9 underflow */
119#define SC2CTR_CK_IOCLK_8 0x0001 /* - 1/8 IOCLK */
120#define SC2CTR_CK_IOCLK_32 0x0002 /* - 1/32 IOCLK */
121#define SC2CTR_CK_TM3UFLOW_2 0x0003 /* - 1/2 timer 3 underflow */
122#define SC2CTR_CK_TM1UFLOW_8 0x0004 /* - 1/8 timer 1 underflow */
123#define SC2CTR_CK_TM3UFLOW_8 0x0005 /* - 1/8 timer 3 underflow */
124#define SC2CTR_CK_EXTERN_8 0x0006 /* - 1/8 external closk */
125#define SC2CTR_CK_EXTERN 0x0007 /* - external closk */
126#endif /* CONFIG_AM33_2 */
108#define SC2CTR_STB 0x0008 /* stop bit select */ 127#define SC2CTR_STB 0x0008 /* stop bit select */
109#define SC2CTR_STB_1BIT 0x0000 /* - 1 stop bit */ 128#define SC2CTR_STB_1BIT 0x0000 /* - 1 stop bit */
110#define SC2CTR_STB_2BIT 0x0008 /* - 2 stop bits */ 129#define SC2CTR_STB_2BIT 0x0008 /* - 2 stop bits */
@@ -134,9 +153,14 @@
134#define SC2ICR_RES 0x04 /* receive error select */ 153#define SC2ICR_RES 0x04 /* receive error select */
135#define SC2ICR_RI 0x01 /* receive interrupt cause */ 154#define SC2ICR_RI 0x01 /* receive interrupt cause */
136 155
137#define SC2TXB __SYSREG(0xd4002018, u8) /* transmit buffer reg */ 156#define SC2TXB __SYSREG(0xd4002028, u8) /* transmit buffer reg */
138#define SC2RXB __SYSREG(0xd4002019, u8) /* receive buffer reg */ 157#define SC2RXB __SYSREG(0xd4002029, u8) /* receive buffer reg */
139#define SC2STR __SYSREG(0xd400201c, u8) /* status reg */ 158
159#ifdef CONFIG_AM33_2
160#define SC2STR __SYSREG(0xd400202c, u8) /* status reg */
161#else /* CONFIG_AM33_2 */
162#define SC2STR __SYSREG(0xd400202c, u16) /* status reg */
163#endif /* CONFIG_AM33_2 */
140#define SC2STR_OEF 0x0001 /* overrun error found */ 164#define SC2STR_OEF 0x0001 /* overrun error found */
141#define SC2STR_PEF 0x0002 /* parity error found */ 165#define SC2STR_PEF 0x0002 /* parity error found */
142#define SC2STR_FEF 0x0004 /* framing error found */ 166#define SC2STR_FEF 0x0004 /* framing error found */
@@ -146,10 +170,17 @@
146#define SC2STR_RXF 0x0040 /* receive status */ 170#define SC2STR_RXF 0x0040 /* receive status */
147#define SC2STR_TXF 0x0080 /* transmit status */ 171#define SC2STR_TXF 0x0080 /* transmit status */
148 172
173#ifdef CONFIG_AM33_2
149#define SC2TIM __SYSREG(0xd400202d, u8) /* status reg */ 174#define SC2TIM __SYSREG(0xd400202d, u8) /* status reg */
175#endif
150 176
177#ifdef CONFIG_AM33_2
151#define SC2RXIRQ 24 /* serial 2 Receive IRQ */ 178#define SC2RXIRQ 24 /* serial 2 Receive IRQ */
152#define SC2TXIRQ 25 /* serial 2 Transmit IRQ */ 179#define SC2TXIRQ 25 /* serial 2 Transmit IRQ */
180#else /* CONFIG_AM33_2 */
181#define SC2RXIRQ 68 /* serial 2 Receive IRQ */
182#define SC2TXIRQ 69 /* serial 2 Transmit IRQ */
183#endif /* CONFIG_AM33_2 */
153 184
154#define SC2RXICR GxICR(SC2RXIRQ) /* serial 2 receive intr ctrl reg */ 185#define SC2RXICR GxICR(SC2RXIRQ) /* serial 2 receive intr ctrl reg */
155#define SC2TXICR GxICR(SC2TXIRQ) /* serial 2 transmit intr ctrl reg */ 186#define SC2TXICR GxICR(SC2TXIRQ) /* serial 2 transmit intr ctrl reg */
diff --git a/arch/mn10300/include/asm/serial.h b/arch/mn10300/include/asm/serial.h
index a29445cddd6f..23a799293599 100644
--- a/arch/mn10300/include/asm/serial.h
+++ b/arch/mn10300/include/asm/serial.h
@@ -9,10 +9,8 @@
9 * 2 of the Licence, or (at your option) any later version. 9 * 2 of the Licence, or (at your option) any later version.
10 */ 10 */
11 11
12/* 12#ifndef _ASM_SERIAL_H
13 * The ASB2305 has an 18.432 MHz clock the UART 13#define _ASM_SERIAL_H
14 */
15#define BASE_BAUD (18432000 / 16)
16 14
17/* Standard COM flags (except for COM4, because of the 8514 problem) */ 15/* Standard COM flags (except for COM4, because of the 8514 problem) */
18#ifdef CONFIG_SERIAL_DETECT_IRQ 16#ifdef CONFIG_SERIAL_DETECT_IRQ
@@ -34,3 +32,5 @@
34#endif 32#endif
35 33
36#include <unit/serial.h> 34#include <unit/serial.h>
35
36#endif /* _ASM_SERIAL_H */
diff --git a/arch/mn10300/include/asm/smp.h b/arch/mn10300/include/asm/smp.h
index 4eb8c61b7dab..b8585b4e8cdf 100644
--- a/arch/mn10300/include/asm/smp.h
+++ b/arch/mn10300/include/asm/smp.h
@@ -3,6 +3,16 @@
3 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. 3 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com) 4 * Written by David Howells (dhowells@redhat.com)
5 * 5 *
6 * Modified by Matsushita Electric Industrial Co., Ltd.
7 * Modifications:
8 * 13-Nov-2006 MEI Define IPI-IRQ number and add inline/macro function
9 * for SMP support.
10 * 22-Jan-2007 MEI Add the define related to SMP_BOOT_IRQ.
11 * 23-Feb-2007 MEI Add the define related to SMP icahce invalidate.
12 * 23-Jun-2008 MEI Delete INTC_IPI.
13 * 22-Jul-2008 MEI Add smp_nmi_call_function and related defines.
14 * 04-Aug-2008 MEI Delete USE_DOIRQ_CACHE_IPI.
15 *
6 * This program is free software; you can redistribute it and/or 16 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public Licence 17 * modify it under the terms of the GNU General Public Licence
8 * as published by the Free Software Foundation; either version 18 * as published by the Free Software Foundation; either version
@@ -11,8 +21,98 @@
11#ifndef _ASM_SMP_H 21#ifndef _ASM_SMP_H
12#define _ASM_SMP_H 22#define _ASM_SMP_H
13 23
24#ifndef __ASSEMBLY__
25#include <linux/threads.h>
26#include <linux/cpumask.h>
27#endif
28
14#ifdef CONFIG_SMP 29#ifdef CONFIG_SMP
15#error SMP not yet supported for MN10300 30#include <proc/smp-regs.h>
31
32#define RESCHEDULE_IPI 63
33#define CALL_FUNC_SINGLE_IPI 192
34#define LOCAL_TIMER_IPI 193
35#define FLUSH_CACHE_IPI 194
36#define CALL_FUNCTION_NMI_IPI 195
37#define GDB_NMI_IPI 196
38
39#define SMP_BOOT_IRQ 195
40
41#define RESCHEDULE_GxICR_LV GxICR_LEVEL_6
42#define CALL_FUNCTION_GxICR_LV GxICR_LEVEL_4
43#define LOCAL_TIMER_GxICR_LV GxICR_LEVEL_4
44#define FLUSH_CACHE_GxICR_LV GxICR_LEVEL_0
45#define SMP_BOOT_GxICR_LV GxICR_LEVEL_0
46
47#define TIME_OUT_COUNT_BOOT_IPI 100
48#define DELAY_TIME_BOOT_IPI 75000
49
50
51#ifndef __ASSEMBLY__
52
53/**
54 * raw_smp_processor_id - Determine the raw CPU ID of the CPU running it
55 *
56 * What we really want to do is to use the CPUID hardware CPU register to get
57 * this information, but accesses to that aren't cached, and run at system bus
58 * speed, not CPU speed. A copy of this value is, however, stored in the
59 * thread_info struct, and that can be cached.
60 *
61 * An alternate way of dealing with this could be to use the EPSW.S bits to
62 * cache this information for systems with up to four CPUs.
63 */
64#if 0
65#define raw_smp_processor_id() (CPUID)
66#else
67#define raw_smp_processor_id() (current_thread_info()->cpu)
16#endif 68#endif
17 69
70static inline int cpu_logical_map(int cpu)
71{
72 return cpu;
73}
74
75static inline int cpu_number_map(int cpu)
76{
77 return cpu;
78}
79
80
81extern cpumask_t cpu_boot_map;
82
83extern void smp_init_cpus(void);
84extern void smp_cache_interrupt(void);
85extern void send_IPI_allbutself(int irq);
86extern int smp_nmi_call_function(smp_call_func_t func, void *info, int wait);
87
88extern void arch_send_call_function_single_ipi(int cpu);
89extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
90
91#ifdef CONFIG_HOTPLUG_CPU
92extern int __cpu_disable(void);
93extern void __cpu_die(unsigned int cpu);
94#endif /* CONFIG_HOTPLUG_CPU */
95
96#ifdef CONFIG_PREEMPT /* FIXME */
97#define __frame \
98 ({ \
99 struct pt_regs *f; \
100 preempt_disable(); \
101 f = ___frame[CPUID]; \
102 preempt_enable(); \
103 f; \
104 })
105#else
106#define __frame ___frame[CPUID]
18#endif 107#endif
108
109#endif /* __ASSEMBLY__ */
110#else /* CONFIG_SMP */
111#ifndef __ASSEMBLY__
112
113static inline void smp_init_cpus(void) {}
114
115#endif /* __ASSEMBLY__ */
116#endif /* CONFIG_SMP */
117
118#endif /* _ASM_SMP_H */
diff --git a/arch/mn10300/include/asm/spinlock.h b/arch/mn10300/include/asm/spinlock.h
index 4bf9c8b169e0..93429154e898 100644
--- a/arch/mn10300/include/asm/spinlock.h
+++ b/arch/mn10300/include/asm/spinlock.h
@@ -11,6 +11,183 @@
11#ifndef _ASM_SPINLOCK_H 11#ifndef _ASM_SPINLOCK_H
12#define _ASM_SPINLOCK_H 12#define _ASM_SPINLOCK_H
13 13
14#error SMP spinlocks not implemented for MN10300 14#include <asm/atomic.h>
15#include <asm/rwlock.h>
16#include <asm/page.h>
15 17
18/*
19 * Simple spin lock operations. There are two variants, one clears IRQ's
20 * on the local processor, one does not.
21 *
22 * We make no fairness assumptions. They have a cost.
23 */
24
25#define arch_spin_is_locked(x) (*(volatile signed char *)(&(x)->slock) != 0)
26#define arch_spin_unlock_wait(x) do { barrier(); } while (arch_spin_is_locked(x))
27
28static inline void arch_spin_unlock(arch_spinlock_t *lock)
29{
30 asm volatile(
31 " bclr 1,(0,%0) \n"
32 :
33 : "a"(&lock->slock)
34 : "memory", "cc");
35}
36
37static inline int arch_spin_trylock(arch_spinlock_t *lock)
38{
39 int ret;
40
41 asm volatile(
42 " mov 1,%0 \n"
43 " bset %0,(%1) \n"
44 " bne 1f \n"
45 " clr %0 \n"
46 "1: xor 1,%0 \n"
47 : "=d"(ret)
48 : "a"(&lock->slock)
49 : "memory", "cc");
50
51 return ret;
52}
53
54static inline void arch_spin_lock(arch_spinlock_t *lock)
55{
56 asm volatile(
57 "1: bset 1,(0,%0) \n"
58 " bne 1b \n"
59 :
60 : "a"(&lock->slock)
61 : "memory", "cc");
62}
63
64static inline void arch_spin_lock_flags(arch_spinlock_t *lock,
65 unsigned long flags)
66{
67 int temp;
68
69 asm volatile(
70 "1: bset 1,(0,%2) \n"
71 " beq 3f \n"
72 " mov %1,epsw \n"
73 "2: mov (0,%2),%0 \n"
74 " or %0,%0 \n"
75 " bne 2b \n"
76 " mov %3,%0 \n"
77 " mov %0,epsw \n"
78 " nop \n"
79 " nop \n"
80 " bra 1b\n"
81 "3: \n"
82 : "=&d" (temp)
83 : "d" (flags), "a"(&lock->slock), "i"(EPSW_IE | MN10300_CLI_LEVEL)
84 : "memory", "cc");
85}
86
87#ifdef __KERNEL__
88
89/*
90 * Read-write spinlocks, allowing multiple readers
91 * but only one writer.
92 *
93 * NOTE! it is quite common to have readers in interrupts
94 * but no interrupt writers. For those circumstances we
95 * can "mix" irq-safe locks - any writer needs to get a
96 * irq-safe write-lock, but readers can get non-irqsafe
97 * read-locks.
98 */
99
100/**
101 * read_can_lock - would read_trylock() succeed?
102 * @lock: the rwlock in question.
103 */
104#define arch_read_can_lock(x) ((int)(x)->lock > 0)
105
106/**
107 * write_can_lock - would write_trylock() succeed?
108 * @lock: the rwlock in question.
109 */
110#define arch_write_can_lock(x) ((x)->lock == RW_LOCK_BIAS)
111
112/*
113 * On mn10300, we implement read-write locks as a 32-bit counter
114 * with the high bit (sign) being the "contended" bit.
115 */
116static inline void arch_read_lock(arch_rwlock_t *rw)
117{
118#if 0 //def CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT
119 __build_read_lock(rw, "__read_lock_failed");
120#else
121 {
122 atomic_t *count = (atomic_t *)rw;
123 while (atomic_dec_return(count) < 0)
124 atomic_inc(count);
125 }
126#endif
127}
128
129static inline void arch_write_lock(arch_rwlock_t *rw)
130{
131#if 0 //def CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT
132 __build_write_lock(rw, "__write_lock_failed");
133#else
134 {
135 atomic_t *count = (atomic_t *)rw;
136 while (!atomic_sub_and_test(RW_LOCK_BIAS, count))
137 atomic_add(RW_LOCK_BIAS, count);
138 }
139#endif
140}
141
142static inline void arch_read_unlock(arch_rwlock_t *rw)
143{
144#if 0 //def CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT
145 __build_read_unlock(rw);
146#else
147 {
148 atomic_t *count = (atomic_t *)rw;
149 atomic_inc(count);
150 }
151#endif
152}
153
154static inline void arch_write_unlock(arch_rwlock_t *rw)
155{
156#if 0 //def CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT
157 __build_write_unlock(rw);
158#else
159 {
160 atomic_t *count = (atomic_t *)rw;
161 atomic_add(RW_LOCK_BIAS, count);
162 }
163#endif
164}
165
166static inline int arch_read_trylock(arch_rwlock_t *lock)
167{
168 atomic_t *count = (atomic_t *)lock;
169 atomic_dec(count);
170 if (atomic_read(count) >= 0)
171 return 1;
172 atomic_inc(count);
173 return 0;
174}
175
176static inline int arch_write_trylock(arch_rwlock_t *lock)
177{
178 atomic_t *count = (atomic_t *)lock;
179 if (atomic_sub_and_test(RW_LOCK_BIAS, count))
180 return 1;
181 atomic_add(RW_LOCK_BIAS, count);
182 return 0;
183}
184
185#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
186#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
187
188#define _raw_spin_relax(lock) cpu_relax()
189#define _raw_read_relax(lock) cpu_relax()
190#define _raw_write_relax(lock) cpu_relax()
191
192#endif /* __KERNEL__ */
16#endif /* _ASM_SPINLOCK_H */ 193#endif /* _ASM_SPINLOCK_H */
diff --git a/arch/mn10300/include/asm/spinlock_types.h b/arch/mn10300/include/asm/spinlock_types.h
new file mode 100644
index 000000000000..653dc519b405
--- /dev/null
+++ b/arch/mn10300/include/asm/spinlock_types.h
@@ -0,0 +1,20 @@
1#ifndef _ASM_SPINLOCK_TYPES_H
2#define _ASM_SPINLOCK_TYPES_H
3
4#ifndef __LINUX_SPINLOCK_TYPES_H
5# error "please don't include this file directly"
6#endif
7
8typedef struct arch_spinlock {
9 unsigned int slock;
10} arch_spinlock_t;
11
12#define __ARCH_SPIN_LOCK_UNLOCKED { 0 }
13
14typedef struct {
15 unsigned int lock;
16} arch_rwlock_t;
17
18#define __ARCH_RW_LOCK_UNLOCKED { RW_LOCK_BIAS }
19
20#endif /* _ASM_SPINLOCK_TYPES_H */
diff --git a/arch/mn10300/include/asm/system.h b/arch/mn10300/include/asm/system.h
index 7de90bc4cf80..8ff3e5aaca41 100644
--- a/arch/mn10300/include/asm/system.h
+++ b/arch/mn10300/include/asm/system.h
@@ -12,6 +12,7 @@
12#define _ASM_SYSTEM_H 12#define _ASM_SYSTEM_H
13 13
14#include <asm/cpu-regs.h> 14#include <asm/cpu-regs.h>
15#include <asm/intctl-regs.h>
15 16
16#ifdef __KERNEL__ 17#ifdef __KERNEL__
17#ifndef __ASSEMBLY__ 18#ifndef __ASSEMBLY__
@@ -57,8 +58,6 @@ do { \
57 58
58#define nop() asm volatile ("nop") 59#define nop() asm volatile ("nop")
59 60
60#endif /* !__ASSEMBLY__ */
61
62/* 61/*
63 * Force strict CPU ordering. 62 * Force strict CPU ordering.
64 * And yes, this is required on UP too when we're talking 63 * And yes, this is required on UP too when we're talking
@@ -85,17 +84,19 @@ do { \
85#define smp_mb() mb() 84#define smp_mb() mb()
86#define smp_rmb() rmb() 85#define smp_rmb() rmb()
87#define smp_wmb() wmb() 86#define smp_wmb() wmb()
88#else 87#define set_mb(var, value) do { xchg(&var, value); } while (0)
88#else /* CONFIG_SMP */
89#define smp_mb() barrier() 89#define smp_mb() barrier()
90#define smp_rmb() barrier() 90#define smp_rmb() barrier()
91#define smp_wmb() barrier() 91#define smp_wmb() barrier()
92#endif
93
94#define set_mb(var, value) do { var = value; mb(); } while (0) 92#define set_mb(var, value) do { var = value; mb(); } while (0)
93#endif /* CONFIG_SMP */
94
95#define set_wmb(var, value) do { var = value; wmb(); } while (0) 95#define set_wmb(var, value) do { var = value; wmb(); } while (0)
96 96
97#define read_barrier_depends() do {} while (0) 97#define read_barrier_depends() do {} while (0)
98#define smp_read_barrier_depends() do {} while (0) 98#define smp_read_barrier_depends() do {} while (0)
99 99
100#endif /* !__ASSEMBLY__ */
100#endif /* __KERNEL__ */ 101#endif /* __KERNEL__ */
101#endif /* _ASM_SYSTEM_H */ 102#endif /* _ASM_SYSTEM_H */
diff --git a/arch/mn10300/include/asm/timer-regs.h b/arch/mn10300/include/asm/timer-regs.h
index 1d883b7f94ab..c634977caf66 100644
--- a/arch/mn10300/include/asm/timer-regs.h
+++ b/arch/mn10300/include/asm/timer-regs.h
@@ -17,21 +17,27 @@
17 17
18#ifdef __KERNEL__ 18#ifdef __KERNEL__
19 19
20/* timer prescalar control */ 20/*
21 * Timer prescalar control
22 */
21#define TMPSCNT __SYSREG(0xd4003071, u8) /* timer prescaler control */ 23#define TMPSCNT __SYSREG(0xd4003071, u8) /* timer prescaler control */
22#define TMPSCNT_ENABLE 0x80 /* timer prescaler enable */ 24#define TMPSCNT_ENABLE 0x80 /* timer prescaler enable */
23#define TMPSCNT_DISABLE 0x00 /* timer prescaler disable */ 25#define TMPSCNT_DISABLE 0x00 /* timer prescaler disable */
24 26
25/* 8 bit timers */ 27/*
28 * 8-bit timers
29 */
26#define TM0MD __SYSREG(0xd4003000, u8) /* timer 0 mode register */ 30#define TM0MD __SYSREG(0xd4003000, u8) /* timer 0 mode register */
27#define TM0MD_SRC 0x07 /* timer source */ 31#define TM0MD_SRC 0x07 /* timer source */
28#define TM0MD_SRC_IOCLK 0x00 /* - IOCLK */ 32#define TM0MD_SRC_IOCLK 0x00 /* - IOCLK */
29#define TM0MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ 33#define TM0MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
30#define TM0MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ 34#define TM0MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
31#define TM0MD_SRC_TM2IO 0x03 /* - TM2IO pin input */
32#define TM0MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ 35#define TM0MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
33#define TM0MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ 36#define TM0MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
37#if defined(CONFIG_AM33_2)
38#define TM0MD_SRC_TM2IO 0x03 /* - TM2IO pin input */
34#define TM0MD_SRC_TM0IO 0x07 /* - TM0IO pin input */ 39#define TM0MD_SRC_TM0IO 0x07 /* - TM0IO pin input */
40#endif /* CONFIG_AM33_2 */
35#define TM0MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ 41#define TM0MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
36#define TM0MD_COUNT_ENABLE 0x80 /* timer count enable */ 42#define TM0MD_COUNT_ENABLE 0x80 /* timer count enable */
37 43
@@ -43,7 +49,9 @@
43#define TM1MD_SRC_TM0CASCADE 0x03 /* - cascade with timer 0 */ 49#define TM1MD_SRC_TM0CASCADE 0x03 /* - cascade with timer 0 */
44#define TM1MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ 50#define TM1MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
45#define TM1MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ 51#define TM1MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
52#if defined(CONFIG_AM33_2)
46#define TM1MD_SRC_TM1IO 0x07 /* - TM1IO pin input */ 53#define TM1MD_SRC_TM1IO 0x07 /* - TM1IO pin input */
54#endif /* CONFIG_AM33_2 */
47#define TM1MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ 55#define TM1MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
48#define TM1MD_COUNT_ENABLE 0x80 /* timer count enable */ 56#define TM1MD_COUNT_ENABLE 0x80 /* timer count enable */
49 57
@@ -55,7 +63,9 @@
55#define TM2MD_SRC_TM1CASCADE 0x03 /* - cascade with timer 1 */ 63#define TM2MD_SRC_TM1CASCADE 0x03 /* - cascade with timer 1 */
56#define TM2MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ 64#define TM2MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
57#define TM2MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ 65#define TM2MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
66#if defined(CONFIG_AM33_2)
58#define TM2MD_SRC_TM2IO 0x07 /* - TM2IO pin input */ 67#define TM2MD_SRC_TM2IO 0x07 /* - TM2IO pin input */
68#endif /* CONFIG_AM33_2 */
59#define TM2MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ 69#define TM2MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
60#define TM2MD_COUNT_ENABLE 0x80 /* timer count enable */ 70#define TM2MD_COUNT_ENABLE 0x80 /* timer count enable */
61 71
@@ -64,11 +74,13 @@
64#define TM3MD_SRC_IOCLK 0x00 /* - IOCLK */ 74#define TM3MD_SRC_IOCLK 0x00 /* - IOCLK */
65#define TM3MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ 75#define TM3MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
66#define TM3MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ 76#define TM3MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
67#define TM3MD_SRC_TM1CASCADE 0x03 /* - cascade with timer 2 */ 77#define TM3MD_SRC_TM2CASCADE 0x03 /* - cascade with timer 2 */
68#define TM3MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ 78#define TM3MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
69#define TM3MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ 79#define TM3MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
70#define TM3MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ 80#define TM3MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
81#if defined(CONFIG_AM33_2)
71#define TM3MD_SRC_TM3IO 0x07 /* - TM3IO pin input */ 82#define TM3MD_SRC_TM3IO 0x07 /* - TM3IO pin input */
83#endif /* CONFIG_AM33_2 */
72#define TM3MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ 84#define TM3MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
73#define TM3MD_COUNT_ENABLE 0x80 /* timer count enable */ 85#define TM3MD_COUNT_ENABLE 0x80 /* timer count enable */
74 86
@@ -96,7 +108,9 @@
96#define TM2ICR GxICR(TM2IRQ) /* timer 2 uflow intr ctrl reg */ 108#define TM2ICR GxICR(TM2IRQ) /* timer 2 uflow intr ctrl reg */
97#define TM3ICR GxICR(TM3IRQ) /* timer 3 uflow intr ctrl reg */ 109#define TM3ICR GxICR(TM3IRQ) /* timer 3 uflow intr ctrl reg */
98 110
99/* 16-bit timers 4,5 & 7-11 */ 111/*
112 * 16-bit timers 4,5 & 7-15
113 */
100#define TM4MD __SYSREG(0xd4003080, u8) /* timer 4 mode register */ 114#define TM4MD __SYSREG(0xd4003080, u8) /* timer 4 mode register */
101#define TM4MD_SRC 0x07 /* timer source */ 115#define TM4MD_SRC 0x07 /* timer source */
102#define TM4MD_SRC_IOCLK 0x00 /* - IOCLK */ 116#define TM4MD_SRC_IOCLK 0x00 /* - IOCLK */
@@ -105,7 +119,9 @@
105#define TM4MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ 119#define TM4MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
106#define TM4MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ 120#define TM4MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
107#define TM4MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ 121#define TM4MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
122#if defined(CONFIG_AM33_2)
108#define TM4MD_SRC_TM4IO 0x07 /* - TM4IO pin input */ 123#define TM4MD_SRC_TM4IO 0x07 /* - TM4IO pin input */
124#endif /* CONFIG_AM33_2 */
109#define TM4MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ 125#define TM4MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
110#define TM4MD_COUNT_ENABLE 0x80 /* timer count enable */ 126#define TM4MD_COUNT_ENABLE 0x80 /* timer count enable */
111 127
@@ -118,7 +134,11 @@
118#define TM5MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ 134#define TM5MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
119#define TM5MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ 135#define TM5MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
120#define TM5MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ 136#define TM5MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
137#if defined(CONFIG_AM33_2)
121#define TM5MD_SRC_TM5IO 0x07 /* - TM5IO pin input */ 138#define TM5MD_SRC_TM5IO 0x07 /* - TM5IO pin input */
139#else /* !CONFIG_AM33_2 */
140#define TM5MD_SRC_TM7UFLOW 0x07 /* - timer 7 underflow */
141#endif /* CONFIG_AM33_2 */
122#define TM5MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ 142#define TM5MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
123#define TM5MD_COUNT_ENABLE 0x80 /* timer count enable */ 143#define TM5MD_COUNT_ENABLE 0x80 /* timer count enable */
124 144
@@ -130,7 +150,9 @@
130#define TM7MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ 150#define TM7MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
131#define TM7MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ 151#define TM7MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
132#define TM7MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ 152#define TM7MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
153#if defined(CONFIG_AM33_2)
133#define TM7MD_SRC_TM7IO 0x07 /* - TM7IO pin input */ 154#define TM7MD_SRC_TM7IO 0x07 /* - TM7IO pin input */
155#endif /* CONFIG_AM33_2 */
134#define TM7MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ 156#define TM7MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
135#define TM7MD_COUNT_ENABLE 0x80 /* timer count enable */ 157#define TM7MD_COUNT_ENABLE 0x80 /* timer count enable */
136 158
@@ -143,7 +165,11 @@
143#define TM8MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ 165#define TM8MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
144#define TM8MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ 166#define TM8MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
145#define TM8MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ 167#define TM8MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
168#if defined(CONFIG_AM33_2)
146#define TM8MD_SRC_TM8IO 0x07 /* - TM8IO pin input */ 169#define TM8MD_SRC_TM8IO 0x07 /* - TM8IO pin input */
170#else /* !CONFIG_AM33_2 */
171#define TM8MD_SRC_TM7UFLOW 0x07 /* - timer 7 underflow */
172#endif /* CONFIG_AM33_2 */
147#define TM8MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ 173#define TM8MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
148#define TM8MD_COUNT_ENABLE 0x80 /* timer count enable */ 174#define TM8MD_COUNT_ENABLE 0x80 /* timer count enable */
149 175
@@ -156,7 +182,11 @@
156#define TM9MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ 182#define TM9MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
157#define TM9MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ 183#define TM9MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
158#define TM9MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ 184#define TM9MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
185#if defined(CONFIG_AM33_2)
159#define TM9MD_SRC_TM9IO 0x07 /* - TM9IO pin input */ 186#define TM9MD_SRC_TM9IO 0x07 /* - TM9IO pin input */
187#else /* !CONFIG_AM33_2 */
188#define TM9MD_SRC_TM7UFLOW 0x07 /* - timer 7 underflow */
189#endif /* CONFIG_AM33_2 */
160#define TM9MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ 190#define TM9MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
161#define TM9MD_COUNT_ENABLE 0x80 /* timer count enable */ 191#define TM9MD_COUNT_ENABLE 0x80 /* timer count enable */
162 192
@@ -169,7 +199,11 @@
169#define TM10MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ 199#define TM10MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
170#define TM10MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ 200#define TM10MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
171#define TM10MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ 201#define TM10MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
202#if defined(CONFIG_AM33_2)
172#define TM10MD_SRC_TM10IO 0x07 /* - TM10IO pin input */ 203#define TM10MD_SRC_TM10IO 0x07 /* - TM10IO pin input */
204#else /* !CONFIG_AM33_2 */
205#define TM10MD_SRC_TM7UFLOW 0x07 /* - timer 7 underflow */
206#endif /* CONFIG_AM33_2 */
173#define TM10MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ 207#define TM10MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
174#define TM10MD_COUNT_ENABLE 0x80 /* timer count enable */ 208#define TM10MD_COUNT_ENABLE 0x80 /* timer count enable */
175 209
@@ -178,32 +212,101 @@
178#define TM11MD_SRC_IOCLK 0x00 /* - IOCLK */ 212#define TM11MD_SRC_IOCLK 0x00 /* - IOCLK */
179#define TM11MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ 213#define TM11MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
180#define TM11MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ 214#define TM11MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
181#define TM11MD_SRC_TM7CASCADE 0x03 /* - cascade with timer 7 */
182#define TM11MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ 215#define TM11MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
183#define TM11MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ 216#define TM11MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
184#define TM11MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ 217#define TM11MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
218#if defined(CONFIG_AM33_2)
185#define TM11MD_SRC_TM11IO 0x07 /* - TM11IO pin input */ 219#define TM11MD_SRC_TM11IO 0x07 /* - TM11IO pin input */
220#else /* !CONFIG_AM33_2 */
221#define TM11MD_SRC_TM7UFLOW 0x07 /* - timer 7 underflow */
222#endif /* CONFIG_AM33_2 */
186#define TM11MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ 223#define TM11MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
187#define TM11MD_COUNT_ENABLE 0x80 /* timer count enable */ 224#define TM11MD_COUNT_ENABLE 0x80 /* timer count enable */
188 225
226#if defined(CONFIG_AM34_2)
227#define TM12MD __SYSREG(0xd4003180, u8) /* timer 11 mode register */
228#define TM12MD_SRC 0x07 /* timer source */
229#define TM12MD_SRC_IOCLK 0x00 /* - IOCLK */
230#define TM12MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
231#define TM12MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
232#define TM12MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
233#define TM12MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
234#define TM12MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
235#define TM12MD_SRC_TM7UFLOW 0x07 /* - timer 7 underflow */
236#define TM12MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
237#define TM12MD_COUNT_ENABLE 0x80 /* timer count enable */
238
239#define TM13MD __SYSREG(0xd4003182, u8) /* timer 11 mode register */
240#define TM13MD_SRC 0x07 /* timer source */
241#define TM13MD_SRC_IOCLK 0x00 /* - IOCLK */
242#define TM13MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
243#define TM13MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
244#define TM13MD_SRC_TM12CASCADE 0x03 /* - cascade with timer 12 */
245#define TM13MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
246#define TM13MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
247#define TM13MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
248#define TM13MD_SRC_TM7UFLOW 0x07 /* - timer 7 underflow */
249#define TM13MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
250#define TM13MD_COUNT_ENABLE 0x80 /* timer count enable */
251
252#define TM14MD __SYSREG(0xd4003184, u8) /* timer 11 mode register */
253#define TM14MD_SRC 0x07 /* timer source */
254#define TM14MD_SRC_IOCLK 0x00 /* - IOCLK */
255#define TM14MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
256#define TM14MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
257#define TM14MD_SRC_TM13CASCADE 0x03 /* - cascade with timer 13 */
258#define TM14MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
259#define TM14MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
260#define TM14MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
261#define TM14MD_SRC_TM7UFLOW 0x07 /* - timer 7 underflow */
262#define TM14MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
263#define TM14MD_COUNT_ENABLE 0x80 /* timer count enable */
264
265#define TM15MD __SYSREG(0xd4003186, u8) /* timer 11 mode register */
266#define TM15MD_SRC 0x07 /* timer source */
267#define TM15MD_SRC_IOCLK 0x00 /* - IOCLK */
268#define TM15MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
269#define TM15MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
270#define TM15MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
271#define TM15MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
272#define TM15MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
273#define TM15MD_SRC_TM7UFLOW 0x07 /* - timer 7 underflow */
274#define TM15MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
275#define TM15MD_COUNT_ENABLE 0x80 /* timer count enable */
276#endif /* CONFIG_AM34_2 */
277
278
189#define TM4BR __SYSREG(0xd4003090, u16) /* timer 4 base register */ 279#define TM4BR __SYSREG(0xd4003090, u16) /* timer 4 base register */
190#define TM5BR __SYSREG(0xd4003092, u16) /* timer 5 base register */ 280#define TM5BR __SYSREG(0xd4003092, u16) /* timer 5 base register */
281#define TM45BR __SYSREG(0xd4003090, u32) /* timer 4:5 base register */
191#define TM7BR __SYSREG(0xd4003096, u16) /* timer 7 base register */ 282#define TM7BR __SYSREG(0xd4003096, u16) /* timer 7 base register */
192#define TM8BR __SYSREG(0xd4003098, u16) /* timer 8 base register */ 283#define TM8BR __SYSREG(0xd4003098, u16) /* timer 8 base register */
193#define TM9BR __SYSREG(0xd400309a, u16) /* timer 9 base register */ 284#define TM9BR __SYSREG(0xd400309a, u16) /* timer 9 base register */
285#define TM89BR __SYSREG(0xd4003098, u32) /* timer 8:9 base register */
194#define TM10BR __SYSREG(0xd400309c, u16) /* timer 10 base register */ 286#define TM10BR __SYSREG(0xd400309c, u16) /* timer 10 base register */
195#define TM11BR __SYSREG(0xd400309e, u16) /* timer 11 base register */ 287#define TM11BR __SYSREG(0xd400309e, u16) /* timer 11 base register */
196#define TM45BR __SYSREG(0xd4003090, u32) /* timer 4:5 base register */ 288#if defined(CONFIG_AM34_2)
289#define TM12BR __SYSREG(0xd4003190, u16) /* timer 12 base register */
290#define TM13BR __SYSREG(0xd4003192, u16) /* timer 13 base register */
291#define TM14BR __SYSREG(0xd4003194, u16) /* timer 14 base register */
292#define TM15BR __SYSREG(0xd4003196, u16) /* timer 15 base register */
293#endif /* CONFIG_AM34_2 */
197 294
198#define TM4BC __SYSREG(0xd40030a0, u16) /* timer 4 binary counter */ 295#define TM4BC __SYSREG(0xd40030a0, u16) /* timer 4 binary counter */
199#define TM5BC __SYSREG(0xd40030a2, u16) /* timer 5 binary counter */ 296#define TM5BC __SYSREG(0xd40030a2, u16) /* timer 5 binary counter */
200#define TM45BC __SYSREG(0xd40030a0, u32) /* timer 4:5 binary counter */ 297#define TM45BC __SYSREG(0xd40030a0, u32) /* timer 4:5 binary counter */
201
202#define TM7BC __SYSREG(0xd40030a6, u16) /* timer 7 binary counter */ 298#define TM7BC __SYSREG(0xd40030a6, u16) /* timer 7 binary counter */
203#define TM8BC __SYSREG(0xd40030a8, u16) /* timer 8 binary counter */ 299#define TM8BC __SYSREG(0xd40030a8, u16) /* timer 8 binary counter */
204#define TM9BC __SYSREG(0xd40030aa, u16) /* timer 9 binary counter */ 300#define TM9BC __SYSREG(0xd40030aa, u16) /* timer 9 binary counter */
301#define TM89BC __SYSREG(0xd40030a8, u32) /* timer 8:9 binary counter */
205#define TM10BC __SYSREG(0xd40030ac, u16) /* timer 10 binary counter */ 302#define TM10BC __SYSREG(0xd40030ac, u16) /* timer 10 binary counter */
206#define TM11BC __SYSREG(0xd40030ae, u16) /* timer 11 binary counter */ 303#define TM11BC __SYSREG(0xd40030ae, u16) /* timer 11 binary counter */
304#if defined(CONFIG_AM34_2)
305#define TM12BC __SYSREG(0xd40031a0, u16) /* timer 12 binary counter */
306#define TM13BC __SYSREG(0xd40031a2, u16) /* timer 13 binary counter */
307#define TM14BC __SYSREG(0xd40031a4, u16) /* timer 14 binary counter */
308#define TM15BC __SYSREG(0xd40031a6, u16) /* timer 15 binary counter */
309#endif /* CONFIG_AM34_2 */
207 310
208#define TM4IRQ 6 /* timer 4 IRQ */ 311#define TM4IRQ 6 /* timer 4 IRQ */
209#define TM5IRQ 7 /* timer 5 IRQ */ 312#define TM5IRQ 7 /* timer 5 IRQ */
@@ -212,6 +315,12 @@
212#define TM9IRQ 13 /* timer 9 IRQ */ 315#define TM9IRQ 13 /* timer 9 IRQ */
213#define TM10IRQ 14 /* timer 10 IRQ */ 316#define TM10IRQ 14 /* timer 10 IRQ */
214#define TM11IRQ 15 /* timer 11 IRQ */ 317#define TM11IRQ 15 /* timer 11 IRQ */
318#if defined(CONFIG_AM34_2)
319#define TM12IRQ 64 /* timer 12 IRQ */
320#define TM13IRQ 65 /* timer 13 IRQ */
321#define TM14IRQ 66 /* timer 14 IRQ */
322#define TM15IRQ 67 /* timer 15 IRQ */
323#endif /* CONFIG_AM34_2 */
215 324
216#define TM4ICR GxICR(TM4IRQ) /* timer 4 uflow intr ctrl reg */ 325#define TM4ICR GxICR(TM4IRQ) /* timer 4 uflow intr ctrl reg */
217#define TM5ICR GxICR(TM5IRQ) /* timer 5 uflow intr ctrl reg */ 326#define TM5ICR GxICR(TM5IRQ) /* timer 5 uflow intr ctrl reg */
@@ -220,8 +329,16 @@
220#define TM9ICR GxICR(TM9IRQ) /* timer 9 uflow intr ctrl reg */ 329#define TM9ICR GxICR(TM9IRQ) /* timer 9 uflow intr ctrl reg */
221#define TM10ICR GxICR(TM10IRQ) /* timer 10 uflow intr ctrl reg */ 330#define TM10ICR GxICR(TM10IRQ) /* timer 10 uflow intr ctrl reg */
222#define TM11ICR GxICR(TM11IRQ) /* timer 11 uflow intr ctrl reg */ 331#define TM11ICR GxICR(TM11IRQ) /* timer 11 uflow intr ctrl reg */
223 332#if defined(CONFIG_AM34_2)
224/* 16-bit timer 6 */ 333#define TM12ICR GxICR(TM12IRQ) /* timer 12 uflow intr ctrl reg */
334#define TM13ICR GxICR(TM13IRQ) /* timer 13 uflow intr ctrl reg */
335#define TM14ICR GxICR(TM14IRQ) /* timer 14 uflow intr ctrl reg */
336#define TM15ICR GxICR(TM15IRQ) /* timer 15 uflow intr ctrl reg */
337#endif /* CONFIG_AM34_2 */
338
339/*
340 * 16-bit timer 6
341 */
225#define TM6MD __SYSREG(0xd4003084, u16) /* timer6 mode register */ 342#define TM6MD __SYSREG(0xd4003084, u16) /* timer6 mode register */
226#define TM6MD_SRC 0x0007 /* timer source */ 343#define TM6MD_SRC 0x0007 /* timer source */
227#define TM6MD_SRC_IOCLK 0x0000 /* - IOCLK */ 344#define TM6MD_SRC_IOCLK 0x0000 /* - IOCLK */
@@ -229,10 +346,14 @@
229#define TM6MD_SRC_IOCLK_32 0x0002 /* - 1/32 IOCLK */ 346#define TM6MD_SRC_IOCLK_32 0x0002 /* - 1/32 IOCLK */
230#define TM6MD_SRC_TM0UFLOW 0x0004 /* - timer 0 underflow */ 347#define TM6MD_SRC_TM0UFLOW 0x0004 /* - timer 0 underflow */
231#define TM6MD_SRC_TM1UFLOW 0x0005 /* - timer 1 underflow */ 348#define TM6MD_SRC_TM1UFLOW 0x0005 /* - timer 1 underflow */
232#define TM6MD_SRC_TM6IOB_BOTH 0x0006 /* - TM6IOB pin input (both edges) */ 349#define TM6MD_SRC_TM2UFLOW 0x0006 /* - timer 2 underflow */
350#if defined(CONFIG_AM33_2)
351/* #define TM6MD_SRC_TM6IOB_BOTH 0x0006 */ /* - TM6IOB pin input (both edges) */
233#define TM6MD_SRC_TM6IOB_SINGLE 0x0007 /* - TM6IOB pin input (single edge) */ 352#define TM6MD_SRC_TM6IOB_SINGLE 0x0007 /* - TM6IOB pin input (single edge) */
234#define TM6MD_CLR_ENABLE 0x0010 /* clear count enable */ 353#endif /* CONFIG_AM33_2 */
235#define TM6MD_ONESHOT_ENABLE 0x0040 /* oneshot count */ 354#define TM6MD_ONESHOT_ENABLE 0x0040 /* oneshot count */
355#define TM6MD_CLR_ENABLE 0x0010 /* clear count enable */
356#if defined(CONFIG_AM33_2)
236#define TM6MD_TRIG_ENABLE 0x0080 /* TM6IOB pin trigger enable */ 357#define TM6MD_TRIG_ENABLE 0x0080 /* TM6IOB pin trigger enable */
237#define TM6MD_PWM 0x3800 /* PWM output mode */ 358#define TM6MD_PWM 0x3800 /* PWM output mode */
238#define TM6MD_PWM_DIS 0x0000 /* - disabled */ 359#define TM6MD_PWM_DIS 0x0000 /* - disabled */
@@ -240,10 +361,15 @@
240#define TM6MD_PWM_11BIT 0x1800 /* - 11 bits mode */ 361#define TM6MD_PWM_11BIT 0x1800 /* - 11 bits mode */
241#define TM6MD_PWM_12BIT 0x3000 /* - 12 bits mode */ 362#define TM6MD_PWM_12BIT 0x3000 /* - 12 bits mode */
242#define TM6MD_PWM_14BIT 0x3800 /* - 14 bits mode */ 363#define TM6MD_PWM_14BIT 0x3800 /* - 14 bits mode */
364#endif /* CONFIG_AM33_2 */
365
243#define TM6MD_INIT_COUNTER 0x4000 /* initialize TMnBC to zero */ 366#define TM6MD_INIT_COUNTER 0x4000 /* initialize TMnBC to zero */
244#define TM6MD_COUNT_ENABLE 0x8000 /* timer count enable */ 367#define TM6MD_COUNT_ENABLE 0x8000 /* timer count enable */
245 368
246#define TM6MDA __SYSREG(0xd40030b4, u8) /* timer6 cmp/cap A mode reg */ 369#define TM6MDA __SYSREG(0xd40030b4, u8) /* timer6 cmp/cap A mode reg */
370#define TM6MDA_MODE_CMP_SINGLE 0x00 /* - compare, single buffer mode */
371#define TM6MDA_MODE_CMP_DOUBLE 0x40 /* - compare, double buffer mode */
372#if defined(CONFIG_AM33_2)
247#define TM6MDA_OUT 0x07 /* output select */ 373#define TM6MDA_OUT 0x07 /* output select */
248#define TM6MDA_OUT_SETA_RESETB 0x00 /* - set at match A, reset at match B */ 374#define TM6MDA_OUT_SETA_RESETB 0x00 /* - set at match A, reset at match B */
249#define TM6MDA_OUT_SETA_RESETOV 0x01 /* - set at match A, reset at overflow */ 375#define TM6MDA_OUT_SETA_RESETOV 0x01 /* - set at match A, reset at overflow */
@@ -251,30 +377,35 @@
251#define TM6MDA_OUT_RESETA 0x03 /* - reset at match A */ 377#define TM6MDA_OUT_RESETA 0x03 /* - reset at match A */
252#define TM6MDA_OUT_TOGGLE 0x04 /* - toggle on match A */ 378#define TM6MDA_OUT_TOGGLE 0x04 /* - toggle on match A */
253#define TM6MDA_MODE 0xc0 /* compare A register mode */ 379#define TM6MDA_MODE 0xc0 /* compare A register mode */
254#define TM6MDA_MODE_CMP_SINGLE 0x00 /* - compare, single buffer mode */
255#define TM6MDA_MODE_CMP_DOUBLE 0x40 /* - compare, double buffer mode */
256#define TM6MDA_MODE_CAP_S_EDGE 0x80 /* - capture, single edge mode */ 380#define TM6MDA_MODE_CAP_S_EDGE 0x80 /* - capture, single edge mode */
257#define TM6MDA_MODE_CAP_D_EDGE 0xc0 /* - capture, double edge mode */ 381#define TM6MDA_MODE_CAP_D_EDGE 0xc0 /* - capture, double edge mode */
258#define TM6MDA_EDGE 0x20 /* compare A edge select */ 382#define TM6MDA_EDGE 0x20 /* compare A edge select */
259#define TM6MDA_EDGE_FALLING 0x00 /* capture on falling edge */ 383#define TM6MDA_EDGE_FALLING 0x00 /* capture on falling edge */
260#define TM6MDA_EDGE_RISING 0x20 /* capture on rising edge */ 384#define TM6MDA_EDGE_RISING 0x20 /* capture on rising edge */
261#define TM6MDA_CAPTURE_ENABLE 0x10 /* capture enable */ 385#define TM6MDA_CAPTURE_ENABLE 0x10 /* capture enable */
386#else /* !CONFIG_AM33_2 */
387#define TM6MDA_MODE 0x40 /* compare A register mode */
388#endif /* CONFIG_AM33_2 */
262 389
263#define TM6MDB __SYSREG(0xd40030b5, u8) /* timer6 cmp/cap B mode reg */ 390#define TM6MDB __SYSREG(0xd40030b5, u8) /* timer6 cmp/cap B mode reg */
391#define TM6MDB_MODE_CMP_SINGLE 0x00 /* - compare, single buffer mode */
392#define TM6MDB_MODE_CMP_DOUBLE 0x40 /* - compare, double buffer mode */
393#if defined(CONFIG_AM33_2)
264#define TM6MDB_OUT 0x07 /* output select */ 394#define TM6MDB_OUT 0x07 /* output select */
265#define TM6MDB_OUT_SETB_RESETA 0x00 /* - set at match B, reset at match A */ 395#define TM6MDB_OUT_SETB_RESETA 0x00 /* - set at match B, reset at match A */
266#define TM6MDB_OUT_SETB_RESETOV 0x01 /* - set at match B */ 396#define TM6MDB_OUT_SETB_RESETOV 0x01 /* - set at match B */
267#define TM6MDB_OUT_RESETB 0x03 /* - reset at match B */ 397#define TM6MDB_OUT_RESETB 0x03 /* - reset at match B */
268#define TM6MDB_OUT_TOGGLE 0x04 /* - toggle on match B */ 398#define TM6MDB_OUT_TOGGLE 0x04 /* - toggle on match B */
269#define TM6MDB_MODE 0xc0 /* compare B register mode */ 399#define TM6MDB_MODE 0xc0 /* compare B register mode */
270#define TM6MDB_MODE_CMP_SINGLE 0x00 /* - compare, single buffer mode */
271#define TM6MDB_MODE_CMP_DOUBLE 0x40 /* - compare, double buffer mode */
272#define TM6MDB_MODE_CAP_S_EDGE 0x80 /* - capture, single edge mode */ 400#define TM6MDB_MODE_CAP_S_EDGE 0x80 /* - capture, single edge mode */
273#define TM6MDB_MODE_CAP_D_EDGE 0xc0 /* - capture, double edge mode */ 401#define TM6MDB_MODE_CAP_D_EDGE 0xc0 /* - capture, double edge mode */
274#define TM6MDB_EDGE 0x20 /* compare B edge select */ 402#define TM6MDB_EDGE 0x20 /* compare B edge select */
275#define TM6MDB_EDGE_FALLING 0x00 /* capture on falling edge */ 403#define TM6MDB_EDGE_FALLING 0x00 /* capture on falling edge */
276#define TM6MDB_EDGE_RISING 0x20 /* capture on rising edge */ 404#define TM6MDB_EDGE_RISING 0x20 /* capture on rising edge */
277#define TM6MDB_CAPTURE_ENABLE 0x10 /* capture enable */ 405#define TM6MDB_CAPTURE_ENABLE 0x10 /* capture enable */
406#else /* !CONFIG_AM33_2 */
407#define TM6MDB_MODE 0x40 /* compare B register mode */
408#endif /* CONFIG_AM33_2 */
278 409
279#define TM6CA __SYSREG(0xd40030c4, u16) /* timer6 cmp/capture reg A */ 410#define TM6CA __SYSREG(0xd40030c4, u16) /* timer6 cmp/capture reg A */
280#define TM6CB __SYSREG(0xd40030d4, u16) /* timer6 cmp/capture reg B */ 411#define TM6CB __SYSREG(0xd40030d4, u16) /* timer6 cmp/capture reg B */
@@ -288,6 +419,34 @@
288#define TM6AICR GxICR(TM6AIRQ) /* timer 6A intr control reg */ 419#define TM6AICR GxICR(TM6AIRQ) /* timer 6A intr control reg */
289#define TM6BICR GxICR(TM6BIRQ) /* timer 6B intr control reg */ 420#define TM6BICR GxICR(TM6BIRQ) /* timer 6B intr control reg */
290 421
422#if defined(CONFIG_AM34_2)
423/*
424 * MTM: OS Tick-Timer
425 */
426#define TMTMD __SYSREG(0xd4004100, u8) /* Tick Timer mode register */
427#define TMTMD_TMTLDE 0x40 /* initialize TMTBC = TMTBR */
428#define TMTMD_TMTCNE 0x80 /* timer count enable */
429
430#define TMTBR __SYSREG(0xd4004110, u32) /* Tick Timer mode reg */
431#define TMTBC __SYSREG(0xd4004120, u32) /* Tick Timer mode reg */
432
433/*
434 * MTM: OS Timestamp-Timer
435 */
436#define TMSMD __SYSREG(0xd4004140, u8) /* Tick Timer mode register */
437#define TMSMD_TMSLDE 0x40 /* initialize TMSBC = TMSBR */
438#define TMSMD_TMSCNE 0x80 /* timer count enable */
439
440#define TMSBR __SYSREG(0xd4004150, u32) /* Tick Timer mode register */
441#define TMSBC __SYSREG(0xd4004160, u32) /* Tick Timer mode register */
442
443#define TMTIRQ 119 /* OS Tick timer IRQ */
444#define TMSIRQ 120 /* Timestamp timer IRQ */
445
446#define TMTICR GxICR(TMTIRQ) /* OS Tick timer uflow intr ctrl reg */
447#define TMSICR GxICR(TMSIRQ) /* Timestamp timer uflow intr ctrl reg */
448#endif /* CONFIG_AM34_2 */
449
291#endif /* __KERNEL__ */ 450#endif /* __KERNEL__ */
292 451
293#endif /* _ASM_TIMER_REGS_H */ 452#endif /* _ASM_TIMER_REGS_H */
diff --git a/arch/mn10300/include/asm/timex.h b/arch/mn10300/include/asm/timex.h
index 8d031f9e117d..ce5719a2ce7c 100644
--- a/arch/mn10300/include/asm/timex.h
+++ b/arch/mn10300/include/asm/timex.h
@@ -16,8 +16,7 @@
16 16
17#define TICK_SIZE (tick_nsec / 1000) 17#define TICK_SIZE (tick_nsec / 1000)
18 18
19#define CLOCK_TICK_RATE 1193180 /* Underlying HZ - this should probably be set 19#define CLOCK_TICK_RATE MN10300_JCCLK /* Underlying HZ */
20 * to something appropriate, but what? */
21 20
22extern cycles_t cacheflush_time; 21extern cycles_t cacheflush_time;
23 22
diff --git a/arch/mn10300/include/asm/uaccess.h b/arch/mn10300/include/asm/uaccess.h
index 197a7af3dd8a..47e7951e6893 100644
--- a/arch/mn10300/include/asm/uaccess.h
+++ b/arch/mn10300/include/asm/uaccess.h
@@ -377,7 +377,7 @@ unsigned long __generic_copy_to_user_nocheck(void *to, const void *from,
377 377
378 378
379#if 0 379#if 0
380#error don't use - these macros don't increment to & from pointers 380#error "don't use - these macros don't increment to & from pointers"
381/* Optimize just a little bit when we know the size of the move. */ 381/* Optimize just a little bit when we know the size of the move. */
382#define __constant_copy_user(to, from, size) \ 382#define __constant_copy_user(to, from, size) \
383do { \ 383do { \
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-03 19:33:21 -0500